cf-fsi-fw.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. #ifndef __CF_FSI_FW_H
  3. #define __CF_FSI_FW_H
  4. /*
  5. * uCode file layout
  6. *
  7. * 0000...03ff : m68k exception vectors
  8. * 0400...04ff : Header info & boot config block
  9. * 0500....... : Code & stack
  10. */
  11. /*
  12. * Header info & boot config area
  13. *
  14. * The Header info is built into the ucode and provide version and
  15. * platform information.
  16. *
  17. * the Boot config needs to be adjusted by the ARM prior to starting
  18. * the ucode if the Command/Status area isn't at 0x320000 in CF space
  19. * (ie. beginning of SRAM).
  20. */
  21. #define HDR_OFFSET 0x400
  22. /* Info: Signature & version */
  23. #define HDR_SYS_SIG 0x00 /* 2 bytes system signature */
  24. #define SYS_SIG_SHARED 0x5348
  25. #define SYS_SIG_SPLIT 0x5350
  26. #define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */
  27. #define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */
  28. #define API_VERSION_MAJ 2 /* Current version */
  29. #define API_VERSION_MIN 1
  30. #define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */
  31. #define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */
  32. #define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */
  33. #define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */
  34. /* Boot Config: Address of Command/Status area */
  35. #define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */
  36. #define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */
  37. #define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */
  38. #define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
  39. #define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */
  40. #define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
  41. #define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
  42. #define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
  43. #define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
  44. #define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
  45. #define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
  46. #define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */
  47. #define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */
  48. #define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */
  49. /*
  50. * Command/Status area layout: Main part
  51. */
  52. /* Command/Status register:
  53. *
  54. * +---------------------------+
  55. * | STAT | RLEN | CLEN | CMD |
  56. * | 8 | 8 | 8 | 8 |
  57. * +---------------------------+
  58. * | | | |
  59. * status | | |
  60. * Response len | |
  61. * (in bits) | |
  62. * | |
  63. * Command len |
  64. * (in bits) |
  65. * |
  66. * Command code
  67. *
  68. * Due to the big endian layout, that means that a byte read will
  69. * return the status byte
  70. */
  71. #define CMD_STAT_REG 0x00
  72. #define CMD_REG_CMD_MASK 0x000000ff
  73. #define CMD_REG_CMD_SHIFT 0
  74. #define CMD_NONE 0x00
  75. #define CMD_COMMAND 0x01
  76. #define CMD_BREAK 0x02
  77. #define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */
  78. #define CMD_INVALID 0xff
  79. #define CMD_REG_CLEN_MASK 0x0000ff00
  80. #define CMD_REG_CLEN_SHIFT 8
  81. #define CMD_REG_RLEN_MASK 0x00ff0000
  82. #define CMD_REG_RLEN_SHIFT 16
  83. #define CMD_REG_STAT_MASK 0xff000000
  84. #define CMD_REG_STAT_SHIFT 24
  85. #define STAT_WORKING 0x00
  86. #define STAT_COMPLETE 0x01
  87. #define STAT_ERR_INVAL_CMD 0x80
  88. #define STAT_ERR_INVAL_IRQ 0x81
  89. #define STAT_ERR_MTOE 0x82
  90. /* Response tag & CRC */
  91. #define STAT_RTAG 0x04
  92. /* Response CRC */
  93. #define STAT_RCRC 0x05
  94. /* Echo and Send delay */
  95. #define ECHO_DLY_REG 0x08
  96. #define SEND_DLY_REG 0x09
  97. /* Command data area
  98. *
  99. * Last byte of message must be left aligned
  100. */
  101. #define CMD_DATA 0x10 /* 64 bit of data */
  102. /* Response data area, right aligned, unused top bits are 1 */
  103. #define RSP_DATA 0x20 /* 32 bit of data */
  104. /* Misc */
  105. #define INT_CNT 0x30 /* 32-bit interrupt count */
  106. #define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */
  107. #define CF_STARTED 0x38 /* byte, set to -1 when copro started */
  108. #define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */
  109. /*
  110. * SRAM layout: GPIO arbitration part
  111. */
  112. #define ARB_REG 0x40
  113. #define ARB_ARM_REQ 0x01
  114. #define ARB_ARM_ACK 0x02
  115. /* Misc2 */
  116. #define CF_RESET_D0 0x50
  117. #define CF_RESET_D1 0x54
  118. #define BAD_INT_S0 0x58
  119. #define BAD_INT_S1 0x5c
  120. #define STOP_CNT 0x60
  121. /* Internal */
  122. /*
  123. * SRAM layout: Trace buffer (debug builds only)
  124. */
  125. #define TRACEBUF 0x100
  126. #define TR_CLKOBIT0 0xc0
  127. #define TR_CLKOBIT1 0xc1
  128. #define TR_CLKOSTART 0x82
  129. #define TR_OLEN 0x83 /* + len */
  130. #define TR_CLKZ 0x84 /* + count */
  131. #define TR_CLKWSTART 0x85
  132. #define TR_CLKTAG 0x86 /* + tag */
  133. #define TR_CLKDATA 0x87 /* + len */
  134. #define TR_CLKCRC 0x88 /* + raw crc */
  135. #define TR_CLKIBIT0 0x90
  136. #define TR_CLKIBIT1 0x91
  137. #define TR_END 0xff
  138. #endif /* __CF_FSI_FW_H */