stratix10-soc.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA Manager Driver for Intel Stratix10 SoC
  4. *
  5. * Copyright (C) 2018 Intel Corporation
  6. */
  7. #include <linux/completion.h>
  8. #include <linux/fpga/fpga-mgr.h>
  9. #include <linux/firmware/intel/stratix10-svc-client.h>
  10. #include <linux/module.h>
  11. #include <linux/of.h>
  12. #include <linux/of_platform.h>
  13. /*
  14. * FPGA programming requires a higher level of privilege (EL3), per the SoC
  15. * design.
  16. */
  17. #define NUM_SVC_BUFS 4
  18. #define SVC_BUF_SIZE SZ_512K
  19. /* Indicates buffer is in use if set */
  20. #define SVC_BUF_LOCK 0
  21. #define S10_BUFFER_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_BUFFER_TIMEOUT_MS))
  22. #define S10_RECONFIG_TIMEOUT (msecs_to_jiffies(SVC_RECONFIG_REQUEST_TIMEOUT_MS))
  23. /*
  24. * struct s10_svc_buf
  25. * buf: virtual address of buf provided by service layer
  26. * lock: locked if buffer is in use
  27. */
  28. struct s10_svc_buf {
  29. char *buf;
  30. unsigned long lock;
  31. };
  32. struct s10_priv {
  33. struct stratix10_svc_chan *chan;
  34. struct stratix10_svc_client client;
  35. struct completion status_return_completion;
  36. struct s10_svc_buf svc_bufs[NUM_SVC_BUFS];
  37. unsigned long status;
  38. };
  39. static int s10_svc_send_msg(struct s10_priv *priv,
  40. enum stratix10_svc_command_code command,
  41. void *payload, u32 payload_length)
  42. {
  43. struct stratix10_svc_chan *chan = priv->chan;
  44. struct device *dev = priv->client.dev;
  45. struct stratix10_svc_client_msg msg;
  46. int ret;
  47. dev_dbg(dev, "%s cmd=%d payload=%p length=%d\n",
  48. __func__, command, payload, payload_length);
  49. msg.command = command;
  50. msg.payload = payload;
  51. msg.payload_length = payload_length;
  52. ret = stratix10_svc_send(chan, &msg);
  53. dev_dbg(dev, "stratix10_svc_send returned status %d\n", ret);
  54. return ret;
  55. }
  56. /*
  57. * Free buffers allocated from the service layer's pool that are not in use.
  58. * Return true when all buffers are freed.
  59. */
  60. static bool s10_free_buffers(struct fpga_manager *mgr)
  61. {
  62. struct s10_priv *priv = mgr->priv;
  63. uint num_free = 0;
  64. uint i;
  65. for (i = 0; i < NUM_SVC_BUFS; i++) {
  66. if (!priv->svc_bufs[i].buf) {
  67. num_free++;
  68. continue;
  69. }
  70. if (!test_and_set_bit_lock(SVC_BUF_LOCK,
  71. &priv->svc_bufs[i].lock)) {
  72. stratix10_svc_free_memory(priv->chan,
  73. priv->svc_bufs[i].buf);
  74. priv->svc_bufs[i].buf = NULL;
  75. num_free++;
  76. }
  77. }
  78. return num_free == NUM_SVC_BUFS;
  79. }
  80. /*
  81. * Returns count of how many buffers are not in use.
  82. */
  83. static uint s10_free_buffer_count(struct fpga_manager *mgr)
  84. {
  85. struct s10_priv *priv = mgr->priv;
  86. uint num_free = 0;
  87. uint i;
  88. for (i = 0; i < NUM_SVC_BUFS; i++)
  89. if (!priv->svc_bufs[i].buf)
  90. num_free++;
  91. return num_free;
  92. }
  93. /*
  94. * s10_unlock_bufs
  95. * Given the returned buffer address, match that address to our buffer struct
  96. * and unlock that buffer. This marks it as available to be refilled and sent
  97. * (or freed).
  98. * priv: private data
  99. * kaddr: kernel address of buffer that was returned from service layer
  100. */
  101. static void s10_unlock_bufs(struct s10_priv *priv, void *kaddr)
  102. {
  103. uint i;
  104. if (!kaddr)
  105. return;
  106. for (i = 0; i < NUM_SVC_BUFS; i++)
  107. if (priv->svc_bufs[i].buf == kaddr) {
  108. clear_bit_unlock(SVC_BUF_LOCK,
  109. &priv->svc_bufs[i].lock);
  110. return;
  111. }
  112. WARN(1, "Unknown buffer returned from service layer %p\n", kaddr);
  113. }
  114. /*
  115. * s10_receive_callback - callback for service layer to use to provide client
  116. * (this driver) messages received through the mailbox.
  117. * client: service layer client struct
  118. * data: message from service layer
  119. */
  120. static void s10_receive_callback(struct stratix10_svc_client *client,
  121. struct stratix10_svc_cb_data *data)
  122. {
  123. struct s10_priv *priv = client->priv;
  124. u32 status;
  125. int i;
  126. WARN_ONCE(!data, "%s: stratix10_svc_rc_data = NULL", __func__);
  127. status = data->status;
  128. /*
  129. * Here we set status bits as we receive them. Elsewhere, we always use
  130. * test_and_clear_bit() to check status in priv->status
  131. */
  132. for (i = 0; i <= SVC_STATUS_ERROR; i++)
  133. if (status & (1 << i))
  134. set_bit(i, &priv->status);
  135. if (status & BIT(SVC_STATUS_BUFFER_DONE)) {
  136. s10_unlock_bufs(priv, data->kaddr1);
  137. s10_unlock_bufs(priv, data->kaddr2);
  138. s10_unlock_bufs(priv, data->kaddr3);
  139. }
  140. complete(&priv->status_return_completion);
  141. }
  142. /*
  143. * s10_ops_write_init - prepare for FPGA reconfiguration by requesting
  144. * partial reconfig and allocating buffers from the service layer.
  145. */
  146. static int s10_ops_write_init(struct fpga_manager *mgr,
  147. struct fpga_image_info *info,
  148. const char *buf, size_t count)
  149. {
  150. struct s10_priv *priv = mgr->priv;
  151. struct device *dev = priv->client.dev;
  152. struct stratix10_svc_command_config_type ctype;
  153. char *kbuf;
  154. uint i;
  155. int ret;
  156. ctype.flags = 0;
  157. if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
  158. dev_dbg(dev, "Requesting partial reconfiguration.\n");
  159. ctype.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL);
  160. } else {
  161. dev_dbg(dev, "Requesting full reconfiguration.\n");
  162. }
  163. reinit_completion(&priv->status_return_completion);
  164. ret = s10_svc_send_msg(priv, COMMAND_RECONFIG,
  165. &ctype, sizeof(ctype));
  166. if (ret < 0)
  167. goto init_done;
  168. ret = wait_for_completion_timeout(
  169. &priv->status_return_completion, S10_RECONFIG_TIMEOUT);
  170. if (!ret) {
  171. dev_err(dev, "timeout waiting for RECONFIG_REQUEST\n");
  172. ret = -ETIMEDOUT;
  173. goto init_done;
  174. }
  175. ret = 0;
  176. if (!test_and_clear_bit(SVC_STATUS_OK, &priv->status)) {
  177. ret = -ETIMEDOUT;
  178. goto init_done;
  179. }
  180. /* Allocate buffers from the service layer's pool. */
  181. for (i = 0; i < NUM_SVC_BUFS; i++) {
  182. kbuf = stratix10_svc_allocate_memory(priv->chan, SVC_BUF_SIZE);
  183. if (!kbuf) {
  184. s10_free_buffers(mgr);
  185. ret = -ENOMEM;
  186. goto init_done;
  187. }
  188. priv->svc_bufs[i].buf = kbuf;
  189. priv->svc_bufs[i].lock = 0;
  190. }
  191. init_done:
  192. stratix10_svc_done(priv->chan);
  193. return ret;
  194. }
  195. /*
  196. * s10_send_buf - send a buffer to the service layer queue
  197. * mgr: fpga manager struct
  198. * buf: fpga image buffer
  199. * count: size of buf in bytes
  200. * Returns # of bytes transferred or -ENOBUFS if the all the buffers are in use
  201. * or if the service queue is full. Never returns 0.
  202. */
  203. static int s10_send_buf(struct fpga_manager *mgr, const char *buf, size_t count)
  204. {
  205. struct s10_priv *priv = mgr->priv;
  206. struct device *dev = priv->client.dev;
  207. void *svc_buf;
  208. size_t xfer_sz;
  209. int ret;
  210. uint i;
  211. /* get/lock a buffer that that's not being used */
  212. for (i = 0; i < NUM_SVC_BUFS; i++)
  213. if (!test_and_set_bit_lock(SVC_BUF_LOCK,
  214. &priv->svc_bufs[i].lock))
  215. break;
  216. if (i == NUM_SVC_BUFS)
  217. return -ENOBUFS;
  218. xfer_sz = count < SVC_BUF_SIZE ? count : SVC_BUF_SIZE;
  219. svc_buf = priv->svc_bufs[i].buf;
  220. memcpy(svc_buf, buf, xfer_sz);
  221. ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_DATA_SUBMIT,
  222. svc_buf, xfer_sz);
  223. if (ret < 0) {
  224. dev_err(dev,
  225. "Error while sending data to service layer (%d)", ret);
  226. clear_bit_unlock(SVC_BUF_LOCK, &priv->svc_bufs[i].lock);
  227. return ret;
  228. }
  229. return xfer_sz;
  230. }
  231. /*
  232. * Send a FPGA image to privileged layers to write to the FPGA. When done
  233. * sending, free all service layer buffers we allocated in write_init.
  234. */
  235. static int s10_ops_write(struct fpga_manager *mgr, const char *buf,
  236. size_t count)
  237. {
  238. struct s10_priv *priv = mgr->priv;
  239. struct device *dev = priv->client.dev;
  240. long wait_status;
  241. int sent = 0;
  242. int ret = 0;
  243. /*
  244. * Loop waiting for buffers to be returned. When a buffer is returned,
  245. * reuse it to send more data or free if if all data has been sent.
  246. */
  247. while (count > 0 || s10_free_buffer_count(mgr) != NUM_SVC_BUFS) {
  248. reinit_completion(&priv->status_return_completion);
  249. if (count > 0) {
  250. sent = s10_send_buf(mgr, buf, count);
  251. if (sent < 0)
  252. continue;
  253. count -= sent;
  254. buf += sent;
  255. } else {
  256. if (s10_free_buffers(mgr))
  257. return 0;
  258. ret = s10_svc_send_msg(
  259. priv, COMMAND_RECONFIG_DATA_CLAIM,
  260. NULL, 0);
  261. if (ret < 0)
  262. break;
  263. }
  264. /*
  265. * If callback hasn't already happened, wait for buffers to be
  266. * returned from service layer
  267. */
  268. wait_status = 1; /* not timed out */
  269. if (!priv->status)
  270. wait_status = wait_for_completion_timeout(
  271. &priv->status_return_completion,
  272. S10_BUFFER_TIMEOUT);
  273. if (test_and_clear_bit(SVC_STATUS_BUFFER_DONE, &priv->status) ||
  274. test_and_clear_bit(SVC_STATUS_BUFFER_SUBMITTED,
  275. &priv->status)) {
  276. ret = 0;
  277. continue;
  278. }
  279. if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) {
  280. dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n");
  281. ret = -EFAULT;
  282. break;
  283. }
  284. if (!wait_status) {
  285. dev_err(dev, "timeout waiting for svc layer buffers\n");
  286. ret = -ETIMEDOUT;
  287. break;
  288. }
  289. }
  290. if (!s10_free_buffers(mgr))
  291. dev_err(dev, "%s not all buffers were freed\n", __func__);
  292. return ret;
  293. }
  294. static int s10_ops_write_complete(struct fpga_manager *mgr,
  295. struct fpga_image_info *info)
  296. {
  297. struct s10_priv *priv = mgr->priv;
  298. struct device *dev = priv->client.dev;
  299. unsigned long timeout;
  300. int ret;
  301. timeout = usecs_to_jiffies(info->config_complete_timeout_us);
  302. do {
  303. reinit_completion(&priv->status_return_completion);
  304. ret = s10_svc_send_msg(priv, COMMAND_RECONFIG_STATUS, NULL, 0);
  305. if (ret < 0)
  306. break;
  307. ret = wait_for_completion_timeout(
  308. &priv->status_return_completion, timeout);
  309. if (!ret) {
  310. dev_err(dev,
  311. "timeout waiting for RECONFIG_COMPLETED\n");
  312. ret = -ETIMEDOUT;
  313. break;
  314. }
  315. /* Not error or timeout, so ret is # of jiffies until timeout */
  316. timeout = ret;
  317. ret = 0;
  318. if (test_and_clear_bit(SVC_STATUS_COMPLETED, &priv->status))
  319. break;
  320. if (test_and_clear_bit(SVC_STATUS_ERROR, &priv->status)) {
  321. dev_err(dev, "ERROR - giving up - SVC_STATUS_ERROR\n");
  322. ret = -EFAULT;
  323. break;
  324. }
  325. } while (1);
  326. stratix10_svc_done(priv->chan);
  327. return ret;
  328. }
  329. static enum fpga_mgr_states s10_ops_state(struct fpga_manager *mgr)
  330. {
  331. return FPGA_MGR_STATE_UNKNOWN;
  332. }
  333. static const struct fpga_manager_ops s10_ops = {
  334. .state = s10_ops_state,
  335. .write_init = s10_ops_write_init,
  336. .write = s10_ops_write,
  337. .write_complete = s10_ops_write_complete,
  338. };
  339. static int s10_probe(struct platform_device *pdev)
  340. {
  341. struct device *dev = &pdev->dev;
  342. struct s10_priv *priv;
  343. struct fpga_manager *mgr;
  344. int ret;
  345. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  346. if (!priv)
  347. return -ENOMEM;
  348. priv->client.dev = dev;
  349. priv->client.receive_cb = s10_receive_callback;
  350. priv->client.priv = priv;
  351. priv->chan = stratix10_svc_request_channel_byname(&priv->client,
  352. SVC_CLIENT_FPGA);
  353. if (IS_ERR(priv->chan)) {
  354. dev_err(dev, "couldn't get service channel (%s)\n",
  355. SVC_CLIENT_FPGA);
  356. return PTR_ERR(priv->chan);
  357. }
  358. init_completion(&priv->status_return_completion);
  359. mgr = fpga_mgr_create(dev, "Stratix10 SOC FPGA Manager",
  360. &s10_ops, priv);
  361. if (!mgr) {
  362. dev_err(dev, "unable to create FPGA manager\n");
  363. ret = -ENOMEM;
  364. goto probe_err;
  365. }
  366. ret = fpga_mgr_register(mgr);
  367. if (ret) {
  368. dev_err(dev, "unable to register FPGA manager\n");
  369. fpga_mgr_free(mgr);
  370. goto probe_err;
  371. }
  372. platform_set_drvdata(pdev, mgr);
  373. return ret;
  374. probe_err:
  375. stratix10_svc_free_channel(priv->chan);
  376. return ret;
  377. }
  378. static int s10_remove(struct platform_device *pdev)
  379. {
  380. struct fpga_manager *mgr = platform_get_drvdata(pdev);
  381. struct s10_priv *priv = mgr->priv;
  382. fpga_mgr_unregister(mgr);
  383. fpga_mgr_free(mgr);
  384. stratix10_svc_free_channel(priv->chan);
  385. return 0;
  386. }
  387. static const struct of_device_id s10_of_match[] = {
  388. {.compatible = "intel,stratix10-soc-fpga-mgr"},
  389. {.compatible = "intel,agilex-soc-fpga-mgr"},
  390. {},
  391. };
  392. MODULE_DEVICE_TABLE(of, s10_of_match);
  393. static struct platform_driver s10_driver = {
  394. .probe = s10_probe,
  395. .remove = s10_remove,
  396. .driver = {
  397. .name = "Stratix10 SoC FPGA manager",
  398. .of_match_table = of_match_ptr(s10_of_match),
  399. },
  400. };
  401. static int __init s10_init(void)
  402. {
  403. struct device_node *fw_np;
  404. struct device_node *np;
  405. int ret;
  406. fw_np = of_find_node_by_name(NULL, "svc");
  407. if (!fw_np)
  408. return -ENODEV;
  409. of_node_get(fw_np);
  410. np = of_find_matching_node(fw_np, s10_of_match);
  411. if (!np) {
  412. of_node_put(fw_np);
  413. return -ENODEV;
  414. }
  415. of_node_put(np);
  416. ret = of_platform_populate(fw_np, s10_of_match, NULL, NULL);
  417. of_node_put(fw_np);
  418. if (ret)
  419. return ret;
  420. return platform_driver_register(&s10_driver);
  421. }
  422. static void __exit s10_exit(void)
  423. {
  424. return platform_driver_unregister(&s10_driver);
  425. }
  426. module_init(s10_init);
  427. module_exit(s10_exit);
  428. MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
  429. MODULE_DESCRIPTION("Intel Stratix 10 SOC FPGA Manager");
  430. MODULE_LICENSE("GPL v2");