socfpga.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA Manager Driver for Altera SOCFPGA
  4. *
  5. * Copyright (C) 2013-2015 Altera Corporation
  6. */
  7. #include <linux/completion.h>
  8. #include <linux/delay.h>
  9. #include <linux/fpga/fpga-mgr.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of_address.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/pm.h>
  16. /* Register offsets */
  17. #define SOCFPGA_FPGMGR_STAT_OFST 0x0
  18. #define SOCFPGA_FPGMGR_CTL_OFST 0x4
  19. #define SOCFPGA_FPGMGR_DCLKCNT_OFST 0x8
  20. #define SOCFPGA_FPGMGR_DCLKSTAT_OFST 0xc
  21. #define SOCFPGA_FPGMGR_GPIO_INTEN_OFST 0x830
  22. #define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST 0x834
  23. #define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST 0x838
  24. #define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST 0x83c
  25. #define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST 0x840
  26. #define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST 0x844
  27. #define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST 0x84c
  28. #define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST 0x850
  29. /* Register bit defines */
  30. /* SOCFPGA_FPGMGR_STAT register mode field values */
  31. #define SOCFPGA_FPGMGR_STAT_POWER_UP 0x0 /*ramping*/
  32. #define SOCFPGA_FPGMGR_STAT_RESET 0x1
  33. #define SOCFPGA_FPGMGR_STAT_CFG 0x2
  34. #define SOCFPGA_FPGMGR_STAT_INIT 0x3
  35. #define SOCFPGA_FPGMGR_STAT_USER_MODE 0x4
  36. #define SOCFPGA_FPGMGR_STAT_UNKNOWN 0x5
  37. #define SOCFPGA_FPGMGR_STAT_STATE_MASK 0x7
  38. /* This is a flag value that doesn't really happen in this register field */
  39. #define SOCFPGA_FPGMGR_STAT_POWER_OFF 0x0
  40. #define MSEL_PP16_FAST_NOAES_NODC 0x0
  41. #define MSEL_PP16_FAST_AES_NODC 0x1
  42. #define MSEL_PP16_FAST_AESOPT_DC 0x2
  43. #define MSEL_PP16_SLOW_NOAES_NODC 0x4
  44. #define MSEL_PP16_SLOW_AES_NODC 0x5
  45. #define MSEL_PP16_SLOW_AESOPT_DC 0x6
  46. #define MSEL_PP32_FAST_NOAES_NODC 0x8
  47. #define MSEL_PP32_FAST_AES_NODC 0x9
  48. #define MSEL_PP32_FAST_AESOPT_DC 0xa
  49. #define MSEL_PP32_SLOW_NOAES_NODC 0xc
  50. #define MSEL_PP32_SLOW_AES_NODC 0xd
  51. #define MSEL_PP32_SLOW_AESOPT_DC 0xe
  52. #define SOCFPGA_FPGMGR_STAT_MSEL_MASK 0x000000f8
  53. #define SOCFPGA_FPGMGR_STAT_MSEL_SHIFT 3
  54. /* SOCFPGA_FPGMGR_CTL register */
  55. #define SOCFPGA_FPGMGR_CTL_EN 0x00000001
  56. #define SOCFPGA_FPGMGR_CTL_NCE 0x00000002
  57. #define SOCFPGA_FPGMGR_CTL_NCFGPULL 0x00000004
  58. #define CDRATIO_X1 0x00000000
  59. #define CDRATIO_X2 0x00000040
  60. #define CDRATIO_X4 0x00000080
  61. #define CDRATIO_X8 0x000000c0
  62. #define SOCFPGA_FPGMGR_CTL_CDRATIO_MASK 0x000000c0
  63. #define SOCFPGA_FPGMGR_CTL_AXICFGEN 0x00000100
  64. #define CFGWDTH_16 0x00000000
  65. #define CFGWDTH_32 0x00000200
  66. #define SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK 0x00000200
  67. /* SOCFPGA_FPGMGR_DCLKSTAT register */
  68. #define SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1
  69. /* SOCFPGA_FPGMGR_GPIO_* registers share the same bit positions */
  70. #define SOCFPGA_FPGMGR_MON_NSTATUS 0x0001
  71. #define SOCFPGA_FPGMGR_MON_CONF_DONE 0x0002
  72. #define SOCFPGA_FPGMGR_MON_INIT_DONE 0x0004
  73. #define SOCFPGA_FPGMGR_MON_CRC_ERROR 0x0008
  74. #define SOCFPGA_FPGMGR_MON_CVP_CONF_DONE 0x0010
  75. #define SOCFPGA_FPGMGR_MON_PR_READY 0x0020
  76. #define SOCFPGA_FPGMGR_MON_PR_ERROR 0x0040
  77. #define SOCFPGA_FPGMGR_MON_PR_DONE 0x0080
  78. #define SOCFPGA_FPGMGR_MON_NCONFIG_PIN 0x0100
  79. #define SOCFPGA_FPGMGR_MON_NSTATUS_PIN 0x0200
  80. #define SOCFPGA_FPGMGR_MON_CONF_DONE_PIN 0x0400
  81. #define SOCFPGA_FPGMGR_MON_FPGA_POWER_ON 0x0800
  82. #define SOCFPGA_FPGMGR_MON_STATUS_MASK 0x0fff
  83. #define SOCFPGA_FPGMGR_NUM_SUPPLIES 3
  84. #define SOCFPGA_RESUME_TIMEOUT 3
  85. /* In power-up order. Reverse for power-down. */
  86. static const char *supply_names[SOCFPGA_FPGMGR_NUM_SUPPLIES] __maybe_unused = {
  87. "FPGA-1.5V",
  88. "FPGA-1.1V",
  89. "FPGA-2.5V",
  90. };
  91. struct socfpga_fpga_priv {
  92. void __iomem *fpga_base_addr;
  93. void __iomem *fpga_data_addr;
  94. struct completion status_complete;
  95. int irq;
  96. };
  97. struct cfgmgr_mode {
  98. /* Values to set in the CTRL register */
  99. u32 ctrl;
  100. /* flag that this table entry is a valid mode */
  101. bool valid;
  102. };
  103. /* For SOCFPGA_FPGMGR_STAT_MSEL field */
  104. static struct cfgmgr_mode cfgmgr_modes[] = {
  105. [MSEL_PP16_FAST_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
  106. [MSEL_PP16_FAST_AES_NODC] = { CFGWDTH_16 | CDRATIO_X2, 1 },
  107. [MSEL_PP16_FAST_AESOPT_DC] = { CFGWDTH_16 | CDRATIO_X4, 1 },
  108. [MSEL_PP16_SLOW_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
  109. [MSEL_PP16_SLOW_AES_NODC] = { CFGWDTH_16 | CDRATIO_X2, 1 },
  110. [MSEL_PP16_SLOW_AESOPT_DC] = { CFGWDTH_16 | CDRATIO_X4, 1 },
  111. [MSEL_PP32_FAST_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
  112. [MSEL_PP32_FAST_AES_NODC] = { CFGWDTH_32 | CDRATIO_X4, 1 },
  113. [MSEL_PP32_FAST_AESOPT_DC] = { CFGWDTH_32 | CDRATIO_X8, 1 },
  114. [MSEL_PP32_SLOW_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
  115. [MSEL_PP32_SLOW_AES_NODC] = { CFGWDTH_32 | CDRATIO_X4, 1 },
  116. [MSEL_PP32_SLOW_AESOPT_DC] = { CFGWDTH_32 | CDRATIO_X8, 1 },
  117. };
  118. static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset)
  119. {
  120. return readl(priv->fpga_base_addr + reg_offset);
  121. }
  122. static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset,
  123. u32 value)
  124. {
  125. writel(value, priv->fpga_base_addr + reg_offset);
  126. }
  127. static u32 socfpga_fpga_raw_readl(struct socfpga_fpga_priv *priv,
  128. u32 reg_offset)
  129. {
  130. return __raw_readl(priv->fpga_base_addr + reg_offset);
  131. }
  132. static void socfpga_fpga_raw_writel(struct socfpga_fpga_priv *priv,
  133. u32 reg_offset, u32 value)
  134. {
  135. __raw_writel(value, priv->fpga_base_addr + reg_offset);
  136. }
  137. static void socfpga_fpga_data_writel(struct socfpga_fpga_priv *priv, u32 value)
  138. {
  139. writel(value, priv->fpga_data_addr);
  140. }
  141. static inline void socfpga_fpga_set_bitsl(struct socfpga_fpga_priv *priv,
  142. u32 offset, u32 bits)
  143. {
  144. u32 val;
  145. val = socfpga_fpga_readl(priv, offset);
  146. val |= bits;
  147. socfpga_fpga_writel(priv, offset, val);
  148. }
  149. static inline void socfpga_fpga_clr_bitsl(struct socfpga_fpga_priv *priv,
  150. u32 offset, u32 bits)
  151. {
  152. u32 val;
  153. val = socfpga_fpga_readl(priv, offset);
  154. val &= ~bits;
  155. socfpga_fpga_writel(priv, offset, val);
  156. }
  157. static u32 socfpga_fpga_mon_status_get(struct socfpga_fpga_priv *priv)
  158. {
  159. return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST) &
  160. SOCFPGA_FPGMGR_MON_STATUS_MASK;
  161. }
  162. static u32 socfpga_fpga_state_get(struct socfpga_fpga_priv *priv)
  163. {
  164. u32 status = socfpga_fpga_mon_status_get(priv);
  165. if ((status & SOCFPGA_FPGMGR_MON_FPGA_POWER_ON) == 0)
  166. return SOCFPGA_FPGMGR_STAT_POWER_OFF;
  167. return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST) &
  168. SOCFPGA_FPGMGR_STAT_STATE_MASK;
  169. }
  170. static void socfpga_fpga_clear_done_status(struct socfpga_fpga_priv *priv)
  171. {
  172. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST,
  173. SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE);
  174. }
  175. /*
  176. * Set the DCLKCNT, wait for DCLKSTAT to report the count completed, and clear
  177. * the complete status.
  178. */
  179. static int socfpga_fpga_dclk_set_and_wait_clear(struct socfpga_fpga_priv *priv,
  180. u32 count)
  181. {
  182. int timeout = 2;
  183. u32 done;
  184. /* Clear any existing DONE status. */
  185. if (socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST))
  186. socfpga_fpga_clear_done_status(priv);
  187. /* Issue the DCLK count. */
  188. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKCNT_OFST, count);
  189. /* Poll DCLKSTAT to see if it completed in the timeout period. */
  190. do {
  191. done = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST);
  192. if (done == SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE) {
  193. socfpga_fpga_clear_done_status(priv);
  194. return 0;
  195. }
  196. udelay(1);
  197. } while (timeout--);
  198. return -ETIMEDOUT;
  199. }
  200. static int socfpga_fpga_wait_for_state(struct socfpga_fpga_priv *priv,
  201. u32 state)
  202. {
  203. int timeout = 2;
  204. /*
  205. * HW doesn't support an interrupt for changes in state, so poll to see
  206. * if it matches the requested state within the timeout period.
  207. */
  208. do {
  209. if ((socfpga_fpga_state_get(priv) & state) != 0)
  210. return 0;
  211. msleep(20);
  212. } while (timeout--);
  213. return -ETIMEDOUT;
  214. }
  215. static void socfpga_fpga_enable_irqs(struct socfpga_fpga_priv *priv, u32 irqs)
  216. {
  217. /* set irqs to level sensitive */
  218. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST, 0);
  219. /* set interrupt polarity */
  220. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INT_POL_OFST, irqs);
  221. /* clear irqs */
  222. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs);
  223. /* unmask interrupts */
  224. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTMSK_OFST, 0);
  225. /* enable interrupts */
  226. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, irqs);
  227. }
  228. static void socfpga_fpga_disable_irqs(struct socfpga_fpga_priv *priv)
  229. {
  230. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);
  231. }
  232. static irqreturn_t socfpga_fpga_isr(int irq, void *dev_id)
  233. {
  234. struct socfpga_fpga_priv *priv = dev_id;
  235. u32 irqs, st;
  236. bool conf_done, nstatus;
  237. /* clear irqs */
  238. irqs = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST);
  239. socfpga_fpga_raw_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs);
  240. st = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST);
  241. conf_done = (st & SOCFPGA_FPGMGR_MON_CONF_DONE) != 0;
  242. nstatus = (st & SOCFPGA_FPGMGR_MON_NSTATUS) != 0;
  243. /* success */
  244. if (conf_done && nstatus) {
  245. /* disable irqs */
  246. socfpga_fpga_raw_writel(priv,
  247. SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);
  248. complete(&priv->status_complete);
  249. }
  250. return IRQ_HANDLED;
  251. }
  252. static int socfpga_fpga_wait_for_config_done(struct socfpga_fpga_priv *priv)
  253. {
  254. int timeout, ret = 0;
  255. socfpga_fpga_disable_irqs(priv);
  256. init_completion(&priv->status_complete);
  257. socfpga_fpga_enable_irqs(priv, SOCFPGA_FPGMGR_MON_CONF_DONE);
  258. timeout = wait_for_completion_interruptible_timeout(
  259. &priv->status_complete,
  260. msecs_to_jiffies(10));
  261. if (timeout == 0)
  262. ret = -ETIMEDOUT;
  263. socfpga_fpga_disable_irqs(priv);
  264. return ret;
  265. }
  266. static int socfpga_fpga_cfg_mode_get(struct socfpga_fpga_priv *priv)
  267. {
  268. u32 msel;
  269. msel = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST);
  270. msel &= SOCFPGA_FPGMGR_STAT_MSEL_MASK;
  271. msel >>= SOCFPGA_FPGMGR_STAT_MSEL_SHIFT;
  272. /* Check that this MSEL setting is supported */
  273. if ((msel >= ARRAY_SIZE(cfgmgr_modes)) || !cfgmgr_modes[msel].valid)
  274. return -EINVAL;
  275. return msel;
  276. }
  277. static int socfpga_fpga_cfg_mode_set(struct socfpga_fpga_priv *priv)
  278. {
  279. u32 ctrl_reg;
  280. int mode;
  281. /* get value from MSEL pins */
  282. mode = socfpga_fpga_cfg_mode_get(priv);
  283. if (mode < 0)
  284. return mode;
  285. /* Adjust CTRL for the CDRATIO */
  286. ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
  287. ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK;
  288. ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK;
  289. ctrl_reg |= cfgmgr_modes[mode].ctrl;
  290. /* Set NCE to 0. */
  291. ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE;
  292. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
  293. return 0;
  294. }
  295. static int socfpga_fpga_reset(struct fpga_manager *mgr)
  296. {
  297. struct socfpga_fpga_priv *priv = mgr->priv;
  298. u32 ctrl_reg, status;
  299. int ret;
  300. /*
  301. * Step 1:
  302. * - Set CTRL.CFGWDTH, CTRL.CDRATIO to match cfg mode
  303. * - Set CTRL.NCE to 0
  304. */
  305. ret = socfpga_fpga_cfg_mode_set(priv);
  306. if (ret)
  307. return ret;
  308. /* Step 2: Set CTRL.EN to 1 */
  309. socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
  310. SOCFPGA_FPGMGR_CTL_EN);
  311. /* Step 3: Set CTRL.NCONFIGPULL to 1 to put FPGA in reset */
  312. ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
  313. ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL;
  314. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
  315. /* Step 4: Wait for STATUS.MODE to report FPGA is in reset phase */
  316. status = socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_RESET);
  317. /* Step 5: Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset */
  318. ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCFGPULL;
  319. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
  320. /* Timeout waiting for reset */
  321. if (status)
  322. return -ETIMEDOUT;
  323. return 0;
  324. }
  325. /*
  326. * Prepare the FPGA to receive the configuration data.
  327. */
  328. static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr,
  329. struct fpga_image_info *info,
  330. const char *buf, size_t count)
  331. {
  332. struct socfpga_fpga_priv *priv = mgr->priv;
  333. int ret;
  334. if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
  335. dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
  336. return -EINVAL;
  337. }
  338. /* Steps 1 - 5: Reset the FPGA */
  339. ret = socfpga_fpga_reset(mgr);
  340. if (ret)
  341. return ret;
  342. /* Step 6: Wait for FPGA to enter configuration phase */
  343. if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_CFG))
  344. return -ETIMEDOUT;
  345. /* Step 7: Clear nSTATUS interrupt */
  346. socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST,
  347. SOCFPGA_FPGMGR_MON_NSTATUS);
  348. /* Step 8: Set CTRL.AXICFGEN to 1 to enable transfer of config data */
  349. socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
  350. SOCFPGA_FPGMGR_CTL_AXICFGEN);
  351. return 0;
  352. }
  353. /*
  354. * Step 9: write data to the FPGA data register
  355. */
  356. static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr,
  357. const char *buf, size_t count)
  358. {
  359. struct socfpga_fpga_priv *priv = mgr->priv;
  360. u32 *buffer_32 = (u32 *)buf;
  361. size_t i = 0;
  362. if (count <= 0)
  363. return -EINVAL;
  364. /* Write out the complete 32-bit chunks. */
  365. while (count >= sizeof(u32)) {
  366. socfpga_fpga_data_writel(priv, buffer_32[i++]);
  367. count -= sizeof(u32);
  368. }
  369. /* Write out remaining non 32-bit chunks. */
  370. switch (count) {
  371. case 3:
  372. socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x00ffffff);
  373. break;
  374. case 2:
  375. socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x0000ffff);
  376. break;
  377. case 1:
  378. socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x000000ff);
  379. break;
  380. case 0:
  381. break;
  382. default:
  383. /* This will never happen. */
  384. return -EFAULT;
  385. }
  386. return 0;
  387. }
  388. static int socfpga_fpga_ops_configure_complete(struct fpga_manager *mgr,
  389. struct fpga_image_info *info)
  390. {
  391. struct socfpga_fpga_priv *priv = mgr->priv;
  392. u32 status;
  393. /*
  394. * Step 10:
  395. * - Observe CONF_DONE and nSTATUS (active low)
  396. * - if CONF_DONE = 1 and nSTATUS = 1, configuration was successful
  397. * - if CONF_DONE = 0 and nSTATUS = 0, configuration failed
  398. */
  399. status = socfpga_fpga_wait_for_config_done(priv);
  400. if (status)
  401. return status;
  402. /* Step 11: Clear CTRL.AXICFGEN to disable transfer of config data */
  403. socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
  404. SOCFPGA_FPGMGR_CTL_AXICFGEN);
  405. /*
  406. * Step 12:
  407. * - Write 4 to DCLKCNT
  408. * - Wait for STATUS.DCNTDONE = 1
  409. * - Clear W1C bit in STATUS.DCNTDONE
  410. */
  411. if (socfpga_fpga_dclk_set_and_wait_clear(priv, 4))
  412. return -ETIMEDOUT;
  413. /* Step 13: Wait for STATUS.MODE to report USER MODE */
  414. if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_USER_MODE))
  415. return -ETIMEDOUT;
  416. /* Step 14: Set CTRL.EN to 0 */
  417. socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
  418. SOCFPGA_FPGMGR_CTL_EN);
  419. return 0;
  420. }
  421. /* Translate state register values to FPGA framework state */
  422. static const enum fpga_mgr_states socfpga_state_to_framework_state[] = {
  423. [SOCFPGA_FPGMGR_STAT_POWER_OFF] = FPGA_MGR_STATE_POWER_OFF,
  424. [SOCFPGA_FPGMGR_STAT_RESET] = FPGA_MGR_STATE_RESET,
  425. [SOCFPGA_FPGMGR_STAT_CFG] = FPGA_MGR_STATE_WRITE_INIT,
  426. [SOCFPGA_FPGMGR_STAT_INIT] = FPGA_MGR_STATE_WRITE_INIT,
  427. [SOCFPGA_FPGMGR_STAT_USER_MODE] = FPGA_MGR_STATE_OPERATING,
  428. [SOCFPGA_FPGMGR_STAT_UNKNOWN] = FPGA_MGR_STATE_UNKNOWN,
  429. };
  430. static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr)
  431. {
  432. struct socfpga_fpga_priv *priv = mgr->priv;
  433. enum fpga_mgr_states ret;
  434. u32 state;
  435. state = socfpga_fpga_state_get(priv);
  436. if (state < ARRAY_SIZE(socfpga_state_to_framework_state))
  437. ret = socfpga_state_to_framework_state[state];
  438. else
  439. ret = FPGA_MGR_STATE_UNKNOWN;
  440. return ret;
  441. }
  442. static const struct fpga_manager_ops socfpga_fpga_ops = {
  443. .state = socfpga_fpga_ops_state,
  444. .write_init = socfpga_fpga_ops_configure_init,
  445. .write = socfpga_fpga_ops_configure_write,
  446. .write_complete = socfpga_fpga_ops_configure_complete,
  447. };
  448. static int socfpga_fpga_probe(struct platform_device *pdev)
  449. {
  450. struct device *dev = &pdev->dev;
  451. struct socfpga_fpga_priv *priv;
  452. struct fpga_manager *mgr;
  453. struct resource *res;
  454. int ret;
  455. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  456. if (!priv)
  457. return -ENOMEM;
  458. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  459. priv->fpga_base_addr = devm_ioremap_resource(dev, res);
  460. if (IS_ERR(priv->fpga_base_addr))
  461. return PTR_ERR(priv->fpga_base_addr);
  462. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  463. priv->fpga_data_addr = devm_ioremap_resource(dev, res);
  464. if (IS_ERR(priv->fpga_data_addr))
  465. return PTR_ERR(priv->fpga_data_addr);
  466. priv->irq = platform_get_irq(pdev, 0);
  467. if (priv->irq < 0)
  468. return priv->irq;
  469. ret = devm_request_irq(dev, priv->irq, socfpga_fpga_isr, 0,
  470. dev_name(dev), priv);
  471. if (ret)
  472. return ret;
  473. mgr = devm_fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
  474. &socfpga_fpga_ops, priv);
  475. if (!mgr)
  476. return -ENOMEM;
  477. platform_set_drvdata(pdev, mgr);
  478. return fpga_mgr_register(mgr);
  479. }
  480. static int socfpga_fpga_remove(struct platform_device *pdev)
  481. {
  482. struct fpga_manager *mgr = platform_get_drvdata(pdev);
  483. fpga_mgr_unregister(mgr);
  484. return 0;
  485. }
  486. #ifdef CONFIG_OF
  487. static const struct of_device_id socfpga_fpga_of_match[] = {
  488. { .compatible = "altr,socfpga-fpga-mgr", },
  489. {},
  490. };
  491. MODULE_DEVICE_TABLE(of, socfpga_fpga_of_match);
  492. #endif
  493. static struct platform_driver socfpga_fpga_driver = {
  494. .probe = socfpga_fpga_probe,
  495. .remove = socfpga_fpga_remove,
  496. .driver = {
  497. .name = "socfpga_fpga_manager",
  498. .of_match_table = of_match_ptr(socfpga_fpga_of_match),
  499. },
  500. };
  501. module_platform_driver(socfpga_fpga_driver);
  502. MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
  503. MODULE_DESCRIPTION("Altera SOCFPGA FPGA Manager");
  504. MODULE_LICENSE("GPL v2");