of-fpga-region.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA Region - Device Tree support for FPGA programming under Linux
  4. *
  5. * Copyright (C) 2013-2016 Altera Corporation
  6. * Copyright (C) 2017 Intel Corporation
  7. */
  8. #include <linux/fpga/fpga-bridge.h>
  9. #include <linux/fpga/fpga-mgr.h>
  10. #include <linux/fpga/fpga-region.h>
  11. #include <linux/idr.h>
  12. #include <linux/kernel.h>
  13. #include <linux/list.h>
  14. #include <linux/module.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/slab.h>
  17. #include <linux/spinlock.h>
  18. static const struct of_device_id fpga_region_of_match[] = {
  19. { .compatible = "fpga-region", },
  20. {},
  21. };
  22. MODULE_DEVICE_TABLE(of, fpga_region_of_match);
  23. /**
  24. * of_fpga_region_find - find FPGA region
  25. * @np: device node of FPGA Region
  26. *
  27. * Caller will need to put_device(&region->dev) when done.
  28. *
  29. * Returns FPGA Region struct or NULL
  30. */
  31. static struct fpga_region *of_fpga_region_find(struct device_node *np)
  32. {
  33. return fpga_region_class_find(NULL, np, device_match_of_node);
  34. }
  35. /**
  36. * of_fpga_region_get_mgr - get reference for FPGA manager
  37. * @np: device node of FPGA region
  38. *
  39. * Get FPGA Manager from "fpga-mgr" property or from ancestor region.
  40. *
  41. * Caller should call fpga_mgr_put() when done with manager.
  42. *
  43. * Return: fpga manager struct or IS_ERR() condition containing error code.
  44. */
  45. static struct fpga_manager *of_fpga_region_get_mgr(struct device_node *np)
  46. {
  47. struct device_node *mgr_node;
  48. struct fpga_manager *mgr;
  49. of_node_get(np);
  50. while (np) {
  51. if (of_device_is_compatible(np, "fpga-region")) {
  52. mgr_node = of_parse_phandle(np, "fpga-mgr", 0);
  53. if (mgr_node) {
  54. mgr = of_fpga_mgr_get(mgr_node);
  55. of_node_put(mgr_node);
  56. of_node_put(np);
  57. return mgr;
  58. }
  59. }
  60. np = of_get_next_parent(np);
  61. }
  62. of_node_put(np);
  63. return ERR_PTR(-EINVAL);
  64. }
  65. /**
  66. * of_fpga_region_get_bridges - create a list of bridges
  67. * @region: FPGA region
  68. *
  69. * Create a list of bridges including the parent bridge and the bridges
  70. * specified by "fpga-bridges" property. Note that the
  71. * fpga_bridges_enable/disable/put functions are all fine with an empty list
  72. * if that happens.
  73. *
  74. * Caller should call fpga_bridges_put(&region->bridge_list) when
  75. * done with the bridges.
  76. *
  77. * Return 0 for success (even if there are no bridges specified)
  78. * or -EBUSY if any of the bridges are in use.
  79. */
  80. static int of_fpga_region_get_bridges(struct fpga_region *region)
  81. {
  82. struct device *dev = &region->dev;
  83. struct device_node *region_np = dev->of_node;
  84. struct fpga_image_info *info = region->info;
  85. struct device_node *br, *np, *parent_br = NULL;
  86. int i, ret;
  87. /* If parent is a bridge, add to list */
  88. ret = of_fpga_bridge_get_to_list(region_np->parent, info,
  89. &region->bridge_list);
  90. /* -EBUSY means parent is a bridge that is under use. Give up. */
  91. if (ret == -EBUSY)
  92. return ret;
  93. /* Zero return code means parent was a bridge and was added to list. */
  94. if (!ret)
  95. parent_br = region_np->parent;
  96. /* If overlay has a list of bridges, use it. */
  97. br = of_parse_phandle(info->overlay, "fpga-bridges", 0);
  98. if (br) {
  99. of_node_put(br);
  100. np = info->overlay;
  101. } else {
  102. np = region_np;
  103. }
  104. for (i = 0; ; i++) {
  105. br = of_parse_phandle(np, "fpga-bridges", i);
  106. if (!br)
  107. break;
  108. /* If parent bridge is in list, skip it. */
  109. if (br == parent_br) {
  110. of_node_put(br);
  111. continue;
  112. }
  113. /* If node is a bridge, get it and add to list */
  114. ret = of_fpga_bridge_get_to_list(br, info,
  115. &region->bridge_list);
  116. of_node_put(br);
  117. /* If any of the bridges are in use, give up */
  118. if (ret == -EBUSY) {
  119. fpga_bridges_put(&region->bridge_list);
  120. return -EBUSY;
  121. }
  122. }
  123. return 0;
  124. }
  125. /**
  126. * child_regions_with_firmware
  127. * @overlay: device node of the overlay
  128. *
  129. * If the overlay adds child FPGA regions, they are not allowed to have
  130. * firmware-name property.
  131. *
  132. * Return 0 for OK or -EINVAL if child FPGA region adds firmware-name.
  133. */
  134. static int child_regions_with_firmware(struct device_node *overlay)
  135. {
  136. struct device_node *child_region;
  137. const char *child_firmware_name;
  138. int ret = 0;
  139. of_node_get(overlay);
  140. child_region = of_find_matching_node(overlay, fpga_region_of_match);
  141. while (child_region) {
  142. if (!of_property_read_string(child_region, "firmware-name",
  143. &child_firmware_name)) {
  144. ret = -EINVAL;
  145. break;
  146. }
  147. child_region = of_find_matching_node(child_region,
  148. fpga_region_of_match);
  149. }
  150. of_node_put(child_region);
  151. if (ret)
  152. pr_err("firmware-name not allowed in child FPGA region: %pOF",
  153. child_region);
  154. return ret;
  155. }
  156. /**
  157. * of_fpga_region_parse_ov - parse and check overlay applied to region
  158. *
  159. * @region: FPGA region
  160. * @overlay: overlay applied to the FPGA region
  161. *
  162. * Given an overlay applied to a FPGA region, parse the FPGA image specific
  163. * info in the overlay and do some checking.
  164. *
  165. * Returns:
  166. * NULL if overlay doesn't direct us to program the FPGA.
  167. * fpga_image_info struct if there is an image to program.
  168. * error code for invalid overlay.
  169. */
  170. static struct fpga_image_info *of_fpga_region_parse_ov(
  171. struct fpga_region *region,
  172. struct device_node *overlay)
  173. {
  174. struct device *dev = &region->dev;
  175. struct fpga_image_info *info;
  176. const char *firmware_name;
  177. int ret;
  178. if (region->info) {
  179. dev_err(dev, "Region already has overlay applied.\n");
  180. return ERR_PTR(-EINVAL);
  181. }
  182. /*
  183. * Reject overlay if child FPGA Regions added in the overlay have
  184. * firmware-name property (would mean that an FPGA region that has
  185. * not been added to the live tree yet is doing FPGA programming).
  186. */
  187. ret = child_regions_with_firmware(overlay);
  188. if (ret)
  189. return ERR_PTR(ret);
  190. info = fpga_image_info_alloc(dev);
  191. if (!info)
  192. return ERR_PTR(-ENOMEM);
  193. info->overlay = overlay;
  194. /* Read FPGA region properties from the overlay */
  195. if (of_property_read_bool(overlay, "partial-fpga-config"))
  196. info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
  197. if (of_property_read_bool(overlay, "external-fpga-config"))
  198. info->flags |= FPGA_MGR_EXTERNAL_CONFIG;
  199. if (of_property_read_bool(overlay, "encrypted-fpga-config"))
  200. info->flags |= FPGA_MGR_ENCRYPTED_BITSTREAM;
  201. if (!of_property_read_string(overlay, "firmware-name",
  202. &firmware_name)) {
  203. info->firmware_name = devm_kstrdup(dev, firmware_name,
  204. GFP_KERNEL);
  205. if (!info->firmware_name)
  206. return ERR_PTR(-ENOMEM);
  207. }
  208. of_property_read_u32(overlay, "region-unfreeze-timeout-us",
  209. &info->enable_timeout_us);
  210. of_property_read_u32(overlay, "region-freeze-timeout-us",
  211. &info->disable_timeout_us);
  212. of_property_read_u32(overlay, "config-complete-timeout-us",
  213. &info->config_complete_timeout_us);
  214. /* If overlay is not programming the FPGA, don't need FPGA image info */
  215. if (!info->firmware_name) {
  216. ret = 0;
  217. goto ret_no_info;
  218. }
  219. /*
  220. * If overlay informs us FPGA was externally programmed, specifying
  221. * firmware here would be ambiguous.
  222. */
  223. if (info->flags & FPGA_MGR_EXTERNAL_CONFIG) {
  224. dev_err(dev, "error: specified firmware and external-fpga-config");
  225. ret = -EINVAL;
  226. goto ret_no_info;
  227. }
  228. return info;
  229. ret_no_info:
  230. fpga_image_info_free(info);
  231. return ERR_PTR(ret);
  232. }
  233. /**
  234. * of_fpga_region_notify_pre_apply - pre-apply overlay notification
  235. *
  236. * @region: FPGA region that the overlay was applied to
  237. * @nd: overlay notification data
  238. *
  239. * Called when an overlay targeted to a FPGA Region is about to be applied.
  240. * Parses the overlay for properties that influence how the FPGA will be
  241. * programmed and does some checking. If the checks pass, programs the FPGA.
  242. * If the checks fail, overlay is rejected and does not get added to the
  243. * live tree.
  244. *
  245. * Returns 0 for success or negative error code for failure.
  246. */
  247. static int of_fpga_region_notify_pre_apply(struct fpga_region *region,
  248. struct of_overlay_notify_data *nd)
  249. {
  250. struct device *dev = &region->dev;
  251. struct fpga_image_info *info;
  252. int ret;
  253. info = of_fpga_region_parse_ov(region, nd->overlay);
  254. if (IS_ERR(info))
  255. return PTR_ERR(info);
  256. /* If overlay doesn't program the FPGA, accept it anyway. */
  257. if (!info)
  258. return 0;
  259. if (region->info) {
  260. dev_err(dev, "Region already has overlay applied.\n");
  261. return -EINVAL;
  262. }
  263. region->info = info;
  264. ret = fpga_region_program_fpga(region);
  265. if (ret) {
  266. /* error; reject overlay */
  267. fpga_image_info_free(info);
  268. region->info = NULL;
  269. }
  270. return ret;
  271. }
  272. /**
  273. * of_fpga_region_notify_post_remove - post-remove overlay notification
  274. *
  275. * @region: FPGA region that was targeted by the overlay that was removed
  276. * @nd: overlay notification data
  277. *
  278. * Called after an overlay has been removed if the overlay's target was a
  279. * FPGA region.
  280. */
  281. static void of_fpga_region_notify_post_remove(struct fpga_region *region,
  282. struct of_overlay_notify_data *nd)
  283. {
  284. fpga_bridges_disable(&region->bridge_list);
  285. fpga_bridges_put(&region->bridge_list);
  286. fpga_image_info_free(region->info);
  287. region->info = NULL;
  288. }
  289. /**
  290. * of_fpga_region_notify - reconfig notifier for dynamic DT changes
  291. * @nb: notifier block
  292. * @action: notifier action
  293. * @arg: reconfig data
  294. *
  295. * This notifier handles programming a FPGA when a "firmware-name" property is
  296. * added to a fpga-region.
  297. *
  298. * Returns NOTIFY_OK or error if FPGA programming fails.
  299. */
  300. static int of_fpga_region_notify(struct notifier_block *nb,
  301. unsigned long action, void *arg)
  302. {
  303. struct of_overlay_notify_data *nd = arg;
  304. struct fpga_region *region;
  305. int ret;
  306. switch (action) {
  307. case OF_OVERLAY_PRE_APPLY:
  308. pr_debug("%s OF_OVERLAY_PRE_APPLY\n", __func__);
  309. break;
  310. case OF_OVERLAY_POST_APPLY:
  311. pr_debug("%s OF_OVERLAY_POST_APPLY\n", __func__);
  312. return NOTIFY_OK; /* not for us */
  313. case OF_OVERLAY_PRE_REMOVE:
  314. pr_debug("%s OF_OVERLAY_PRE_REMOVE\n", __func__);
  315. return NOTIFY_OK; /* not for us */
  316. case OF_OVERLAY_POST_REMOVE:
  317. pr_debug("%s OF_OVERLAY_POST_REMOVE\n", __func__);
  318. break;
  319. default: /* should not happen */
  320. return NOTIFY_OK;
  321. }
  322. region = of_fpga_region_find(nd->target);
  323. if (!region)
  324. return NOTIFY_OK;
  325. ret = 0;
  326. switch (action) {
  327. case OF_OVERLAY_PRE_APPLY:
  328. ret = of_fpga_region_notify_pre_apply(region, nd);
  329. break;
  330. case OF_OVERLAY_POST_REMOVE:
  331. of_fpga_region_notify_post_remove(region, nd);
  332. break;
  333. }
  334. put_device(&region->dev);
  335. if (ret)
  336. return notifier_from_errno(ret);
  337. return NOTIFY_OK;
  338. }
  339. static struct notifier_block fpga_region_of_nb = {
  340. .notifier_call = of_fpga_region_notify,
  341. };
  342. static int of_fpga_region_probe(struct platform_device *pdev)
  343. {
  344. struct device *dev = &pdev->dev;
  345. struct device_node *np = dev->of_node;
  346. struct fpga_region *region;
  347. struct fpga_manager *mgr;
  348. int ret;
  349. /* Find the FPGA mgr specified by region or parent region. */
  350. mgr = of_fpga_region_get_mgr(np);
  351. if (IS_ERR(mgr))
  352. return -EPROBE_DEFER;
  353. region = devm_fpga_region_create(dev, mgr, of_fpga_region_get_bridges);
  354. if (!region) {
  355. ret = -ENOMEM;
  356. goto eprobe_mgr_put;
  357. }
  358. ret = fpga_region_register(region);
  359. if (ret)
  360. goto eprobe_mgr_put;
  361. of_platform_populate(np, fpga_region_of_match, NULL, &region->dev);
  362. platform_set_drvdata(pdev, region);
  363. dev_info(dev, "FPGA Region probed\n");
  364. return 0;
  365. eprobe_mgr_put:
  366. fpga_mgr_put(mgr);
  367. return ret;
  368. }
  369. static int of_fpga_region_remove(struct platform_device *pdev)
  370. {
  371. struct fpga_region *region = platform_get_drvdata(pdev);
  372. struct fpga_manager *mgr = region->mgr;
  373. fpga_region_unregister(region);
  374. fpga_mgr_put(mgr);
  375. return 0;
  376. }
  377. static struct platform_driver of_fpga_region_driver = {
  378. .probe = of_fpga_region_probe,
  379. .remove = of_fpga_region_remove,
  380. .driver = {
  381. .name = "of-fpga-region",
  382. .of_match_table = of_match_ptr(fpga_region_of_match),
  383. },
  384. };
  385. /**
  386. * fpga_region_init - init function for fpga_region class
  387. * Creates the fpga_region class and registers a reconfig notifier.
  388. */
  389. static int __init of_fpga_region_init(void)
  390. {
  391. int ret;
  392. ret = of_overlay_notifier_register(&fpga_region_of_nb);
  393. if (ret)
  394. return ret;
  395. ret = platform_driver_register(&of_fpga_region_driver);
  396. if (ret)
  397. goto err_plat;
  398. return 0;
  399. err_plat:
  400. of_overlay_notifier_unregister(&fpga_region_of_nb);
  401. return ret;
  402. }
  403. static void __exit of_fpga_region_exit(void)
  404. {
  405. platform_driver_unregister(&of_fpga_region_driver);
  406. of_overlay_notifier_unregister(&fpga_region_of_nb);
  407. }
  408. subsys_initcall(of_fpga_region_init);
  409. module_exit(of_fpga_region_exit);
  410. MODULE_DESCRIPTION("FPGA Region");
  411. MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
  412. MODULE_LICENSE("GPL v2");