machxo2-spi.c 9.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Lattice MachXO2 Slave SPI Driver
  4. *
  5. * Manage Lattice FPGA firmware that is loaded over SPI using
  6. * the slave serial configuration interface.
  7. *
  8. * Copyright (C) 2018 Paolo Pisati <p.pisati@gmail.com>
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/fpga/fpga-mgr.h>
  12. #include <linux/gpio/consumer.h>
  13. #include <linux/module.h>
  14. #include <linux/of.h>
  15. #include <linux/spi/spi.h>
  16. /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
  17. #define IDCODE_PUB {0xe0, 0x00, 0x00, 0x00}
  18. #define ISC_ENABLE {0xc6, 0x08, 0x00, 0x00}
  19. #define ISC_ERASE {0x0e, 0x04, 0x00, 0x00}
  20. #define ISC_PROGRAMDONE {0x5e, 0x00, 0x00, 0x00}
  21. #define LSC_INITADDRESS {0x46, 0x00, 0x00, 0x00}
  22. #define LSC_PROGINCRNV {0x70, 0x00, 0x00, 0x01}
  23. #define LSC_READ_STATUS {0x3c, 0x00, 0x00, 0x00}
  24. #define LSC_REFRESH {0x79, 0x00, 0x00, 0x00}
  25. /*
  26. * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
  27. * Sheet' sysCONFIG Port Timing Specifications (3-36)
  28. */
  29. #define MACHXO2_MAX_SPEED 66000000
  30. #define MACHXO2_LOW_DELAY_USEC 5
  31. #define MACHXO2_HIGH_DELAY_USEC 200
  32. #define MACHXO2_REFRESH_USEC 4800
  33. #define MACHXO2_MAX_BUSY_LOOP 128
  34. #define MACHXO2_MAX_REFRESH_LOOP 16
  35. #define MACHXO2_PAGE_SIZE 16
  36. #define MACHXO2_BUF_SIZE (MACHXO2_PAGE_SIZE + 4)
  37. /* Status register bits, errors and error mask */
  38. #define BUSY 12
  39. #define DONE 8
  40. #define DVER 27
  41. #define ENAB 9
  42. #define ERRBITS 23
  43. #define ERRMASK 7
  44. #define FAIL 13
  45. #define ENOERR 0 /* no error */
  46. #define EID 1
  47. #define ECMD 2
  48. #define ECRC 3
  49. #define EPREAM 4 /* preamble error */
  50. #define EABRT 5 /* abort error */
  51. #define EOVERFL 6 /* overflow error */
  52. #define ESDMEOF 7 /* SDM EOF */
  53. static inline u8 get_err(unsigned long *status)
  54. {
  55. return (*status >> ERRBITS) & ERRMASK;
  56. }
  57. static int get_status(struct spi_device *spi, unsigned long *status)
  58. {
  59. struct spi_message msg;
  60. struct spi_transfer rx, tx;
  61. static const u8 cmd[] = LSC_READ_STATUS;
  62. int ret;
  63. memset(&rx, 0, sizeof(rx));
  64. memset(&tx, 0, sizeof(tx));
  65. tx.tx_buf = cmd;
  66. tx.len = sizeof(cmd);
  67. rx.rx_buf = status;
  68. rx.len = 4;
  69. spi_message_init(&msg);
  70. spi_message_add_tail(&tx, &msg);
  71. spi_message_add_tail(&rx, &msg);
  72. ret = spi_sync(spi, &msg);
  73. if (ret)
  74. return ret;
  75. *status = be32_to_cpu(*status);
  76. return 0;
  77. }
  78. #ifdef DEBUG
  79. static const char *get_err_string(u8 err)
  80. {
  81. switch (err) {
  82. case ENOERR: return "No Error";
  83. case EID: return "ID ERR";
  84. case ECMD: return "CMD ERR";
  85. case ECRC: return "CRC ERR";
  86. case EPREAM: return "Preamble ERR";
  87. case EABRT: return "Abort ERR";
  88. case EOVERFL: return "Overflow ERR";
  89. case ESDMEOF: return "SDM EOF";
  90. }
  91. return "Default switch case";
  92. }
  93. #endif
  94. static void dump_status_reg(unsigned long *status)
  95. {
  96. #ifdef DEBUG
  97. pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
  98. *status, test_bit(DONE, status), test_bit(ENAB, status),
  99. test_bit(BUSY, status), test_bit(FAIL, status),
  100. test_bit(DVER, status), get_err_string(get_err(status)));
  101. #endif
  102. }
  103. static int wait_until_not_busy(struct spi_device *spi)
  104. {
  105. unsigned long status;
  106. int ret, loop = 0;
  107. do {
  108. ret = get_status(spi, &status);
  109. if (ret)
  110. return ret;
  111. if (++loop >= MACHXO2_MAX_BUSY_LOOP)
  112. return -EBUSY;
  113. } while (test_bit(BUSY, &status));
  114. return 0;
  115. }
  116. static int machxo2_cleanup(struct fpga_manager *mgr)
  117. {
  118. struct spi_device *spi = mgr->priv;
  119. struct spi_message msg;
  120. struct spi_transfer tx[2];
  121. static const u8 erase[] = ISC_ERASE;
  122. static const u8 refresh[] = LSC_REFRESH;
  123. int ret;
  124. memset(tx, 0, sizeof(tx));
  125. spi_message_init(&msg);
  126. tx[0].tx_buf = &erase;
  127. tx[0].len = sizeof(erase);
  128. spi_message_add_tail(&tx[0], &msg);
  129. ret = spi_sync(spi, &msg);
  130. if (ret)
  131. goto fail;
  132. ret = wait_until_not_busy(spi);
  133. if (ret)
  134. goto fail;
  135. spi_message_init(&msg);
  136. tx[1].tx_buf = &refresh;
  137. tx[1].len = sizeof(refresh);
  138. tx[1].delay.value = MACHXO2_REFRESH_USEC;
  139. tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
  140. spi_message_add_tail(&tx[1], &msg);
  141. ret = spi_sync(spi, &msg);
  142. if (ret)
  143. goto fail;
  144. return 0;
  145. fail:
  146. dev_err(&mgr->dev, "Cleanup failed\n");
  147. return ret;
  148. }
  149. static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
  150. {
  151. struct spi_device *spi = mgr->priv;
  152. unsigned long status;
  153. get_status(spi, &status);
  154. if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
  155. get_err(&status) == ENOERR)
  156. return FPGA_MGR_STATE_OPERATING;
  157. return FPGA_MGR_STATE_UNKNOWN;
  158. }
  159. static int machxo2_write_init(struct fpga_manager *mgr,
  160. struct fpga_image_info *info,
  161. const char *buf, size_t count)
  162. {
  163. struct spi_device *spi = mgr->priv;
  164. struct spi_message msg;
  165. struct spi_transfer tx[3];
  166. static const u8 enable[] = ISC_ENABLE;
  167. static const u8 erase[] = ISC_ERASE;
  168. static const u8 initaddr[] = LSC_INITADDRESS;
  169. unsigned long status;
  170. int ret;
  171. if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
  172. dev_err(&mgr->dev,
  173. "Partial reconfiguration is not supported\n");
  174. return -ENOTSUPP;
  175. }
  176. get_status(spi, &status);
  177. dump_status_reg(&status);
  178. memset(tx, 0, sizeof(tx));
  179. spi_message_init(&msg);
  180. tx[0].tx_buf = &enable;
  181. tx[0].len = sizeof(enable);
  182. tx[0].delay.value = MACHXO2_LOW_DELAY_USEC;
  183. tx[0].delay.unit = SPI_DELAY_UNIT_USECS;
  184. spi_message_add_tail(&tx[0], &msg);
  185. tx[1].tx_buf = &erase;
  186. tx[1].len = sizeof(erase);
  187. spi_message_add_tail(&tx[1], &msg);
  188. ret = spi_sync(spi, &msg);
  189. if (ret)
  190. goto fail;
  191. ret = wait_until_not_busy(spi);
  192. if (ret)
  193. goto fail;
  194. get_status(spi, &status);
  195. if (test_bit(FAIL, &status)) {
  196. ret = -EINVAL;
  197. goto fail;
  198. }
  199. dump_status_reg(&status);
  200. spi_message_init(&msg);
  201. tx[2].tx_buf = &initaddr;
  202. tx[2].len = sizeof(initaddr);
  203. spi_message_add_tail(&tx[2], &msg);
  204. ret = spi_sync(spi, &msg);
  205. if (ret)
  206. goto fail;
  207. get_status(spi, &status);
  208. dump_status_reg(&status);
  209. return 0;
  210. fail:
  211. dev_err(&mgr->dev, "Error during FPGA init.\n");
  212. return ret;
  213. }
  214. static int machxo2_write(struct fpga_manager *mgr, const char *buf,
  215. size_t count)
  216. {
  217. struct spi_device *spi = mgr->priv;
  218. struct spi_message msg;
  219. struct spi_transfer tx;
  220. static const u8 progincr[] = LSC_PROGINCRNV;
  221. u8 payload[MACHXO2_BUF_SIZE];
  222. unsigned long status;
  223. int i, ret;
  224. if (count % MACHXO2_PAGE_SIZE != 0) {
  225. dev_err(&mgr->dev, "Malformed payload.\n");
  226. return -EINVAL;
  227. }
  228. get_status(spi, &status);
  229. dump_status_reg(&status);
  230. memcpy(payload, &progincr, sizeof(progincr));
  231. for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
  232. memcpy(&payload[sizeof(progincr)], &buf[i], MACHXO2_PAGE_SIZE);
  233. memset(&tx, 0, sizeof(tx));
  234. spi_message_init(&msg);
  235. tx.tx_buf = payload;
  236. tx.len = MACHXO2_BUF_SIZE;
  237. tx.delay.value = MACHXO2_HIGH_DELAY_USEC;
  238. tx.delay.unit = SPI_DELAY_UNIT_USECS;
  239. spi_message_add_tail(&tx, &msg);
  240. ret = spi_sync(spi, &msg);
  241. if (ret) {
  242. dev_err(&mgr->dev, "Error loading the bitstream.\n");
  243. return ret;
  244. }
  245. }
  246. get_status(spi, &status);
  247. dump_status_reg(&status);
  248. return 0;
  249. }
  250. static int machxo2_write_complete(struct fpga_manager *mgr,
  251. struct fpga_image_info *info)
  252. {
  253. struct spi_device *spi = mgr->priv;
  254. struct spi_message msg;
  255. struct spi_transfer tx[2];
  256. static const u8 progdone[] = ISC_PROGRAMDONE;
  257. static const u8 refresh[] = LSC_REFRESH;
  258. unsigned long status;
  259. int ret, refreshloop = 0;
  260. memset(tx, 0, sizeof(tx));
  261. spi_message_init(&msg);
  262. tx[0].tx_buf = &progdone;
  263. tx[0].len = sizeof(progdone);
  264. spi_message_add_tail(&tx[0], &msg);
  265. ret = spi_sync(spi, &msg);
  266. if (ret)
  267. goto fail;
  268. ret = wait_until_not_busy(spi);
  269. if (ret)
  270. goto fail;
  271. get_status(spi, &status);
  272. dump_status_reg(&status);
  273. if (!test_bit(DONE, &status)) {
  274. machxo2_cleanup(mgr);
  275. ret = -EINVAL;
  276. goto fail;
  277. }
  278. do {
  279. spi_message_init(&msg);
  280. tx[1].tx_buf = &refresh;
  281. tx[1].len = sizeof(refresh);
  282. tx[1].delay.value = MACHXO2_REFRESH_USEC;
  283. tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
  284. spi_message_add_tail(&tx[1], &msg);
  285. ret = spi_sync(spi, &msg);
  286. if (ret)
  287. goto fail;
  288. /* check refresh status */
  289. get_status(spi, &status);
  290. dump_status_reg(&status);
  291. if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
  292. get_err(&status) == ENOERR)
  293. break;
  294. if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {
  295. machxo2_cleanup(mgr);
  296. ret = -EINVAL;
  297. goto fail;
  298. }
  299. } while (1);
  300. get_status(spi, &status);
  301. dump_status_reg(&status);
  302. return 0;
  303. fail:
  304. dev_err(&mgr->dev, "Refresh failed.\n");
  305. return ret;
  306. }
  307. static const struct fpga_manager_ops machxo2_ops = {
  308. .state = machxo2_spi_state,
  309. .write_init = machxo2_write_init,
  310. .write = machxo2_write,
  311. .write_complete = machxo2_write_complete,
  312. };
  313. static int machxo2_spi_probe(struct spi_device *spi)
  314. {
  315. struct device *dev = &spi->dev;
  316. struct fpga_manager *mgr;
  317. if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
  318. dev_err(dev, "Speed is too high\n");
  319. return -EINVAL;
  320. }
  321. mgr = devm_fpga_mgr_create(dev, "Lattice MachXO2 SPI FPGA Manager",
  322. &machxo2_ops, spi);
  323. if (!mgr)
  324. return -ENOMEM;
  325. spi_set_drvdata(spi, mgr);
  326. return fpga_mgr_register(mgr);
  327. }
  328. static int machxo2_spi_remove(struct spi_device *spi)
  329. {
  330. struct fpga_manager *mgr = spi_get_drvdata(spi);
  331. fpga_mgr_unregister(mgr);
  332. return 0;
  333. }
  334. static const struct of_device_id of_match[] = {
  335. { .compatible = "lattice,machxo2-slave-spi", },
  336. {}
  337. };
  338. MODULE_DEVICE_TABLE(of, of_match);
  339. static const struct spi_device_id lattice_ids[] = {
  340. { "machxo2-slave-spi", 0 },
  341. { },
  342. };
  343. MODULE_DEVICE_TABLE(spi, lattice_ids);
  344. static struct spi_driver machxo2_spi_driver = {
  345. .driver = {
  346. .name = "machxo2-slave-spi",
  347. .of_match_table = of_match_ptr(of_match),
  348. },
  349. .probe = machxo2_spi_probe,
  350. .remove = machxo2_spi_remove,
  351. .id_table = lattice_ids,
  352. };
  353. module_spi_driver(machxo2_spi_driver)
  354. MODULE_AUTHOR("Paolo Pisati <p.pisati@gmail.com>");
  355. MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI");
  356. MODULE_LICENSE("GPL v2");