ice40-spi.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * FPGA Manager Driver for Lattice iCE40.
  4. *
  5. * Copyright (c) 2016 Joel Holdsworth
  6. *
  7. * This driver adds support to the FPGA manager for configuring the SRAM of
  8. * Lattice iCE40 FPGAs through slave SPI.
  9. */
  10. #include <linux/fpga/fpga-mgr.h>
  11. #include <linux/gpio/consumer.h>
  12. #include <linux/module.h>
  13. #include <linux/of_gpio.h>
  14. #include <linux/spi/spi.h>
  15. #include <linux/stringify.h>
  16. #define ICE40_SPI_MAX_SPEED 25000000 /* Hz */
  17. #define ICE40_SPI_MIN_SPEED 1000000 /* Hz */
  18. #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
  19. #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */
  20. #define ICE40_SPI_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8)
  21. struct ice40_fpga_priv {
  22. struct spi_device *dev;
  23. struct gpio_desc *reset;
  24. struct gpio_desc *cdone;
  25. };
  26. static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
  27. {
  28. struct ice40_fpga_priv *priv = mgr->priv;
  29. return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :
  30. FPGA_MGR_STATE_UNKNOWN;
  31. }
  32. static int ice40_fpga_ops_write_init(struct fpga_manager *mgr,
  33. struct fpga_image_info *info,
  34. const char *buf, size_t count)
  35. {
  36. struct ice40_fpga_priv *priv = mgr->priv;
  37. struct spi_device *dev = priv->dev;
  38. struct spi_message message;
  39. struct spi_transfer assert_cs_then_reset_delay = {
  40. .cs_change = 1,
  41. .delay = {
  42. .value = ICE40_SPI_RESET_DELAY,
  43. .unit = SPI_DELAY_UNIT_USECS
  44. }
  45. };
  46. struct spi_transfer housekeeping_delay_then_release_cs = {
  47. .delay = {
  48. .value = ICE40_SPI_HOUSEKEEPING_DELAY,
  49. .unit = SPI_DELAY_UNIT_USECS
  50. }
  51. };
  52. int ret;
  53. if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
  54. dev_err(&dev->dev,
  55. "Partial reconfiguration is not supported\n");
  56. return -ENOTSUPP;
  57. }
  58. /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */
  59. spi_bus_lock(dev->master);
  60. gpiod_set_value(priv->reset, 1);
  61. spi_message_init(&message);
  62. spi_message_add_tail(&assert_cs_then_reset_delay, &message);
  63. ret = spi_sync_locked(dev, &message);
  64. /* Come out of reset */
  65. gpiod_set_value(priv->reset, 0);
  66. /* Abort if the chip-select failed */
  67. if (ret)
  68. goto fail;
  69. /* Check CDONE is de-asserted i.e. the FPGA is reset */
  70. if (gpiod_get_value(priv->cdone)) {
  71. dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
  72. ret = -EIO;
  73. goto fail;
  74. }
  75. /* Wait for the housekeeping to complete, and release SS_B */
  76. spi_message_init(&message);
  77. spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
  78. ret = spi_sync_locked(dev, &message);
  79. fail:
  80. spi_bus_unlock(dev->master);
  81. return ret;
  82. }
  83. static int ice40_fpga_ops_write(struct fpga_manager *mgr,
  84. const char *buf, size_t count)
  85. {
  86. struct ice40_fpga_priv *priv = mgr->priv;
  87. return spi_write(priv->dev, buf, count);
  88. }
  89. static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr,
  90. struct fpga_image_info *info)
  91. {
  92. struct ice40_fpga_priv *priv = mgr->priv;
  93. struct spi_device *dev = priv->dev;
  94. const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0};
  95. /* Check CDONE is asserted */
  96. if (!gpiod_get_value(priv->cdone)) {
  97. dev_err(&dev->dev,
  98. "CDONE was not asserted after firmware transfer\n");
  99. return -EIO;
  100. }
  101. /* Send of zero-padding to activate the firmware */
  102. return spi_write(dev, padding, sizeof(padding));
  103. }
  104. static const struct fpga_manager_ops ice40_fpga_ops = {
  105. .state = ice40_fpga_ops_state,
  106. .write_init = ice40_fpga_ops_write_init,
  107. .write = ice40_fpga_ops_write,
  108. .write_complete = ice40_fpga_ops_write_complete,
  109. };
  110. static int ice40_fpga_probe(struct spi_device *spi)
  111. {
  112. struct device *dev = &spi->dev;
  113. struct ice40_fpga_priv *priv;
  114. struct fpga_manager *mgr;
  115. int ret;
  116. priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
  117. if (!priv)
  118. return -ENOMEM;
  119. priv->dev = spi;
  120. /* Check board setup data. */
  121. if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {
  122. dev_err(dev, "SPI speed is too high, maximum speed is "
  123. __stringify(ICE40_SPI_MAX_SPEED) "\n");
  124. return -EINVAL;
  125. }
  126. if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {
  127. dev_err(dev, "SPI speed is too low, minimum speed is "
  128. __stringify(ICE40_SPI_MIN_SPEED) "\n");
  129. return -EINVAL;
  130. }
  131. if (spi->mode & SPI_CPHA) {
  132. dev_err(dev, "Bad SPI mode, CPHA not supported\n");
  133. return -EINVAL;
  134. }
  135. /* Set up the GPIOs */
  136. priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
  137. if (IS_ERR(priv->cdone)) {
  138. ret = PTR_ERR(priv->cdone);
  139. dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret);
  140. return ret;
  141. }
  142. priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
  143. if (IS_ERR(priv->reset)) {
  144. ret = PTR_ERR(priv->reset);
  145. dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret);
  146. return ret;
  147. }
  148. mgr = devm_fpga_mgr_create(dev, "Lattice iCE40 FPGA Manager",
  149. &ice40_fpga_ops, priv);
  150. if (!mgr)
  151. return -ENOMEM;
  152. spi_set_drvdata(spi, mgr);
  153. return fpga_mgr_register(mgr);
  154. }
  155. static int ice40_fpga_remove(struct spi_device *spi)
  156. {
  157. struct fpga_manager *mgr = spi_get_drvdata(spi);
  158. fpga_mgr_unregister(mgr);
  159. return 0;
  160. }
  161. static const struct of_device_id ice40_fpga_of_match[] = {
  162. { .compatible = "lattice,ice40-fpga-mgr", },
  163. {},
  164. };
  165. MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
  166. static struct spi_driver ice40_fpga_driver = {
  167. .probe = ice40_fpga_probe,
  168. .remove = ice40_fpga_remove,
  169. .driver = {
  170. .name = "ice40spi",
  171. .of_match_table = of_match_ptr(ice40_fpga_of_match),
  172. },
  173. };
  174. module_spi_driver(ice40_fpga_driver);
  175. MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>");
  176. MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
  177. MODULE_LICENSE("GPL v2");