dfl.h 18 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Driver Header File for FPGA Device Feature List (DFL) Support
  4. *
  5. * Copyright (C) 2017-2018 Intel Corporation, Inc.
  6. *
  7. * Authors:
  8. * Kang Luwei <luwei.kang@intel.com>
  9. * Zhang Yi <yi.z.zhang@intel.com>
  10. * Wu Hao <hao.wu@intel.com>
  11. * Xiao Guangrong <guangrong.xiao@linux.intel.com>
  12. */
  13. #ifndef __FPGA_DFL_H
  14. #define __FPGA_DFL_H
  15. #include <linux/bitfield.h>
  16. #include <linux/cdev.h>
  17. #include <linux/delay.h>
  18. #include <linux/eventfd.h>
  19. #include <linux/fs.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/iopoll.h>
  22. #include <linux/io-64-nonatomic-lo-hi.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/slab.h>
  25. #include <linux/uuid.h>
  26. #include <linux/fpga/fpga-region.h>
  27. /* maximum supported number of ports */
  28. #define MAX_DFL_FPGA_PORT_NUM 4
  29. /* plus one for fme device */
  30. #define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1)
  31. /* Reserved 0xfe for Header Group Register and 0xff for AFU */
  32. #define FEATURE_ID_FIU_HEADER 0xfe
  33. #define FEATURE_ID_AFU 0xff
  34. #define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  35. #define FME_FEATURE_ID_THERMAL_MGMT 0x1
  36. #define FME_FEATURE_ID_POWER_MGMT 0x2
  37. #define FME_FEATURE_ID_GLOBAL_IPERF 0x3
  38. #define FME_FEATURE_ID_GLOBAL_ERR 0x4
  39. #define FME_FEATURE_ID_PR_MGMT 0x5
  40. #define FME_FEATURE_ID_HSSI 0x6
  41. #define FME_FEATURE_ID_GLOBAL_DPERF 0x7
  42. #define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER
  43. #define PORT_FEATURE_ID_AFU FEATURE_ID_AFU
  44. #define PORT_FEATURE_ID_ERROR 0x10
  45. #define PORT_FEATURE_ID_UMSG 0x11
  46. #define PORT_FEATURE_ID_UINT 0x12
  47. #define PORT_FEATURE_ID_STP 0x13
  48. /*
  49. * Device Feature Header Register Set
  50. *
  51. * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers.
  52. * For AFUs, they have DFH + GUID as common header registers.
  53. * For private features, they only have DFH register as common header.
  54. */
  55. #define DFH 0x0
  56. #define GUID_L 0x8
  57. #define GUID_H 0x10
  58. #define NEXT_AFU 0x18
  59. #define DFH_SIZE 0x8
  60. /* Device Feature Header Register Bitfield */
  61. #define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */
  62. #define DFH_ID_FIU_FME 0
  63. #define DFH_ID_FIU_PORT 1
  64. #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */
  65. #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */
  66. #define DFH_EOL BIT_ULL(40) /* End of list */
  67. #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */
  68. #define DFH_TYPE_AFU 1
  69. #define DFH_TYPE_PRIVATE 3
  70. #define DFH_TYPE_FIU 4
  71. /* Next AFU Register Bitfield */
  72. #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */
  73. /* FME Header Register Set */
  74. #define FME_HDR_DFH DFH
  75. #define FME_HDR_GUID_L GUID_L
  76. #define FME_HDR_GUID_H GUID_H
  77. #define FME_HDR_NEXT_AFU NEXT_AFU
  78. #define FME_HDR_CAP 0x30
  79. #define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8))
  80. #define FME_HDR_BITSTREAM_ID 0x60
  81. #define FME_HDR_BITSTREAM_MD 0x68
  82. /* FME Fab Capability Register Bitfield */
  83. #define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */
  84. #define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */
  85. #define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */
  86. #define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */
  87. #define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */
  88. #define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */
  89. #define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */
  90. #define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */
  91. #define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */
  92. #define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */
  93. /* FME Port Offset Register Bitfield */
  94. /* Offset to port device feature header */
  95. #define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0)
  96. /* PCI Bar ID for this port */
  97. #define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32)
  98. /* AFU MMIO access permission. 1 - VF, 0 - PF. */
  99. #define FME_PORT_OFST_ACC_CTRL BIT_ULL(55)
  100. #define FME_PORT_OFST_ACC_PF 0
  101. #define FME_PORT_OFST_ACC_VF 1
  102. #define FME_PORT_OFST_IMP BIT_ULL(60)
  103. /* FME Error Capability Register */
  104. #define FME_ERROR_CAP 0x70
  105. /* FME Error Capability Register Bitfield */
  106. #define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
  107. #define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
  108. /* PORT Header Register Set */
  109. #define PORT_HDR_DFH DFH
  110. #define PORT_HDR_GUID_L GUID_L
  111. #define PORT_HDR_GUID_H GUID_H
  112. #define PORT_HDR_NEXT_AFU NEXT_AFU
  113. #define PORT_HDR_CAP 0x30
  114. #define PORT_HDR_CTRL 0x38
  115. #define PORT_HDR_STS 0x40
  116. #define PORT_HDR_USRCLK_CMD0 0x50
  117. #define PORT_HDR_USRCLK_CMD1 0x58
  118. #define PORT_HDR_USRCLK_STS0 0x60
  119. #define PORT_HDR_USRCLK_STS1 0x68
  120. /* Port Capability Register Bitfield */
  121. #define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */
  122. #define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */
  123. #define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */
  124. /* Port Control Register Bitfield */
  125. #define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */
  126. /* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/
  127. #define PORT_CTRL_LATENCY BIT_ULL(2)
  128. #define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */
  129. /* Port Status Register Bitfield */
  130. #define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */
  131. #define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */
  132. #define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */
  133. #define PORT_STS_PWR_STATE_NORM 0
  134. #define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */
  135. #define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */
  136. #define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */
  137. /* Port Error Capability Register */
  138. #define PORT_ERROR_CAP 0x38
  139. /* Port Error Capability Register Bitfield */
  140. #define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */
  141. #define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */
  142. /* Port Uint Capability Register */
  143. #define PORT_UINT_CAP 0x8
  144. /* Port Uint Capability Register Bitfield */
  145. #define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */
  146. #define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */
  147. /**
  148. * struct dfl_fpga_port_ops - port ops
  149. *
  150. * @name: name of this port ops, to match with port platform device.
  151. * @owner: pointer to the module which owns this port ops.
  152. * @node: node to link port ops to global list.
  153. * @get_id: get port id from hardware.
  154. * @enable_set: enable/disable the port.
  155. */
  156. struct dfl_fpga_port_ops {
  157. const char *name;
  158. struct module *owner;
  159. struct list_head node;
  160. int (*get_id)(struct platform_device *pdev);
  161. int (*enable_set)(struct platform_device *pdev, bool enable);
  162. };
  163. void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops);
  164. void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops);
  165. struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev);
  166. void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops);
  167. int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id);
  168. /**
  169. * struct dfl_feature_id - dfl private feature id
  170. *
  171. * @id: unique dfl private feature id.
  172. */
  173. struct dfl_feature_id {
  174. u16 id;
  175. };
  176. /**
  177. * struct dfl_feature_driver - dfl private feature driver
  178. *
  179. * @id_table: id_table for dfl private features supported by this driver.
  180. * @ops: ops of this dfl private feature driver.
  181. */
  182. struct dfl_feature_driver {
  183. const struct dfl_feature_id *id_table;
  184. const struct dfl_feature_ops *ops;
  185. };
  186. /**
  187. * struct dfl_feature_irq_ctx - dfl private feature interrupt context
  188. *
  189. * @irq: Linux IRQ number of this interrupt.
  190. * @trigger: eventfd context to signal when interrupt happens.
  191. * @name: irq name needed when requesting irq.
  192. */
  193. struct dfl_feature_irq_ctx {
  194. int irq;
  195. struct eventfd_ctx *trigger;
  196. char *name;
  197. };
  198. /**
  199. * struct dfl_feature - sub feature of the feature devices
  200. *
  201. * @dev: ptr to pdev of the feature device which has the sub feature.
  202. * @id: sub feature id.
  203. * @resource_index: each sub feature has one mmio resource for its registers.
  204. * this index is used to find its mmio resource from the
  205. * feature dev (platform device)'s reources.
  206. * @ioaddr: mapped mmio resource address.
  207. * @irq_ctx: interrupt context list.
  208. * @nr_irqs: number of interrupt contexts.
  209. * @ops: ops of this sub feature.
  210. * @ddev: ptr to the dfl device of this sub feature.
  211. * @priv: priv data of this feature.
  212. */
  213. struct dfl_feature {
  214. struct platform_device *dev;
  215. u16 id;
  216. int resource_index;
  217. void __iomem *ioaddr;
  218. struct dfl_feature_irq_ctx *irq_ctx;
  219. unsigned int nr_irqs;
  220. const struct dfl_feature_ops *ops;
  221. struct dfl_device *ddev;
  222. void *priv;
  223. };
  224. #define FEATURE_DEV_ID_UNUSED (-1)
  225. /**
  226. * struct dfl_feature_platform_data - platform data for feature devices
  227. *
  228. * @node: node to link feature devs to container device's port_dev_list.
  229. * @lock: mutex to protect platform data.
  230. * @cdev: cdev of feature dev.
  231. * @dev: ptr to platform device linked with this platform data.
  232. * @dfl_cdev: ptr to container device.
  233. * @id: id used for this feature device.
  234. * @disable_count: count for port disable.
  235. * @excl_open: set on feature device exclusive open.
  236. * @open_count: count for feature device open.
  237. * @num: number for sub features.
  238. * @private: ptr to feature dev private data.
  239. * @features: sub features of this feature dev.
  240. */
  241. struct dfl_feature_platform_data {
  242. struct list_head node;
  243. struct mutex lock;
  244. struct cdev cdev;
  245. struct platform_device *dev;
  246. struct dfl_fpga_cdev *dfl_cdev;
  247. int id;
  248. unsigned int disable_count;
  249. bool excl_open;
  250. int open_count;
  251. void *private;
  252. int num;
  253. struct dfl_feature features[];
  254. };
  255. static inline
  256. int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata,
  257. bool excl)
  258. {
  259. if (pdata->excl_open)
  260. return -EBUSY;
  261. if (excl) {
  262. if (pdata->open_count)
  263. return -EBUSY;
  264. pdata->excl_open = true;
  265. }
  266. pdata->open_count++;
  267. return 0;
  268. }
  269. static inline
  270. void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata)
  271. {
  272. pdata->excl_open = false;
  273. if (WARN_ON(pdata->open_count <= 0))
  274. return;
  275. pdata->open_count--;
  276. }
  277. static inline
  278. int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata)
  279. {
  280. return pdata->open_count;
  281. }
  282. static inline
  283. void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata,
  284. void *private)
  285. {
  286. pdata->private = private;
  287. }
  288. static inline
  289. void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata)
  290. {
  291. return pdata->private;
  292. }
  293. struct dfl_feature_ops {
  294. int (*init)(struct platform_device *pdev, struct dfl_feature *feature);
  295. void (*uinit)(struct platform_device *pdev,
  296. struct dfl_feature *feature);
  297. long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature,
  298. unsigned int cmd, unsigned long arg);
  299. };
  300. #define DFL_FPGA_FEATURE_DEV_FME "dfl-fme"
  301. #define DFL_FPGA_FEATURE_DEV_PORT "dfl-port"
  302. void dfl_fpga_dev_feature_uinit(struct platform_device *pdev);
  303. int dfl_fpga_dev_feature_init(struct platform_device *pdev,
  304. struct dfl_feature_driver *feature_drvs);
  305. int dfl_fpga_dev_ops_register(struct platform_device *pdev,
  306. const struct file_operations *fops,
  307. struct module *owner);
  308. void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
  309. static inline
  310. struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode)
  311. {
  312. struct dfl_feature_platform_data *pdata;
  313. pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
  314. cdev);
  315. return pdata->dev;
  316. }
  317. #define dfl_fpga_dev_for_each_feature(pdata, feature) \
  318. for ((feature) = (pdata)->features; \
  319. (feature) < (pdata)->features + (pdata)->num; (feature)++)
  320. static inline
  321. struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id)
  322. {
  323. struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
  324. struct dfl_feature *feature;
  325. dfl_fpga_dev_for_each_feature(pdata, feature)
  326. if (feature->id == id)
  327. return feature;
  328. return NULL;
  329. }
  330. static inline
  331. void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id)
  332. {
  333. struct dfl_feature *feature = dfl_get_feature_by_id(dev, id);
  334. if (feature && feature->ioaddr)
  335. return feature->ioaddr;
  336. WARN_ON(1);
  337. return NULL;
  338. }
  339. static inline bool is_dfl_feature_present(struct device *dev, u16 id)
  340. {
  341. return !!dfl_get_feature_ioaddr_by_id(dev, id);
  342. }
  343. static inline
  344. struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata)
  345. {
  346. return pdata->dev->dev.parent->parent;
  347. }
  348. static inline bool dfl_feature_is_fme(void __iomem *base)
  349. {
  350. u64 v = readq(base + DFH);
  351. return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
  352. (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
  353. }
  354. static inline bool dfl_feature_is_port(void __iomem *base)
  355. {
  356. u64 v = readq(base + DFH);
  357. return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
  358. (FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
  359. }
  360. static inline u8 dfl_feature_revision(void __iomem *base)
  361. {
  362. return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
  363. }
  364. /**
  365. * struct dfl_fpga_enum_info - DFL FPGA enumeration information
  366. *
  367. * @dev: parent device.
  368. * @dfls: list of device feature lists.
  369. * @nr_irqs: number of irqs for all feature devices.
  370. * @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
  371. */
  372. struct dfl_fpga_enum_info {
  373. struct device *dev;
  374. struct list_head dfls;
  375. unsigned int nr_irqs;
  376. int *irq_table;
  377. };
  378. /**
  379. * struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info
  380. *
  381. * @start: base address of this device feature list.
  382. * @len: size of this device feature list.
  383. * @node: node in list of device feature lists.
  384. */
  385. struct dfl_fpga_enum_dfl {
  386. resource_size_t start;
  387. resource_size_t len;
  388. struct list_head node;
  389. };
  390. struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev);
  391. int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info,
  392. resource_size_t start, resource_size_t len);
  393. int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info,
  394. unsigned int nr_irqs, int *irq_table);
  395. void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info);
  396. /**
  397. * struct dfl_fpga_cdev - container device of DFL based FPGA
  398. *
  399. * @parent: parent device of this container device.
  400. * @region: base fpga region.
  401. * @fme_dev: FME feature device under this container device.
  402. * @lock: mutex lock to protect the port device list.
  403. * @port_dev_list: list of all port feature devices under this container device.
  404. * @released_port_num: released port number under this container device.
  405. */
  406. struct dfl_fpga_cdev {
  407. struct device *parent;
  408. struct fpga_region *region;
  409. struct device *fme_dev;
  410. struct mutex lock;
  411. struct list_head port_dev_list;
  412. int released_port_num;
  413. };
  414. struct dfl_fpga_cdev *
  415. dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info);
  416. void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev);
  417. /*
  418. * need to drop the device reference with put_device() after use port platform
  419. * device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port
  420. * functions.
  421. */
  422. struct platform_device *
  423. __dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
  424. int (*match)(struct platform_device *, void *));
  425. static inline struct platform_device *
  426. dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data,
  427. int (*match)(struct platform_device *, void *))
  428. {
  429. struct platform_device *pdev;
  430. mutex_lock(&cdev->lock);
  431. pdev = __dfl_fpga_cdev_find_port(cdev, data, match);
  432. mutex_unlock(&cdev->lock);
  433. return pdev;
  434. }
  435. int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id);
  436. int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id);
  437. void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev);
  438. int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf);
  439. int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start,
  440. unsigned int count, int32_t *fds);
  441. long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev,
  442. struct dfl_feature *feature,
  443. unsigned long arg);
  444. long dfl_feature_ioctl_set_irq(struct platform_device *pdev,
  445. struct dfl_feature *feature,
  446. unsigned long arg);
  447. /**
  448. * enum dfl_id_type - define the DFL FIU types
  449. */
  450. enum dfl_id_type {
  451. FME_ID,
  452. PORT_ID,
  453. DFL_ID_MAX,
  454. };
  455. /**
  456. * struct dfl_device_id - dfl device identifier
  457. * @type: contains 4 bits DFL FIU type of the device. See enum dfl_id_type.
  458. * @feature_id: contains 12 bits feature identifier local to its DFL FIU type.
  459. * @driver_data: driver specific data.
  460. */
  461. struct dfl_device_id {
  462. u8 type;
  463. u16 feature_id;
  464. unsigned long driver_data;
  465. };
  466. /**
  467. * struct dfl_device - represent an dfl device on dfl bus
  468. *
  469. * @dev: generic device interface.
  470. * @id: id of the dfl device.
  471. * @type: type of DFL FIU of the device. See enum dfl_id_type.
  472. * @feature_id: 16 bits feature identifier local to its DFL FIU type.
  473. * @mmio_res: mmio resource of this dfl device.
  474. * @irqs: list of Linux IRQ numbers of this dfl device.
  475. * @num_irqs: number of IRQs supported by this dfl device.
  476. * @cdev: pointer to DFL FPGA container device this dfl device belongs to.
  477. * @id_entry: matched id entry in dfl driver's id table.
  478. */
  479. struct dfl_device {
  480. struct device dev;
  481. int id;
  482. u8 type;
  483. u16 feature_id;
  484. struct resource mmio_res;
  485. int *irqs;
  486. unsigned int num_irqs;
  487. struct dfl_fpga_cdev *cdev;
  488. const struct dfl_device_id *id_entry;
  489. };
  490. /**
  491. * struct dfl_driver - represent an dfl device driver
  492. *
  493. * @drv: driver model structure.
  494. * @id_table: pointer to table of device IDs the driver is interested in.
  495. * { } member terminated.
  496. * @probe: mandatory callback for device binding.
  497. * @remove: callback for device unbinding.
  498. */
  499. struct dfl_driver {
  500. struct device_driver drv;
  501. const struct dfl_device_id *id_table;
  502. int (*probe)(struct dfl_device *dfl_dev);
  503. void (*remove)(struct dfl_device *dfl_dev);
  504. };
  505. #define to_dfl_dev(d) container_of(d, struct dfl_device, dev)
  506. #define to_dfl_drv(d) container_of(d, struct dfl_driver, drv)
  507. /*
  508. * use a macro to avoid include chaining to get THIS_MODULE.
  509. */
  510. #define dfl_driver_register(drv) \
  511. __dfl_driver_register(drv, THIS_MODULE)
  512. int __dfl_driver_register(struct dfl_driver *dfl_drv, struct module *owner);
  513. void dfl_driver_unregister(struct dfl_driver *dfl_drv);
  514. /*
  515. * module_dfl_driver() - Helper macro for drivers that don't do
  516. * anything special in module init/exit. This eliminates a lot of
  517. * boilerplate. Each module may only use this macro once, and
  518. * calling it replaces module_init() and module_exit().
  519. */
  520. #define module_dfl_driver(__dfl_driver) \
  521. module_driver(__dfl_driver, dfl_driver_register, \
  522. dfl_driver_unregister)
  523. #endif /* __FPGA_DFL_H */