dfl-fme-mgr.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA Manager Driver for FPGA Management Engine (FME)
  4. *
  5. * Copyright (C) 2017-2018 Intel Corporation, Inc.
  6. *
  7. * Authors:
  8. * Kang Luwei <luwei.kang@intel.com>
  9. * Xiao Guangrong <guangrong.xiao@linux.intel.com>
  10. * Wu Hao <hao.wu@intel.com>
  11. * Joseph Grecco <joe.grecco@intel.com>
  12. * Enno Luebbers <enno.luebbers@intel.com>
  13. * Tim Whisonant <tim.whisonant@intel.com>
  14. * Ananda Ravuri <ananda.ravuri@intel.com>
  15. * Christopher Rauer <christopher.rauer@intel.com>
  16. * Henry Mitchel <henry.mitchel@intel.com>
  17. */
  18. #include <linux/bitfield.h>
  19. #include <linux/module.h>
  20. #include <linux/iopoll.h>
  21. #include <linux/io-64-nonatomic-lo-hi.h>
  22. #include <linux/fpga/fpga-mgr.h>
  23. #include "dfl-fme-pr.h"
  24. /* FME Partial Reconfiguration Sub Feature Register Set */
  25. #define FME_PR_DFH 0x0
  26. #define FME_PR_CTRL 0x8
  27. #define FME_PR_STS 0x10
  28. #define FME_PR_DATA 0x18
  29. #define FME_PR_ERR 0x20
  30. #define FME_PR_INTFC_ID_L 0xA8
  31. #define FME_PR_INTFC_ID_H 0xB0
  32. /* FME PR Control Register Bitfield */
  33. #define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
  34. #define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
  35. #define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
  36. #define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
  37. #define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
  38. /* FME PR Status Register Bitfield */
  39. /* Number of available entries in HW queue inside the PR engine. */
  40. #define FME_PR_STS_PR_CREDIT GENMASK_ULL(8, 0)
  41. #define FME_PR_STS_PR_STS BIT_ULL(16) /* PR operation status */
  42. #define FME_PR_STS_PR_STS_IDLE 0
  43. #define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20) /* Controller status */
  44. #define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24) /* PR host status */
  45. /* FME PR Data Register Bitfield */
  46. /* PR data from the raw-binary file. */
  47. #define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)
  48. /* FME PR Error Register */
  49. /* PR Operation errors detected. */
  50. #define FME_PR_ERR_OPERATION_ERR BIT_ULL(0)
  51. /* CRC error detected. */
  52. #define FME_PR_ERR_CRC_ERR BIT_ULL(1)
  53. /* Incompatible PR bitstream detected. */
  54. #define FME_PR_ERR_INCOMPATIBLE_BS BIT_ULL(2)
  55. /* PR data push protocol violated. */
  56. #define FME_PR_ERR_PROTOCOL_ERR BIT_ULL(3)
  57. /* PR data fifo overflow error detected */
  58. #define FME_PR_ERR_FIFO_OVERFLOW BIT_ULL(4)
  59. #define PR_WAIT_TIMEOUT 8000000
  60. #define PR_HOST_STATUS_IDLE 0
  61. struct fme_mgr_priv {
  62. void __iomem *ioaddr;
  63. u64 pr_error;
  64. };
  65. static u64 pr_error_to_mgr_status(u64 err)
  66. {
  67. u64 status = 0;
  68. if (err & FME_PR_ERR_OPERATION_ERR)
  69. status |= FPGA_MGR_STATUS_OPERATION_ERR;
  70. if (err & FME_PR_ERR_CRC_ERR)
  71. status |= FPGA_MGR_STATUS_CRC_ERR;
  72. if (err & FME_PR_ERR_INCOMPATIBLE_BS)
  73. status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
  74. if (err & FME_PR_ERR_PROTOCOL_ERR)
  75. status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
  76. if (err & FME_PR_ERR_FIFO_OVERFLOW)
  77. status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
  78. return status;
  79. }
  80. static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
  81. {
  82. u64 pr_status, pr_error;
  83. pr_status = readq(fme_pr + FME_PR_STS);
  84. if (!(pr_status & FME_PR_STS_PR_STS))
  85. return 0;
  86. pr_error = readq(fme_pr + FME_PR_ERR);
  87. writeq(pr_error, fme_pr + FME_PR_ERR);
  88. return pr_error;
  89. }
  90. static int fme_mgr_write_init(struct fpga_manager *mgr,
  91. struct fpga_image_info *info,
  92. const char *buf, size_t count)
  93. {
  94. struct device *dev = &mgr->dev;
  95. struct fme_mgr_priv *priv = mgr->priv;
  96. void __iomem *fme_pr = priv->ioaddr;
  97. u64 pr_ctrl, pr_status;
  98. if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
  99. dev_err(dev, "only supports partial reconfiguration.\n");
  100. return -EINVAL;
  101. }
  102. dev_dbg(dev, "resetting PR before initiated PR\n");
  103. pr_ctrl = readq(fme_pr + FME_PR_CTRL);
  104. pr_ctrl |= FME_PR_CTRL_PR_RST;
  105. writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
  106. if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
  107. pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
  108. PR_WAIT_TIMEOUT)) {
  109. dev_err(dev, "PR Reset ACK timeout\n");
  110. return -ETIMEDOUT;
  111. }
  112. pr_ctrl = readq(fme_pr + FME_PR_CTRL);
  113. pr_ctrl &= ~FME_PR_CTRL_PR_RST;
  114. writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
  115. dev_dbg(dev,
  116. "waiting for PR resource in HW to be initialized and ready\n");
  117. if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
  118. (pr_status & FME_PR_STS_PR_STS) ==
  119. FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
  120. dev_err(dev, "PR Status timeout\n");
  121. priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
  122. return -ETIMEDOUT;
  123. }
  124. dev_dbg(dev, "check and clear previous PR error\n");
  125. priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
  126. if (priv->pr_error)
  127. dev_dbg(dev, "previous PR error detected %llx\n",
  128. (unsigned long long)priv->pr_error);
  129. dev_dbg(dev, "set PR port ID\n");
  130. pr_ctrl = readq(fme_pr + FME_PR_CTRL);
  131. pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
  132. pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
  133. writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
  134. return 0;
  135. }
  136. static int fme_mgr_write(struct fpga_manager *mgr,
  137. const char *buf, size_t count)
  138. {
  139. struct device *dev = &mgr->dev;
  140. struct fme_mgr_priv *priv = mgr->priv;
  141. void __iomem *fme_pr = priv->ioaddr;
  142. u64 pr_ctrl, pr_status, pr_data;
  143. int delay = 0, pr_credit, i = 0;
  144. dev_dbg(dev, "start request\n");
  145. pr_ctrl = readq(fme_pr + FME_PR_CTRL);
  146. pr_ctrl |= FME_PR_CTRL_PR_START;
  147. writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
  148. dev_dbg(dev, "pushing data from bitstream to HW\n");
  149. /*
  150. * driver can push data to PR hardware using PR_DATA register once HW
  151. * has enough pr_credit (> 1), pr_credit reduces one for every 32bit
  152. * pr data write to PR_DATA register. If pr_credit <= 1, driver needs
  153. * to wait for enough pr_credit from hardware by polling.
  154. */
  155. pr_status = readq(fme_pr + FME_PR_STS);
  156. pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
  157. while (count > 0) {
  158. while (pr_credit <= 1) {
  159. if (delay++ > PR_WAIT_TIMEOUT) {
  160. dev_err(dev, "PR_CREDIT timeout\n");
  161. return -ETIMEDOUT;
  162. }
  163. udelay(1);
  164. pr_status = readq(fme_pr + FME_PR_STS);
  165. pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
  166. }
  167. if (count < 4) {
  168. dev_err(dev, "Invalid PR bitstream size\n");
  169. return -EINVAL;
  170. }
  171. pr_data = 0;
  172. pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
  173. *(((u32 *)buf) + i));
  174. writeq(pr_data, fme_pr + FME_PR_DATA);
  175. count -= 4;
  176. pr_credit--;
  177. i++;
  178. }
  179. return 0;
  180. }
  181. static int fme_mgr_write_complete(struct fpga_manager *mgr,
  182. struct fpga_image_info *info)
  183. {
  184. struct device *dev = &mgr->dev;
  185. struct fme_mgr_priv *priv = mgr->priv;
  186. void __iomem *fme_pr = priv->ioaddr;
  187. u64 pr_ctrl;
  188. pr_ctrl = readq(fme_pr + FME_PR_CTRL);
  189. pr_ctrl |= FME_PR_CTRL_PR_COMPLETE;
  190. writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
  191. dev_dbg(dev, "green bitstream push complete\n");
  192. dev_dbg(dev, "waiting for HW to release PR resource\n");
  193. if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
  194. !(pr_ctrl & FME_PR_CTRL_PR_START), 1,
  195. PR_WAIT_TIMEOUT)) {
  196. dev_err(dev, "PR Completion ACK timeout.\n");
  197. return -ETIMEDOUT;
  198. }
  199. dev_dbg(dev, "PR operation complete, checking status\n");
  200. priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
  201. if (priv->pr_error) {
  202. dev_dbg(dev, "PR error detected %llx\n",
  203. (unsigned long long)priv->pr_error);
  204. return -EIO;
  205. }
  206. dev_dbg(dev, "PR done successfully\n");
  207. return 0;
  208. }
  209. static enum fpga_mgr_states fme_mgr_state(struct fpga_manager *mgr)
  210. {
  211. return FPGA_MGR_STATE_UNKNOWN;
  212. }
  213. static u64 fme_mgr_status(struct fpga_manager *mgr)
  214. {
  215. struct fme_mgr_priv *priv = mgr->priv;
  216. return pr_error_to_mgr_status(priv->pr_error);
  217. }
  218. static const struct fpga_manager_ops fme_mgr_ops = {
  219. .write_init = fme_mgr_write_init,
  220. .write = fme_mgr_write,
  221. .write_complete = fme_mgr_write_complete,
  222. .state = fme_mgr_state,
  223. .status = fme_mgr_status,
  224. };
  225. static void fme_mgr_get_compat_id(void __iomem *fme_pr,
  226. struct fpga_compat_id *id)
  227. {
  228. id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);
  229. id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);
  230. }
  231. static int fme_mgr_probe(struct platform_device *pdev)
  232. {
  233. struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
  234. struct fpga_compat_id *compat_id;
  235. struct device *dev = &pdev->dev;
  236. struct fme_mgr_priv *priv;
  237. struct fpga_manager *mgr;
  238. struct resource *res;
  239. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  240. if (!priv)
  241. return -ENOMEM;
  242. if (pdata->ioaddr)
  243. priv->ioaddr = pdata->ioaddr;
  244. if (!priv->ioaddr) {
  245. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  246. priv->ioaddr = devm_ioremap_resource(dev, res);
  247. if (IS_ERR(priv->ioaddr))
  248. return PTR_ERR(priv->ioaddr);
  249. }
  250. compat_id = devm_kzalloc(dev, sizeof(*compat_id), GFP_KERNEL);
  251. if (!compat_id)
  252. return -ENOMEM;
  253. fme_mgr_get_compat_id(priv->ioaddr, compat_id);
  254. mgr = devm_fpga_mgr_create(dev, "DFL FME FPGA Manager",
  255. &fme_mgr_ops, priv);
  256. if (!mgr)
  257. return -ENOMEM;
  258. mgr->compat_id = compat_id;
  259. platform_set_drvdata(pdev, mgr);
  260. return fpga_mgr_register(mgr);
  261. }
  262. static int fme_mgr_remove(struct platform_device *pdev)
  263. {
  264. struct fpga_manager *mgr = platform_get_drvdata(pdev);
  265. fpga_mgr_unregister(mgr);
  266. return 0;
  267. }
  268. static struct platform_driver fme_mgr_driver = {
  269. .driver = {
  270. .name = DFL_FPGA_FME_MGR,
  271. },
  272. .probe = fme_mgr_probe,
  273. .remove = fme_mgr_remove,
  274. };
  275. module_platform_driver(fme_mgr_driver);
  276. MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
  277. MODULE_AUTHOR("Intel Corporation");
  278. MODULE_LICENSE("GPL v2");
  279. MODULE_ALIAS("platform:dfl-fme-mgr");