altera-pr-ip-core.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Altera Partial Reconfiguration IP Core
  4. *
  5. * Copyright (C) 2016-2017 Intel Corporation
  6. *
  7. * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
  8. * by Alan Tull <atull@opensource.altera.com>
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/fpga/altera-pr-ip-core.h>
  12. #include <linux/fpga/fpga-mgr.h>
  13. #include <linux/module.h>
  14. #define ALT_PR_DATA_OFST 0x00
  15. #define ALT_PR_CSR_OFST 0x04
  16. #define ALT_PR_CSR_PR_START BIT(0)
  17. #define ALT_PR_CSR_STATUS_SFT 2
  18. #define ALT_PR_CSR_STATUS_MSK (7 << ALT_PR_CSR_STATUS_SFT)
  19. #define ALT_PR_CSR_STATUS_NRESET (0 << ALT_PR_CSR_STATUS_SFT)
  20. #define ALT_PR_CSR_STATUS_PR_ERR (1 << ALT_PR_CSR_STATUS_SFT)
  21. #define ALT_PR_CSR_STATUS_CRC_ERR (2 << ALT_PR_CSR_STATUS_SFT)
  22. #define ALT_PR_CSR_STATUS_BAD_BITS (3 << ALT_PR_CSR_STATUS_SFT)
  23. #define ALT_PR_CSR_STATUS_PR_IN_PROG (4 << ALT_PR_CSR_STATUS_SFT)
  24. #define ALT_PR_CSR_STATUS_PR_SUCCESS (5 << ALT_PR_CSR_STATUS_SFT)
  25. struct alt_pr_priv {
  26. void __iomem *reg_base;
  27. };
  28. static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
  29. {
  30. struct alt_pr_priv *priv = mgr->priv;
  31. const char *err = "unknown";
  32. enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
  33. u32 val;
  34. val = readl(priv->reg_base + ALT_PR_CSR_OFST);
  35. val &= ALT_PR_CSR_STATUS_MSK;
  36. switch (val) {
  37. case ALT_PR_CSR_STATUS_NRESET:
  38. return FPGA_MGR_STATE_RESET;
  39. case ALT_PR_CSR_STATUS_PR_ERR:
  40. err = "pr error";
  41. ret = FPGA_MGR_STATE_WRITE_ERR;
  42. break;
  43. case ALT_PR_CSR_STATUS_CRC_ERR:
  44. err = "crc error";
  45. ret = FPGA_MGR_STATE_WRITE_ERR;
  46. break;
  47. case ALT_PR_CSR_STATUS_BAD_BITS:
  48. err = "bad bits";
  49. ret = FPGA_MGR_STATE_WRITE_ERR;
  50. break;
  51. case ALT_PR_CSR_STATUS_PR_IN_PROG:
  52. return FPGA_MGR_STATE_WRITE;
  53. case ALT_PR_CSR_STATUS_PR_SUCCESS:
  54. return FPGA_MGR_STATE_OPERATING;
  55. default:
  56. break;
  57. }
  58. dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
  59. val, err, __func__);
  60. return ret;
  61. }
  62. static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
  63. struct fpga_image_info *info,
  64. const char *buf, size_t count)
  65. {
  66. struct alt_pr_priv *priv = mgr->priv;
  67. u32 val;
  68. if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
  69. dev_err(&mgr->dev, "%s Partial Reconfiguration flag not set\n",
  70. __func__);
  71. return -EINVAL;
  72. }
  73. val = readl(priv->reg_base + ALT_PR_CSR_OFST);
  74. if (val & ALT_PR_CSR_PR_START) {
  75. dev_err(&mgr->dev,
  76. "%s Partial Reconfiguration already started\n",
  77. __func__);
  78. return -EINVAL;
  79. }
  80. writel(val | ALT_PR_CSR_PR_START, priv->reg_base + ALT_PR_CSR_OFST);
  81. return 0;
  82. }
  83. static int alt_pr_fpga_write(struct fpga_manager *mgr, const char *buf,
  84. size_t count)
  85. {
  86. struct alt_pr_priv *priv = mgr->priv;
  87. u32 *buffer_32 = (u32 *)buf;
  88. size_t i = 0;
  89. if (count <= 0)
  90. return -EINVAL;
  91. /* Write out the complete 32-bit chunks */
  92. while (count >= sizeof(u32)) {
  93. writel(buffer_32[i++], priv->reg_base);
  94. count -= sizeof(u32);
  95. }
  96. /* Write out remaining non 32-bit chunks */
  97. switch (count) {
  98. case 3:
  99. writel(buffer_32[i++] & 0x00ffffff, priv->reg_base);
  100. break;
  101. case 2:
  102. writel(buffer_32[i++] & 0x0000ffff, priv->reg_base);
  103. break;
  104. case 1:
  105. writel(buffer_32[i++] & 0x000000ff, priv->reg_base);
  106. break;
  107. case 0:
  108. break;
  109. default:
  110. /* This will never happen */
  111. return -EFAULT;
  112. }
  113. if (alt_pr_fpga_state(mgr) == FPGA_MGR_STATE_WRITE_ERR)
  114. return -EIO;
  115. return 0;
  116. }
  117. static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
  118. struct fpga_image_info *info)
  119. {
  120. u32 i = 0;
  121. do {
  122. switch (alt_pr_fpga_state(mgr)) {
  123. case FPGA_MGR_STATE_WRITE_ERR:
  124. return -EIO;
  125. case FPGA_MGR_STATE_OPERATING:
  126. dev_info(&mgr->dev,
  127. "successful partial reconfiguration\n");
  128. return 0;
  129. default:
  130. break;
  131. }
  132. udelay(1);
  133. } while (info->config_complete_timeout_us > i++);
  134. dev_err(&mgr->dev, "timed out waiting for write to complete\n");
  135. return -ETIMEDOUT;
  136. }
  137. static const struct fpga_manager_ops alt_pr_ops = {
  138. .state = alt_pr_fpga_state,
  139. .write_init = alt_pr_fpga_write_init,
  140. .write = alt_pr_fpga_write,
  141. .write_complete = alt_pr_fpga_write_complete,
  142. };
  143. int alt_pr_register(struct device *dev, void __iomem *reg_base)
  144. {
  145. struct alt_pr_priv *priv;
  146. struct fpga_manager *mgr;
  147. u32 val;
  148. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  149. if (!priv)
  150. return -ENOMEM;
  151. priv->reg_base = reg_base;
  152. val = readl(priv->reg_base + ALT_PR_CSR_OFST);
  153. dev_dbg(dev, "%s status=%d start=%d\n", __func__,
  154. (val & ALT_PR_CSR_STATUS_MSK) >> ALT_PR_CSR_STATUS_SFT,
  155. (int)(val & ALT_PR_CSR_PR_START));
  156. mgr = devm_fpga_mgr_create(dev, dev_name(dev), &alt_pr_ops, priv);
  157. if (!mgr)
  158. return -ENOMEM;
  159. dev_set_drvdata(dev, mgr);
  160. return fpga_mgr_register(mgr);
  161. }
  162. EXPORT_SYMBOL_GPL(alt_pr_register);
  163. void alt_pr_unregister(struct device *dev)
  164. {
  165. struct fpga_manager *mgr = dev_get_drvdata(dev);
  166. dev_dbg(dev, "%s\n", __func__);
  167. fpga_mgr_unregister(mgr);
  168. }
  169. EXPORT_SYMBOL_GPL(alt_pr_unregister);
  170. MODULE_AUTHOR("Matthew Gerlach <matthew.gerlach@linux.intel.com>");
  171. MODULE_DESCRIPTION("Altera Partial Reconfiguration IP Core");
  172. MODULE_LICENSE("GPL v2");