altera-hps2fpga.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices
  4. *
  5. * Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved.
  6. *
  7. * Includes this patch from the mailing list:
  8. * fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters
  9. * Signed-off-by: Anatolij Gustschin <agust@denx.de>
  10. */
  11. /*
  12. * This driver manages bridges on a Altera SOCFPGA between the ARM host
  13. * processor system (HPS) and the embedded FPGA.
  14. *
  15. * This driver supports enabling and disabling of the configured ports, which
  16. * allows for safe reprogramming of the FPGA, assuming that the new FPGA image
  17. * uses the same port configuration. Bridges must be disabled before
  18. * reprogramming the FPGA and re-enabled after the FPGA has been programmed.
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/fpga/fpga-bridge.h>
  22. #include <linux/kernel.h>
  23. #include <linux/mfd/syscon.h>
  24. #include <linux/module.h>
  25. #include <linux/of_platform.h>
  26. #include <linux/regmap.h>
  27. #include <linux/reset.h>
  28. #include <linux/spinlock.h>
  29. #define ALT_L3_REMAP_OFST 0x0
  30. #define ALT_L3_REMAP_MPUZERO_MSK 0x00000001
  31. #define ALT_L3_REMAP_H2F_MSK 0x00000008
  32. #define ALT_L3_REMAP_LWH2F_MSK 0x00000010
  33. #define HPS2FPGA_BRIDGE_NAME "hps2fpga"
  34. #define LWHPS2FPGA_BRIDGE_NAME "lwhps2fpga"
  35. #define FPGA2HPS_BRIDGE_NAME "fpga2hps"
  36. struct altera_hps2fpga_data {
  37. const char *name;
  38. struct reset_control *bridge_reset;
  39. struct regmap *l3reg;
  40. unsigned int remap_mask;
  41. struct clk *clk;
  42. };
  43. static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge)
  44. {
  45. struct altera_hps2fpga_data *priv = bridge->priv;
  46. return reset_control_status(priv->bridge_reset);
  47. }
  48. /* The L3 REMAP register is write only, so keep a cached value. */
  49. static unsigned int l3_remap_shadow;
  50. static DEFINE_SPINLOCK(l3_remap_lock);
  51. static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv,
  52. bool enable)
  53. {
  54. unsigned long flags;
  55. int ret;
  56. /* bring bridge out of reset */
  57. if (enable)
  58. ret = reset_control_deassert(priv->bridge_reset);
  59. else
  60. ret = reset_control_assert(priv->bridge_reset);
  61. if (ret)
  62. return ret;
  63. /* Allow bridge to be visible to L3 masters or not */
  64. if (priv->remap_mask) {
  65. spin_lock_irqsave(&l3_remap_lock, flags);
  66. l3_remap_shadow |= ALT_L3_REMAP_MPUZERO_MSK;
  67. if (enable)
  68. l3_remap_shadow |= priv->remap_mask;
  69. else
  70. l3_remap_shadow &= ~priv->remap_mask;
  71. ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST,
  72. l3_remap_shadow);
  73. spin_unlock_irqrestore(&l3_remap_lock, flags);
  74. }
  75. return ret;
  76. }
  77. static int alt_hps2fpga_enable_set(struct fpga_bridge *bridge, bool enable)
  78. {
  79. return _alt_hps2fpga_enable_set(bridge->priv, enable);
  80. }
  81. static const struct fpga_bridge_ops altera_hps2fpga_br_ops = {
  82. .enable_set = alt_hps2fpga_enable_set,
  83. .enable_show = alt_hps2fpga_enable_show,
  84. };
  85. static struct altera_hps2fpga_data hps2fpga_data = {
  86. .name = HPS2FPGA_BRIDGE_NAME,
  87. .remap_mask = ALT_L3_REMAP_H2F_MSK,
  88. };
  89. static struct altera_hps2fpga_data lwhps2fpga_data = {
  90. .name = LWHPS2FPGA_BRIDGE_NAME,
  91. .remap_mask = ALT_L3_REMAP_LWH2F_MSK,
  92. };
  93. static struct altera_hps2fpga_data fpga2hps_data = {
  94. .name = FPGA2HPS_BRIDGE_NAME,
  95. };
  96. static const struct of_device_id altera_fpga_of_match[] = {
  97. { .compatible = "altr,socfpga-hps2fpga-bridge",
  98. .data = &hps2fpga_data },
  99. { .compatible = "altr,socfpga-lwhps2fpga-bridge",
  100. .data = &lwhps2fpga_data },
  101. { .compatible = "altr,socfpga-fpga2hps-bridge",
  102. .data = &fpga2hps_data },
  103. {},
  104. };
  105. static int alt_fpga_bridge_probe(struct platform_device *pdev)
  106. {
  107. struct device *dev = &pdev->dev;
  108. struct altera_hps2fpga_data *priv;
  109. const struct of_device_id *of_id;
  110. struct fpga_bridge *br;
  111. u32 enable;
  112. int ret;
  113. of_id = of_match_device(altera_fpga_of_match, dev);
  114. if (!of_id) {
  115. dev_err(dev, "failed to match device\n");
  116. return -ENODEV;
  117. }
  118. priv = (struct altera_hps2fpga_data *)of_id->data;
  119. priv->bridge_reset = of_reset_control_get_exclusive_by_index(dev->of_node,
  120. 0);
  121. if (IS_ERR(priv->bridge_reset)) {
  122. dev_err(dev, "Could not get %s reset control\n", priv->name);
  123. return PTR_ERR(priv->bridge_reset);
  124. }
  125. if (priv->remap_mask) {
  126. priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs");
  127. if (IS_ERR(priv->l3reg)) {
  128. dev_err(dev, "regmap for altr,l3regs lookup failed\n");
  129. return PTR_ERR(priv->l3reg);
  130. }
  131. }
  132. priv->clk = devm_clk_get(dev, NULL);
  133. if (IS_ERR(priv->clk)) {
  134. dev_err(dev, "no clock specified\n");
  135. return PTR_ERR(priv->clk);
  136. }
  137. ret = clk_prepare_enable(priv->clk);
  138. if (ret) {
  139. dev_err(dev, "could not enable clock\n");
  140. return -EBUSY;
  141. }
  142. if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) {
  143. if (enable > 1) {
  144. dev_warn(dev, "invalid bridge-enable %u > 1\n", enable);
  145. } else {
  146. dev_info(dev, "%s bridge\n",
  147. (enable ? "enabling" : "disabling"));
  148. ret = _alt_hps2fpga_enable_set(priv, enable);
  149. if (ret)
  150. goto err;
  151. }
  152. }
  153. br = devm_fpga_bridge_create(dev, priv->name,
  154. &altera_hps2fpga_br_ops, priv);
  155. if (!br) {
  156. ret = -ENOMEM;
  157. goto err;
  158. }
  159. platform_set_drvdata(pdev, br);
  160. ret = fpga_bridge_register(br);
  161. if (ret)
  162. goto err;
  163. return 0;
  164. err:
  165. clk_disable_unprepare(priv->clk);
  166. return ret;
  167. }
  168. static int alt_fpga_bridge_remove(struct platform_device *pdev)
  169. {
  170. struct fpga_bridge *bridge = platform_get_drvdata(pdev);
  171. struct altera_hps2fpga_data *priv = bridge->priv;
  172. fpga_bridge_unregister(bridge);
  173. clk_disable_unprepare(priv->clk);
  174. return 0;
  175. }
  176. MODULE_DEVICE_TABLE(of, altera_fpga_of_match);
  177. static struct platform_driver alt_fpga_bridge_driver = {
  178. .probe = alt_fpga_bridge_probe,
  179. .remove = alt_fpga_bridge_remove,
  180. .driver = {
  181. .name = "altera_hps2fpga_bridge",
  182. .of_match_table = of_match_ptr(altera_fpga_of_match),
  183. },
  184. };
  185. module_platform_driver(alt_fpga_bridge_driver);
  186. MODULE_DESCRIPTION("Altera SoCFPGA HPS to FPGA Bridge");
  187. MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
  188. MODULE_LICENSE("GPL v2");