altera-cvp.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
  4. *
  5. * Copyright (C) 2017 DENX Software Engineering
  6. *
  7. * Anatolij Gustschin <agust@denx.de>
  8. *
  9. * Manage Altera FPGA firmware using PCIe CvP.
  10. * Firmware must be in binary "rbf" format.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/fpga/fpga-mgr.h>
  15. #include <linux/module.h>
  16. #include <linux/pci.h>
  17. #include <linux/sizes.h>
  18. #define CVP_BAR 0 /* BAR used for data transfer in memory mode */
  19. #define CVP_DUMMY_WR 244 /* dummy writes to clear CvP state machine */
  20. #define TIMEOUT_US 2000 /* CVP STATUS timeout for USERMODE polling */
  21. /* Vendor Specific Extended Capability Registers */
  22. #define VSE_PCIE_EXT_CAP_ID 0x0
  23. #define VSE_PCIE_EXT_CAP_ID_VAL 0x000b /* 16bit */
  24. #define VSE_CVP_STATUS 0x1c /* 32bit */
  25. #define VSE_CVP_STATUS_CFG_RDY BIT(18) /* CVP_CONFIG_READY */
  26. #define VSE_CVP_STATUS_CFG_ERR BIT(19) /* CVP_CONFIG_ERROR */
  27. #define VSE_CVP_STATUS_CVP_EN BIT(20) /* ctrl block is enabling CVP */
  28. #define VSE_CVP_STATUS_USERMODE BIT(21) /* USERMODE */
  29. #define VSE_CVP_STATUS_CFG_DONE BIT(23) /* CVP_CONFIG_DONE */
  30. #define VSE_CVP_STATUS_PLD_CLK_IN_USE BIT(24) /* PLD_CLK_IN_USE */
  31. #define VSE_CVP_MODE_CTRL 0x20 /* 32bit */
  32. #define VSE_CVP_MODE_CTRL_CVP_MODE BIT(0) /* CVP (1) or normal mode (0) */
  33. #define VSE_CVP_MODE_CTRL_HIP_CLK_SEL BIT(1) /* PMA (1) or fabric clock (0) */
  34. #define VSE_CVP_MODE_CTRL_NUMCLKS_OFF 8 /* NUMCLKS bits offset */
  35. #define VSE_CVP_MODE_CTRL_NUMCLKS_MASK GENMASK(15, 8)
  36. #define VSE_CVP_DATA 0x28 /* 32bit */
  37. #define VSE_CVP_PROG_CTRL 0x2c /* 32bit */
  38. #define VSE_CVP_PROG_CTRL_CONFIG BIT(0)
  39. #define VSE_CVP_PROG_CTRL_START_XFER BIT(1)
  40. #define VSE_CVP_PROG_CTRL_MASK GENMASK(1, 0)
  41. #define VSE_UNCOR_ERR_STATUS 0x34 /* 32bit */
  42. #define VSE_UNCOR_ERR_CVP_CFG_ERR BIT(5) /* CVP_CONFIG_ERROR_LATCHED */
  43. #define V1_VSEC_OFFSET 0x200 /* Vendor Specific Offset V1 */
  44. /* V2 Defines */
  45. #define VSE_CVP_TX_CREDITS 0x49 /* 8bit */
  46. #define V2_CREDIT_TIMEOUT_US 20000
  47. #define V2_CHECK_CREDIT_US 10
  48. #define V2_POLL_TIMEOUT_US 1000000
  49. #define V2_USER_TIMEOUT_US 500000
  50. #define V1_POLL_TIMEOUT_US 10
  51. #define DRV_NAME "altera-cvp"
  52. #define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager"
  53. /* Write block sizes */
  54. #define ALTERA_CVP_V1_SIZE 4
  55. #define ALTERA_CVP_V2_SIZE 4096
  56. /* Optional CvP config error status check for debugging */
  57. static bool altera_cvp_chkcfg;
  58. struct cvp_priv;
  59. struct altera_cvp_conf {
  60. struct fpga_manager *mgr;
  61. struct pci_dev *pci_dev;
  62. void __iomem *map;
  63. void (*write_data)(struct altera_cvp_conf *conf,
  64. u32 data);
  65. char mgr_name[64];
  66. u8 numclks;
  67. u32 sent_packets;
  68. u32 vsec_offset;
  69. const struct cvp_priv *priv;
  70. };
  71. struct cvp_priv {
  72. void (*switch_clk)(struct altera_cvp_conf *conf);
  73. int (*clear_state)(struct altera_cvp_conf *conf);
  74. int (*wait_credit)(struct fpga_manager *mgr, u32 blocks);
  75. size_t block_size;
  76. int poll_time_us;
  77. int user_time_us;
  78. };
  79. static int altera_read_config_byte(struct altera_cvp_conf *conf,
  80. int where, u8 *val)
  81. {
  82. return pci_read_config_byte(conf->pci_dev, conf->vsec_offset + where,
  83. val);
  84. }
  85. static int altera_read_config_dword(struct altera_cvp_conf *conf,
  86. int where, u32 *val)
  87. {
  88. return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where,
  89. val);
  90. }
  91. static int altera_write_config_dword(struct altera_cvp_conf *conf,
  92. int where, u32 val)
  93. {
  94. return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where,
  95. val);
  96. }
  97. static enum fpga_mgr_states altera_cvp_state(struct fpga_manager *mgr)
  98. {
  99. struct altera_cvp_conf *conf = mgr->priv;
  100. u32 status;
  101. altera_read_config_dword(conf, VSE_CVP_STATUS, &status);
  102. if (status & VSE_CVP_STATUS_CFG_DONE)
  103. return FPGA_MGR_STATE_OPERATING;
  104. if (status & VSE_CVP_STATUS_CVP_EN)
  105. return FPGA_MGR_STATE_POWER_UP;
  106. return FPGA_MGR_STATE_UNKNOWN;
  107. }
  108. static void altera_cvp_write_data_iomem(struct altera_cvp_conf *conf, u32 val)
  109. {
  110. writel(val, conf->map);
  111. }
  112. static void altera_cvp_write_data_config(struct altera_cvp_conf *conf, u32 val)
  113. {
  114. pci_write_config_dword(conf->pci_dev, conf->vsec_offset + VSE_CVP_DATA,
  115. val);
  116. }
  117. /* switches between CvP clock and internal clock */
  118. static void altera_cvp_dummy_write(struct altera_cvp_conf *conf)
  119. {
  120. unsigned int i;
  121. u32 val;
  122. /* set 1 CVP clock cycle for every CVP Data Register Write */
  123. altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
  124. val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
  125. val |= 1 << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
  126. altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
  127. for (i = 0; i < CVP_DUMMY_WR; i++)
  128. conf->write_data(conf, 0); /* dummy data, could be any value */
  129. }
  130. static int altera_cvp_wait_status(struct altera_cvp_conf *conf, u32 status_mask,
  131. u32 status_val, int timeout_us)
  132. {
  133. unsigned int retries;
  134. u32 val;
  135. retries = timeout_us / 10;
  136. if (timeout_us % 10)
  137. retries++;
  138. do {
  139. altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
  140. if ((val & status_mask) == status_val)
  141. return 0;
  142. /* use small usleep value to re-check and break early */
  143. usleep_range(10, 11);
  144. } while (--retries);
  145. return -ETIMEDOUT;
  146. }
  147. static int altera_cvp_chk_error(struct fpga_manager *mgr, size_t bytes)
  148. {
  149. struct altera_cvp_conf *conf = mgr->priv;
  150. u32 val;
  151. int ret;
  152. /* STEP 10 (optional) - check CVP_CONFIG_ERROR flag */
  153. ret = altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
  154. if (ret || (val & VSE_CVP_STATUS_CFG_ERR)) {
  155. dev_err(&mgr->dev, "CVP_CONFIG_ERROR after %zu bytes!\n",
  156. bytes);
  157. return -EPROTO;
  158. }
  159. return 0;
  160. }
  161. /*
  162. * CvP Version2 Functions
  163. * Recent Intel FPGAs use a credit mechanism to throttle incoming
  164. * bitstreams and a different method of clearing the state.
  165. */
  166. static int altera_cvp_v2_clear_state(struct altera_cvp_conf *conf)
  167. {
  168. u32 val;
  169. int ret;
  170. /* Clear the START_XFER and CVP_CONFIG bits */
  171. ret = altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
  172. if (ret) {
  173. dev_err(&conf->pci_dev->dev,
  174. "Error reading CVP Program Control Register\n");
  175. return ret;
  176. }
  177. val &= ~VSE_CVP_PROG_CTRL_MASK;
  178. ret = altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
  179. if (ret) {
  180. dev_err(&conf->pci_dev->dev,
  181. "Error writing CVP Program Control Register\n");
  182. return ret;
  183. }
  184. return altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
  185. conf->priv->poll_time_us);
  186. }
  187. static int altera_cvp_v2_wait_for_credit(struct fpga_manager *mgr,
  188. u32 blocks)
  189. {
  190. u32 timeout = V2_CREDIT_TIMEOUT_US / V2_CHECK_CREDIT_US;
  191. struct altera_cvp_conf *conf = mgr->priv;
  192. int ret;
  193. u8 val;
  194. do {
  195. ret = altera_read_config_byte(conf, VSE_CVP_TX_CREDITS, &val);
  196. if (ret) {
  197. dev_err(&conf->pci_dev->dev,
  198. "Error reading CVP Credit Register\n");
  199. return ret;
  200. }
  201. /* Return if there is space in FIFO */
  202. if (val - (u8)conf->sent_packets)
  203. return 0;
  204. ret = altera_cvp_chk_error(mgr, blocks * ALTERA_CVP_V2_SIZE);
  205. if (ret) {
  206. dev_err(&conf->pci_dev->dev,
  207. "CE Bit error credit reg[0x%x]:sent[0x%x]\n",
  208. val, conf->sent_packets);
  209. return -EAGAIN;
  210. }
  211. /* Limit the check credit byte traffic */
  212. usleep_range(V2_CHECK_CREDIT_US, V2_CHECK_CREDIT_US + 1);
  213. } while (timeout--);
  214. dev_err(&conf->pci_dev->dev, "Timeout waiting for credit\n");
  215. return -ETIMEDOUT;
  216. }
  217. static int altera_cvp_send_block(struct altera_cvp_conf *conf,
  218. const u32 *data, size_t len)
  219. {
  220. u32 mask, words = len / sizeof(u32);
  221. int i, remainder;
  222. for (i = 0; i < words; i++)
  223. conf->write_data(conf, *data++);
  224. /* write up to 3 trailing bytes, if any */
  225. remainder = len % sizeof(u32);
  226. if (remainder) {
  227. mask = BIT(remainder * 8) - 1;
  228. if (mask)
  229. conf->write_data(conf, *data & mask);
  230. }
  231. return 0;
  232. }
  233. static int altera_cvp_teardown(struct fpga_manager *mgr,
  234. struct fpga_image_info *info)
  235. {
  236. struct altera_cvp_conf *conf = mgr->priv;
  237. int ret;
  238. u32 val;
  239. /* STEP 12 - reset START_XFER bit */
  240. altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
  241. val &= ~VSE_CVP_PROG_CTRL_START_XFER;
  242. altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
  243. /* STEP 13 - reset CVP_CONFIG bit */
  244. val &= ~VSE_CVP_PROG_CTRL_CONFIG;
  245. altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
  246. /*
  247. * STEP 14
  248. * - set CVP_NUMCLKS to 1 and then issue CVP_DUMMY_WR dummy
  249. * writes to the HIP
  250. */
  251. if (conf->priv->switch_clk)
  252. conf->priv->switch_clk(conf);
  253. /* STEP 15 - poll CVP_CONFIG_READY bit for 0 with 10us timeout */
  254. ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY, 0,
  255. conf->priv->poll_time_us);
  256. if (ret)
  257. dev_err(&mgr->dev, "CFG_RDY == 0 timeout\n");
  258. return ret;
  259. }
  260. static int altera_cvp_write_init(struct fpga_manager *mgr,
  261. struct fpga_image_info *info,
  262. const char *buf, size_t count)
  263. {
  264. struct altera_cvp_conf *conf = mgr->priv;
  265. u32 iflags, val;
  266. int ret;
  267. iflags = info ? info->flags : 0;
  268. if (iflags & FPGA_MGR_PARTIAL_RECONFIG) {
  269. dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
  270. return -EINVAL;
  271. }
  272. /* Determine allowed clock to data ratio */
  273. if (iflags & FPGA_MGR_COMPRESSED_BITSTREAM)
  274. conf->numclks = 8; /* ratio for all compressed images */
  275. else if (iflags & FPGA_MGR_ENCRYPTED_BITSTREAM)
  276. conf->numclks = 4; /* for uncompressed and encrypted images */
  277. else
  278. conf->numclks = 1; /* for uncompressed and unencrypted images */
  279. /* STEP 1 - read CVP status and check CVP_EN flag */
  280. altera_read_config_dword(conf, VSE_CVP_STATUS, &val);
  281. if (!(val & VSE_CVP_STATUS_CVP_EN)) {
  282. dev_err(&mgr->dev, "CVP mode off: 0x%04x\n", val);
  283. return -ENODEV;
  284. }
  285. if (val & VSE_CVP_STATUS_CFG_RDY) {
  286. dev_warn(&mgr->dev, "CvP already started, teardown first\n");
  287. ret = altera_cvp_teardown(mgr, info);
  288. if (ret)
  289. return ret;
  290. }
  291. /*
  292. * STEP 2
  293. * - set HIP_CLK_SEL and CVP_MODE (must be set in the order mentioned)
  294. */
  295. /* switch from fabric to PMA clock */
  296. altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
  297. val |= VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
  298. altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
  299. /* set CVP mode */
  300. altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
  301. val |= VSE_CVP_MODE_CTRL_CVP_MODE;
  302. altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
  303. /*
  304. * STEP 3
  305. * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
  306. */
  307. if (conf->priv->switch_clk)
  308. conf->priv->switch_clk(conf);
  309. if (conf->priv->clear_state) {
  310. ret = conf->priv->clear_state(conf);
  311. if (ret) {
  312. dev_err(&mgr->dev, "Problem clearing out state\n");
  313. return ret;
  314. }
  315. }
  316. conf->sent_packets = 0;
  317. /* STEP 4 - set CVP_CONFIG bit */
  318. altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
  319. /* request control block to begin transfer using CVP */
  320. val |= VSE_CVP_PROG_CTRL_CONFIG;
  321. altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
  322. /* STEP 5 - poll CVP_CONFIG READY for 1 with timeout */
  323. ret = altera_cvp_wait_status(conf, VSE_CVP_STATUS_CFG_RDY,
  324. VSE_CVP_STATUS_CFG_RDY,
  325. conf->priv->poll_time_us);
  326. if (ret) {
  327. dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
  328. return ret;
  329. }
  330. /*
  331. * STEP 6
  332. * - set CVP_NUMCLKS to 1 and issue CVP_DUMMY_WR dummy writes to the HIP
  333. */
  334. if (conf->priv->switch_clk)
  335. conf->priv->switch_clk(conf);
  336. if (altera_cvp_chkcfg) {
  337. ret = altera_cvp_chk_error(mgr, 0);
  338. if (ret) {
  339. dev_warn(&mgr->dev, "CFG_RDY == 1 timeout\n");
  340. return ret;
  341. }
  342. }
  343. /* STEP 7 - set START_XFER */
  344. altera_read_config_dword(conf, VSE_CVP_PROG_CTRL, &val);
  345. val |= VSE_CVP_PROG_CTRL_START_XFER;
  346. altera_write_config_dword(conf, VSE_CVP_PROG_CTRL, val);
  347. /* STEP 8 - start transfer (set CVP_NUMCLKS for bitstream) */
  348. if (conf->priv->switch_clk) {
  349. altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
  350. val &= ~VSE_CVP_MODE_CTRL_NUMCLKS_MASK;
  351. val |= conf->numclks << VSE_CVP_MODE_CTRL_NUMCLKS_OFF;
  352. altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
  353. }
  354. return 0;
  355. }
  356. static int altera_cvp_write(struct fpga_manager *mgr, const char *buf,
  357. size_t count)
  358. {
  359. struct altera_cvp_conf *conf = mgr->priv;
  360. size_t done, remaining, len;
  361. const u32 *data;
  362. int status = 0;
  363. /* STEP 9 - write 32-bit data from RBF file to CVP data register */
  364. data = (u32 *)buf;
  365. remaining = count;
  366. done = 0;
  367. while (remaining) {
  368. /* Use credit throttling if available */
  369. if (conf->priv->wait_credit) {
  370. status = conf->priv->wait_credit(mgr, done);
  371. if (status) {
  372. dev_err(&conf->pci_dev->dev,
  373. "Wait Credit ERR: 0x%x\n", status);
  374. return status;
  375. }
  376. }
  377. len = min(conf->priv->block_size, remaining);
  378. altera_cvp_send_block(conf, data, len);
  379. data += len / sizeof(u32);
  380. done += len;
  381. remaining -= len;
  382. conf->sent_packets++;
  383. /*
  384. * STEP 10 (optional) and STEP 11
  385. * - check error flag
  386. * - loop until data transfer completed
  387. * Config images can be huge (more than 40 MiB), so
  388. * only check after a new 4k data block has been written.
  389. * This reduces the number of checks and speeds up the
  390. * configuration process.
  391. */
  392. if (altera_cvp_chkcfg && !(done % SZ_4K)) {
  393. status = altera_cvp_chk_error(mgr, done);
  394. if (status < 0)
  395. return status;
  396. }
  397. }
  398. if (altera_cvp_chkcfg)
  399. status = altera_cvp_chk_error(mgr, count);
  400. return status;
  401. }
  402. static int altera_cvp_write_complete(struct fpga_manager *mgr,
  403. struct fpga_image_info *info)
  404. {
  405. struct altera_cvp_conf *conf = mgr->priv;
  406. u32 mask, val;
  407. int ret;
  408. ret = altera_cvp_teardown(mgr, info);
  409. if (ret)
  410. return ret;
  411. /* STEP 16 - check CVP_CONFIG_ERROR_LATCHED bit */
  412. altera_read_config_dword(conf, VSE_UNCOR_ERR_STATUS, &val);
  413. if (val & VSE_UNCOR_ERR_CVP_CFG_ERR) {
  414. dev_err(&mgr->dev, "detected CVP_CONFIG_ERROR_LATCHED!\n");
  415. return -EPROTO;
  416. }
  417. /* STEP 17 - reset CVP_MODE and HIP_CLK_SEL bit */
  418. altera_read_config_dword(conf, VSE_CVP_MODE_CTRL, &val);
  419. val &= ~VSE_CVP_MODE_CTRL_HIP_CLK_SEL;
  420. val &= ~VSE_CVP_MODE_CTRL_CVP_MODE;
  421. altera_write_config_dword(conf, VSE_CVP_MODE_CTRL, val);
  422. /* STEP 18 - poll PLD_CLK_IN_USE and USER_MODE bits */
  423. mask = VSE_CVP_STATUS_PLD_CLK_IN_USE | VSE_CVP_STATUS_USERMODE;
  424. ret = altera_cvp_wait_status(conf, mask, mask,
  425. conf->priv->user_time_us);
  426. if (ret)
  427. dev_err(&mgr->dev, "PLD_CLK_IN_USE|USERMODE timeout\n");
  428. return ret;
  429. }
  430. static const struct fpga_manager_ops altera_cvp_ops = {
  431. .state = altera_cvp_state,
  432. .write_init = altera_cvp_write_init,
  433. .write = altera_cvp_write,
  434. .write_complete = altera_cvp_write_complete,
  435. };
  436. static const struct cvp_priv cvp_priv_v1 = {
  437. .switch_clk = altera_cvp_dummy_write,
  438. .block_size = ALTERA_CVP_V1_SIZE,
  439. .poll_time_us = V1_POLL_TIMEOUT_US,
  440. .user_time_us = TIMEOUT_US,
  441. };
  442. static const struct cvp_priv cvp_priv_v2 = {
  443. .clear_state = altera_cvp_v2_clear_state,
  444. .wait_credit = altera_cvp_v2_wait_for_credit,
  445. .block_size = ALTERA_CVP_V2_SIZE,
  446. .poll_time_us = V2_POLL_TIMEOUT_US,
  447. .user_time_us = V2_USER_TIMEOUT_US,
  448. };
  449. static ssize_t chkcfg_show(struct device_driver *dev, char *buf)
  450. {
  451. return snprintf(buf, 3, "%d\n", altera_cvp_chkcfg);
  452. }
  453. static ssize_t chkcfg_store(struct device_driver *drv, const char *buf,
  454. size_t count)
  455. {
  456. int ret;
  457. ret = kstrtobool(buf, &altera_cvp_chkcfg);
  458. if (ret)
  459. return ret;
  460. return count;
  461. }
  462. static DRIVER_ATTR_RW(chkcfg);
  463. static int altera_cvp_probe(struct pci_dev *pdev,
  464. const struct pci_device_id *dev_id);
  465. static void altera_cvp_remove(struct pci_dev *pdev);
  466. static struct pci_device_id altera_cvp_id_tbl[] = {
  467. { PCI_VDEVICE(ALTERA, PCI_ANY_ID) },
  468. { }
  469. };
  470. MODULE_DEVICE_TABLE(pci, altera_cvp_id_tbl);
  471. static struct pci_driver altera_cvp_driver = {
  472. .name = DRV_NAME,
  473. .id_table = altera_cvp_id_tbl,
  474. .probe = altera_cvp_probe,
  475. .remove = altera_cvp_remove,
  476. };
  477. static int altera_cvp_probe(struct pci_dev *pdev,
  478. const struct pci_device_id *dev_id)
  479. {
  480. struct altera_cvp_conf *conf;
  481. struct fpga_manager *mgr;
  482. int ret, offset;
  483. u16 cmd, val;
  484. u32 regval;
  485. /* Discover the Vendor Specific Offset for this device */
  486. offset = pci_find_next_ext_capability(pdev, 0, PCI_EXT_CAP_ID_VNDR);
  487. if (!offset) {
  488. dev_err(&pdev->dev, "No Vendor Specific Offset.\n");
  489. return -ENODEV;
  490. }
  491. /*
  492. * First check if this is the expected FPGA device. PCI config
  493. * space access works without enabling the PCI device, memory
  494. * space access is enabled further down.
  495. */
  496. pci_read_config_word(pdev, offset + VSE_PCIE_EXT_CAP_ID, &val);
  497. if (val != VSE_PCIE_EXT_CAP_ID_VAL) {
  498. dev_err(&pdev->dev, "Wrong EXT_CAP_ID value 0x%x\n", val);
  499. return -ENODEV;
  500. }
  501. pci_read_config_dword(pdev, offset + VSE_CVP_STATUS, &regval);
  502. if (!(regval & VSE_CVP_STATUS_CVP_EN)) {
  503. dev_err(&pdev->dev,
  504. "CVP is disabled for this device: CVP_STATUS Reg 0x%x\n",
  505. regval);
  506. return -ENODEV;
  507. }
  508. conf = devm_kzalloc(&pdev->dev, sizeof(*conf), GFP_KERNEL);
  509. if (!conf)
  510. return -ENOMEM;
  511. conf->vsec_offset = offset;
  512. /*
  513. * Enable memory BAR access. We cannot use pci_enable_device() here
  514. * because it will make the driver unusable with FPGA devices that
  515. * have additional big IOMEM resources (e.g. 4GiB BARs) on 32-bit
  516. * platform. Such BARs will not have an assigned address range and
  517. * pci_enable_device() will fail, complaining about not claimed BAR,
  518. * even if the concerned BAR is not needed for FPGA configuration
  519. * at all. Thus, enable the device via PCI config space command.
  520. */
  521. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  522. if (!(cmd & PCI_COMMAND_MEMORY)) {
  523. cmd |= PCI_COMMAND_MEMORY;
  524. pci_write_config_word(pdev, PCI_COMMAND, cmd);
  525. }
  526. ret = pci_request_region(pdev, CVP_BAR, "CVP");
  527. if (ret) {
  528. dev_err(&pdev->dev, "Requesting CVP BAR region failed\n");
  529. goto err_disable;
  530. }
  531. conf->pci_dev = pdev;
  532. conf->write_data = altera_cvp_write_data_iomem;
  533. if (conf->vsec_offset == V1_VSEC_OFFSET)
  534. conf->priv = &cvp_priv_v1;
  535. else
  536. conf->priv = &cvp_priv_v2;
  537. conf->map = pci_iomap(pdev, CVP_BAR, 0);
  538. if (!conf->map) {
  539. dev_warn(&pdev->dev, "Mapping CVP BAR failed\n");
  540. conf->write_data = altera_cvp_write_data_config;
  541. }
  542. snprintf(conf->mgr_name, sizeof(conf->mgr_name), "%s @%s",
  543. ALTERA_CVP_MGR_NAME, pci_name(pdev));
  544. mgr = devm_fpga_mgr_create(&pdev->dev, conf->mgr_name,
  545. &altera_cvp_ops, conf);
  546. if (!mgr) {
  547. ret = -ENOMEM;
  548. goto err_unmap;
  549. }
  550. pci_set_drvdata(pdev, mgr);
  551. ret = fpga_mgr_register(mgr);
  552. if (ret)
  553. goto err_unmap;
  554. return 0;
  555. err_unmap:
  556. if (conf->map)
  557. pci_iounmap(pdev, conf->map);
  558. pci_release_region(pdev, CVP_BAR);
  559. err_disable:
  560. cmd &= ~PCI_COMMAND_MEMORY;
  561. pci_write_config_word(pdev, PCI_COMMAND, cmd);
  562. return ret;
  563. }
  564. static void altera_cvp_remove(struct pci_dev *pdev)
  565. {
  566. struct fpga_manager *mgr = pci_get_drvdata(pdev);
  567. struct altera_cvp_conf *conf = mgr->priv;
  568. u16 cmd;
  569. fpga_mgr_unregister(mgr);
  570. if (conf->map)
  571. pci_iounmap(pdev, conf->map);
  572. pci_release_region(pdev, CVP_BAR);
  573. pci_read_config_word(pdev, PCI_COMMAND, &cmd);
  574. cmd &= ~PCI_COMMAND_MEMORY;
  575. pci_write_config_word(pdev, PCI_COMMAND, cmd);
  576. }
  577. static int __init altera_cvp_init(void)
  578. {
  579. int ret;
  580. ret = pci_register_driver(&altera_cvp_driver);
  581. if (ret)
  582. return ret;
  583. ret = driver_create_file(&altera_cvp_driver.driver,
  584. &driver_attr_chkcfg);
  585. if (ret)
  586. pr_warn("Can't create sysfs chkcfg file\n");
  587. return 0;
  588. }
  589. static void __exit altera_cvp_exit(void)
  590. {
  591. driver_remove_file(&altera_cvp_driver.driver, &driver_attr_chkcfg);
  592. pci_unregister_driver(&altera_cvp_driver);
  593. }
  594. module_init(altera_cvp_init);
  595. module_exit(altera_cvp_exit);
  596. MODULE_LICENSE("GPL v2");
  597. MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
  598. MODULE_DESCRIPTION("Module to load Altera FPGA over CvP");