Kconfig 6.9 KB

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  1. # SPDX-License-Identifier: GPL-2.0-only
  2. #
  3. # FPGA framework configuration
  4. #
  5. menuconfig FPGA
  6. tristate "FPGA Configuration Framework"
  7. help
  8. Say Y here if you want support for configuring FPGAs from the
  9. kernel. The FPGA framework adds a FPGA manager class and FPGA
  10. manager drivers.
  11. if FPGA
  12. config FPGA_MGR_SOCFPGA
  13. tristate "Altera SOCFPGA FPGA Manager"
  14. depends on ARCH_SOCFPGA || COMPILE_TEST
  15. help
  16. FPGA manager driver support for Altera SOCFPGA.
  17. config FPGA_MGR_SOCFPGA_A10
  18. tristate "Altera SoCFPGA Arria10"
  19. depends on ARCH_SOCFPGA || COMPILE_TEST
  20. select REGMAP_MMIO
  21. help
  22. FPGA manager driver support for Altera Arria10 SoCFPGA.
  23. config ALTERA_PR_IP_CORE
  24. tristate "Altera Partial Reconfiguration IP Core"
  25. help
  26. Core driver support for Altera Partial Reconfiguration IP component
  27. config ALTERA_PR_IP_CORE_PLAT
  28. tristate "Platform support of Altera Partial Reconfiguration IP Core"
  29. depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM
  30. help
  31. Platform driver support for Altera Partial Reconfiguration IP
  32. component
  33. config FPGA_MGR_ALTERA_PS_SPI
  34. tristate "Altera FPGA Passive Serial over SPI"
  35. depends on SPI
  36. select BITREVERSE
  37. help
  38. FPGA manager driver support for Altera Arria/Cyclone/Stratix
  39. using the passive serial interface over SPI.
  40. config FPGA_MGR_ALTERA_CVP
  41. tristate "Altera CvP FPGA Manager"
  42. depends on PCI
  43. help
  44. FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V,
  45. Arria 10 and Stratix10 Altera FPGAs using the CvP interface over PCIe.
  46. config FPGA_MGR_ZYNQ_FPGA
  47. tristate "Xilinx Zynq FPGA"
  48. depends on ARCH_ZYNQ || COMPILE_TEST
  49. help
  50. FPGA manager driver support for Xilinx Zynq FPGAs.
  51. config FPGA_MGR_STRATIX10_SOC
  52. tristate "Intel Stratix10 SoC FPGA Manager"
  53. depends on (ARCH_STRATIX10 && INTEL_STRATIX10_SERVICE)
  54. help
  55. FPGA manager driver support for the Intel Stratix10 SoC.
  56. config FPGA_MGR_XILINX_SPI
  57. tristate "Xilinx Configuration over Slave Serial (SPI)"
  58. depends on SPI
  59. help
  60. FPGA manager driver support for Xilinx FPGA configuration
  61. over slave serial interface.
  62. config FPGA_MGR_ICE40_SPI
  63. tristate "Lattice iCE40 SPI"
  64. depends on OF && SPI
  65. help
  66. FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
  67. config FPGA_MGR_MACHXO2_SPI
  68. tristate "Lattice MachXO2 SPI"
  69. depends on SPI
  70. help
  71. FPGA manager driver support for Lattice MachXO2 configuration
  72. over slave SPI interface.
  73. config FPGA_MGR_TS73XX
  74. tristate "Technologic Systems TS-73xx SBC FPGA Manager"
  75. depends on ARCH_EP93XX && MACH_TS72XX
  76. help
  77. FPGA manager driver support for the Altera Cyclone II FPGA
  78. present on the TS-73xx SBC boards.
  79. config FPGA_BRIDGE
  80. tristate "FPGA Bridge Framework"
  81. help
  82. Say Y here if you want to support bridges connected between host
  83. processors and FPGAs or between FPGAs.
  84. config SOCFPGA_FPGA_BRIDGE
  85. tristate "Altera SoCFPGA FPGA Bridges"
  86. depends on ARCH_SOCFPGA && FPGA_BRIDGE
  87. help
  88. Say Y to enable drivers for FPGA bridges for Altera SOCFPGA
  89. devices.
  90. config ALTERA_FREEZE_BRIDGE
  91. tristate "Altera FPGA Freeze Bridge"
  92. depends on FPGA_BRIDGE && HAS_IOMEM
  93. help
  94. Say Y to enable drivers for Altera FPGA Freeze bridges. A
  95. freeze bridge is a bridge that exists in the FPGA fabric to
  96. isolate one region of the FPGA from the busses while that
  97. region is being reprogrammed.
  98. config XILINX_PR_DECOUPLER
  99. tristate "Xilinx LogiCORE PR Decoupler"
  100. depends on FPGA_BRIDGE
  101. depends on HAS_IOMEM
  102. help
  103. Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
  104. The PR Decoupler exists in the FPGA fabric to isolate one
  105. region of the FPGA from the busses while that region is
  106. being reprogrammed during partial reconfig.
  107. config FPGA_REGION
  108. tristate "FPGA Region"
  109. depends on FPGA_BRIDGE
  110. help
  111. FPGA Region common code. A FPGA Region controls a FPGA Manager
  112. and the FPGA Bridges associated with either a reconfigurable
  113. region of an FPGA or a whole FPGA.
  114. config OF_FPGA_REGION
  115. tristate "FPGA Region Device Tree Overlay Support"
  116. depends on OF && FPGA_REGION
  117. help
  118. Support for loading FPGA images by applying a Device Tree
  119. overlay.
  120. config FPGA_DFL
  121. tristate "FPGA Device Feature List (DFL) support"
  122. select FPGA_BRIDGE
  123. select FPGA_REGION
  124. depends on HAS_IOMEM
  125. help
  126. Device Feature List (DFL) defines a feature list structure that
  127. creates a linked list of feature headers within the MMIO space
  128. to provide an extensible way of adding features for FPGA.
  129. Driver can walk through the feature headers to enumerate feature
  130. devices (e.g. FPGA Management Engine, Port and Accelerator
  131. Function Unit) and their private features for target FPGA devices.
  132. Select this option to enable common support for Field-Programmable
  133. Gate Array (FPGA) solutions which implement Device Feature List.
  134. It provides enumeration APIs and feature device infrastructure.
  135. config FPGA_DFL_FME
  136. tristate "FPGA DFL FME Driver"
  137. depends on FPGA_DFL && HWMON && PERF_EVENTS
  138. help
  139. The FPGA Management Engine (FME) is a feature device implemented
  140. under Device Feature List (DFL) framework. Select this option to
  141. enable the platform device driver for FME which implements all
  142. FPGA platform level management features. There shall be one FME
  143. per DFL based FPGA device.
  144. config FPGA_DFL_FME_MGR
  145. tristate "FPGA DFL FME Manager Driver"
  146. depends on FPGA_DFL_FME && HAS_IOMEM
  147. help
  148. Say Y to enable FPGA Manager driver for FPGA Management Engine.
  149. config FPGA_DFL_FME_BRIDGE
  150. tristate "FPGA DFL FME Bridge Driver"
  151. depends on FPGA_DFL_FME && HAS_IOMEM
  152. help
  153. Say Y to enable FPGA Bridge driver for FPGA Management Engine.
  154. config FPGA_DFL_FME_REGION
  155. tristate "FPGA DFL FME Region Driver"
  156. depends on FPGA_DFL_FME && HAS_IOMEM
  157. help
  158. Say Y to enable FPGA Region driver for FPGA Management Engine.
  159. config FPGA_DFL_AFU
  160. tristate "FPGA DFL AFU Driver"
  161. depends on FPGA_DFL
  162. help
  163. This is the driver for FPGA Accelerated Function Unit (AFU) which
  164. implements AFU and Port management features. A User AFU connects
  165. to the FPGA infrastructure via a Port. There may be more than one
  166. Port/AFU per DFL based FPGA device.
  167. config FPGA_DFL_PCI
  168. tristate "FPGA DFL PCIe Device Driver"
  169. depends on PCI && FPGA_DFL
  170. help
  171. Select this option to enable PCIe driver for PCIe-based
  172. Field-Programmable Gate Array (FPGA) solutions which implement
  173. the Device Feature List (DFL). This driver provides interfaces
  174. for userspace applications to configure, enumerate, open and access
  175. FPGA accelerators on the FPGA DFL devices, enables system level
  176. management functions such as FPGA partial reconfiguration, power
  177. management and virtualization with DFL framework and DFL feature
  178. device drivers.
  179. To compile this as a module, choose M here.
  180. config FPGA_MGR_ZYNQMP_FPGA
  181. tristate "Xilinx ZynqMP FPGA"
  182. depends on ZYNQMP_FIRMWARE || (!ZYNQMP_FIRMWARE && COMPILE_TEST)
  183. help
  184. FPGA manager driver support for Xilinx ZynqMP FPGAs.
  185. This driver uses the processor configuration port(PCAP)
  186. to configure the programmable logic(PL) through PS
  187. on ZynqMP SoC.
  188. endif # FPGA