ohci.c 105 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for OHCI 1394 controllers
  4. *
  5. * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/bug.h>
  9. #include <linux/compiler.h>
  10. #include <linux/delay.h>
  11. #include <linux/device.h>
  12. #include <linux/dma-mapping.h>
  13. #include <linux/firewire.h>
  14. #include <linux/firewire-constants.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/kernel.h>
  19. #include <linux/list.h>
  20. #include <linux/mm.h>
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/mutex.h>
  24. #include <linux/pci.h>
  25. #include <linux/pci_ids.h>
  26. #include <linux/slab.h>
  27. #include <linux/spinlock.h>
  28. #include <linux/string.h>
  29. #include <linux/time.h>
  30. #include <linux/vmalloc.h>
  31. #include <linux/workqueue.h>
  32. #include <asm/byteorder.h>
  33. #include <asm/page.h>
  34. #ifdef CONFIG_PPC_PMAC
  35. #include <asm/pmac_feature.h>
  36. #endif
  37. #include "core.h"
  38. #include "ohci.h"
  39. #define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
  40. #define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
  41. #define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
  42. #define DESCRIPTOR_OUTPUT_MORE 0
  43. #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
  44. #define DESCRIPTOR_INPUT_MORE (2 << 12)
  45. #define DESCRIPTOR_INPUT_LAST (3 << 12)
  46. #define DESCRIPTOR_STATUS (1 << 11)
  47. #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
  48. #define DESCRIPTOR_PING (1 << 7)
  49. #define DESCRIPTOR_YY (1 << 6)
  50. #define DESCRIPTOR_NO_IRQ (0 << 4)
  51. #define DESCRIPTOR_IRQ_ERROR (1 << 4)
  52. #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
  53. #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
  54. #define DESCRIPTOR_WAIT (3 << 0)
  55. #define DESCRIPTOR_CMD (0xf << 12)
  56. struct descriptor {
  57. __le16 req_count;
  58. __le16 control;
  59. __le32 data_address;
  60. __le32 branch_address;
  61. __le16 res_count;
  62. __le16 transfer_status;
  63. } __attribute__((aligned(16)));
  64. #define CONTROL_SET(regs) (regs)
  65. #define CONTROL_CLEAR(regs) ((regs) + 4)
  66. #define COMMAND_PTR(regs) ((regs) + 12)
  67. #define CONTEXT_MATCH(regs) ((regs) + 16)
  68. #define AR_BUFFER_SIZE (32*1024)
  69. #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  70. /* we need at least two pages for proper list management */
  71. #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  72. #define MAX_ASYNC_PAYLOAD 4096
  73. #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
  74. #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  75. struct ar_context {
  76. struct fw_ohci *ohci;
  77. struct page *pages[AR_BUFFERS];
  78. void *buffer;
  79. struct descriptor *descriptors;
  80. dma_addr_t descriptors_bus;
  81. void *pointer;
  82. unsigned int last_buffer_index;
  83. u32 regs;
  84. struct tasklet_struct tasklet;
  85. };
  86. struct context;
  87. typedef int (*descriptor_callback_t)(struct context *ctx,
  88. struct descriptor *d,
  89. struct descriptor *last);
  90. /*
  91. * A buffer that contains a block of DMA-able coherent memory used for
  92. * storing a portion of a DMA descriptor program.
  93. */
  94. struct descriptor_buffer {
  95. struct list_head list;
  96. dma_addr_t buffer_bus;
  97. size_t buffer_size;
  98. size_t used;
  99. struct descriptor buffer[];
  100. };
  101. struct context {
  102. struct fw_ohci *ohci;
  103. u32 regs;
  104. int total_allocation;
  105. u32 current_bus;
  106. bool running;
  107. bool flushing;
  108. /*
  109. * List of page-sized buffers for storing DMA descriptors.
  110. * Head of list contains buffers in use and tail of list contains
  111. * free buffers.
  112. */
  113. struct list_head buffer_list;
  114. /*
  115. * Pointer to a buffer inside buffer_list that contains the tail
  116. * end of the current DMA program.
  117. */
  118. struct descriptor_buffer *buffer_tail;
  119. /*
  120. * The descriptor containing the branch address of the first
  121. * descriptor that has not yet been filled by the device.
  122. */
  123. struct descriptor *last;
  124. /*
  125. * The last descriptor block in the DMA program. It contains the branch
  126. * address that must be updated upon appending a new descriptor.
  127. */
  128. struct descriptor *prev;
  129. int prev_z;
  130. descriptor_callback_t callback;
  131. struct tasklet_struct tasklet;
  132. };
  133. #define IT_HEADER_SY(v) ((v) << 0)
  134. #define IT_HEADER_TCODE(v) ((v) << 4)
  135. #define IT_HEADER_CHANNEL(v) ((v) << 8)
  136. #define IT_HEADER_TAG(v) ((v) << 14)
  137. #define IT_HEADER_SPEED(v) ((v) << 16)
  138. #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
  139. struct iso_context {
  140. struct fw_iso_context base;
  141. struct context context;
  142. void *header;
  143. size_t header_length;
  144. unsigned long flushing_completions;
  145. u32 mc_buffer_bus;
  146. u16 mc_completed;
  147. u16 last_timestamp;
  148. u8 sync;
  149. u8 tags;
  150. };
  151. #define CONFIG_ROM_SIZE 1024
  152. struct fw_ohci {
  153. struct fw_card card;
  154. __iomem char *registers;
  155. int node_id;
  156. int generation;
  157. int request_generation; /* for timestamping incoming requests */
  158. unsigned quirks;
  159. unsigned int pri_req_max;
  160. u32 bus_time;
  161. bool bus_time_running;
  162. bool is_root;
  163. bool csr_state_setclear_abdicate;
  164. int n_ir;
  165. int n_it;
  166. /*
  167. * Spinlock for accessing fw_ohci data. Never call out of
  168. * this driver with this lock held.
  169. */
  170. spinlock_t lock;
  171. struct mutex phy_reg_mutex;
  172. void *misc_buffer;
  173. dma_addr_t misc_buffer_bus;
  174. struct ar_context ar_request_ctx;
  175. struct ar_context ar_response_ctx;
  176. struct context at_request_ctx;
  177. struct context at_response_ctx;
  178. u32 it_context_support;
  179. u32 it_context_mask; /* unoccupied IT contexts */
  180. struct iso_context *it_context_list;
  181. u64 ir_context_channels; /* unoccupied channels */
  182. u32 ir_context_support;
  183. u32 ir_context_mask; /* unoccupied IR contexts */
  184. struct iso_context *ir_context_list;
  185. u64 mc_channels; /* channels in use by the multichannel IR context */
  186. bool mc_allocated;
  187. __be32 *config_rom;
  188. dma_addr_t config_rom_bus;
  189. __be32 *next_config_rom;
  190. dma_addr_t next_config_rom_bus;
  191. __be32 next_header;
  192. __le32 *self_id;
  193. dma_addr_t self_id_bus;
  194. struct work_struct bus_reset_work;
  195. u32 self_id_buffer[512];
  196. };
  197. static struct workqueue_struct *selfid_workqueue;
  198. static inline struct fw_ohci *fw_ohci(struct fw_card *card)
  199. {
  200. return container_of(card, struct fw_ohci, card);
  201. }
  202. #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
  203. #define IR_CONTEXT_BUFFER_FILL 0x80000000
  204. #define IR_CONTEXT_ISOCH_HEADER 0x40000000
  205. #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
  206. #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
  207. #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
  208. #define CONTEXT_RUN 0x8000
  209. #define CONTEXT_WAKE 0x1000
  210. #define CONTEXT_DEAD 0x0800
  211. #define CONTEXT_ACTIVE 0x0400
  212. #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
  213. #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
  214. #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
  215. #define OHCI1394_REGISTER_SIZE 0x800
  216. #define OHCI1394_PCI_HCI_Control 0x40
  217. #define SELF_ID_BUF_SIZE 0x800
  218. #define OHCI_TCODE_PHY_PACKET 0x0e
  219. #define OHCI_VERSION_1_1 0x010010
  220. static char ohci_driver_name[] = KBUILD_MODNAME;
  221. #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
  222. #define PCI_DEVICE_ID_AGERE_FW643 0x5901
  223. #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
  224. #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
  225. #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
  226. #define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
  227. #define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
  228. #define PCI_DEVICE_ID_VIA_VT630X 0x3044
  229. #define PCI_REV_ID_VIA_VT6306 0x46
  230. #define PCI_DEVICE_ID_VIA_VT6315 0x3403
  231. #define QUIRK_CYCLE_TIMER 0x1
  232. #define QUIRK_RESET_PACKET 0x2
  233. #define QUIRK_BE_HEADERS 0x4
  234. #define QUIRK_NO_1394A 0x8
  235. #define QUIRK_NO_MSI 0x10
  236. #define QUIRK_TI_SLLZ059 0x20
  237. #define QUIRK_IR_WAKE 0x40
  238. /* In case of multiple matches in ohci_quirks[], only the first one is used. */
  239. static const struct {
  240. unsigned short vendor, device, revision, flags;
  241. } ohci_quirks[] = {
  242. {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
  243. QUIRK_CYCLE_TIMER},
  244. {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
  245. QUIRK_BE_HEADERS},
  246. {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
  247. QUIRK_NO_MSI},
  248. {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
  249. QUIRK_RESET_PACKET},
  250. {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
  251. QUIRK_NO_MSI},
  252. {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
  253. QUIRK_CYCLE_TIMER},
  254. {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
  255. QUIRK_NO_MSI},
  256. {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
  257. QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
  258. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
  259. QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
  260. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
  261. QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
  262. {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
  263. QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
  264. {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
  265. QUIRK_RESET_PACKET},
  266. {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
  267. QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
  268. {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
  269. QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
  270. {PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
  271. QUIRK_NO_MSI},
  272. {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
  273. QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
  274. };
  275. /* This overrides anything that was found in ohci_quirks[]. */
  276. static int param_quirks;
  277. module_param_named(quirks, param_quirks, int, 0644);
  278. MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
  279. ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
  280. ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
  281. ", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
  282. ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
  283. ", disable MSI = " __stringify(QUIRK_NO_MSI)
  284. ", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
  285. ", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
  286. ")");
  287. #define OHCI_PARAM_DEBUG_AT_AR 1
  288. #define OHCI_PARAM_DEBUG_SELFIDS 2
  289. #define OHCI_PARAM_DEBUG_IRQS 4
  290. #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
  291. static int param_debug;
  292. module_param_named(debug, param_debug, int, 0644);
  293. MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
  294. ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
  295. ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
  296. ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
  297. ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
  298. ", or a combination, or all = -1)");
  299. static bool param_remote_dma;
  300. module_param_named(remote_dma, param_remote_dma, bool, 0444);
  301. MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
  302. static void log_irqs(struct fw_ohci *ohci, u32 evt)
  303. {
  304. if (likely(!(param_debug &
  305. (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
  306. return;
  307. if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
  308. !(evt & OHCI1394_busReset))
  309. return;
  310. ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
  311. evt & OHCI1394_selfIDComplete ? " selfID" : "",
  312. evt & OHCI1394_RQPkt ? " AR_req" : "",
  313. evt & OHCI1394_RSPkt ? " AR_resp" : "",
  314. evt & OHCI1394_reqTxComplete ? " AT_req" : "",
  315. evt & OHCI1394_respTxComplete ? " AT_resp" : "",
  316. evt & OHCI1394_isochRx ? " IR" : "",
  317. evt & OHCI1394_isochTx ? " IT" : "",
  318. evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
  319. evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
  320. evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
  321. evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
  322. evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
  323. evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
  324. evt & OHCI1394_busReset ? " busReset" : "",
  325. evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
  326. OHCI1394_RSPkt | OHCI1394_reqTxComplete |
  327. OHCI1394_respTxComplete | OHCI1394_isochRx |
  328. OHCI1394_isochTx | OHCI1394_postedWriteErr |
  329. OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
  330. OHCI1394_cycleInconsistent |
  331. OHCI1394_regAccessFail | OHCI1394_busReset)
  332. ? " ?" : "");
  333. }
  334. static const char *speed[] = {
  335. [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
  336. };
  337. static const char *power[] = {
  338. [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
  339. [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
  340. };
  341. static const char port[] = { '.', '-', 'p', 'c', };
  342. static char _p(u32 *s, int shift)
  343. {
  344. return port[*s >> shift & 3];
  345. }
  346. static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
  347. {
  348. u32 *s;
  349. if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
  350. return;
  351. ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
  352. self_id_count, generation, ohci->node_id);
  353. for (s = ohci->self_id_buffer; self_id_count--; ++s)
  354. if ((*s & 1 << 23) == 0)
  355. ohci_notice(ohci,
  356. "selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
  357. *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
  358. speed[*s >> 14 & 3], *s >> 16 & 63,
  359. power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
  360. *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
  361. else
  362. ohci_notice(ohci,
  363. "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
  364. *s, *s >> 24 & 63,
  365. _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
  366. _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
  367. }
  368. static const char *evts[] = {
  369. [0x00] = "evt_no_status", [0x01] = "-reserved-",
  370. [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
  371. [0x04] = "evt_underrun", [0x05] = "evt_overrun",
  372. [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
  373. [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
  374. [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
  375. [0x0c] = "-reserved-", [0x0d] = "-reserved-",
  376. [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
  377. [0x10] = "-reserved-", [0x11] = "ack_complete",
  378. [0x12] = "ack_pending ", [0x13] = "-reserved-",
  379. [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
  380. [0x16] = "ack_busy_B", [0x17] = "-reserved-",
  381. [0x18] = "-reserved-", [0x19] = "-reserved-",
  382. [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
  383. [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
  384. [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
  385. [0x20] = "pending/cancelled",
  386. };
  387. static const char *tcodes[] = {
  388. [0x0] = "QW req", [0x1] = "BW req",
  389. [0x2] = "W resp", [0x3] = "-reserved-",
  390. [0x4] = "QR req", [0x5] = "BR req",
  391. [0x6] = "QR resp", [0x7] = "BR resp",
  392. [0x8] = "cycle start", [0x9] = "Lk req",
  393. [0xa] = "async stream packet", [0xb] = "Lk resp",
  394. [0xc] = "-reserved-", [0xd] = "-reserved-",
  395. [0xe] = "link internal", [0xf] = "-reserved-",
  396. };
  397. static void log_ar_at_event(struct fw_ohci *ohci,
  398. char dir, int speed, u32 *header, int evt)
  399. {
  400. int tcode = header[0] >> 4 & 0xf;
  401. char specific[12];
  402. if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
  403. return;
  404. if (unlikely(evt >= ARRAY_SIZE(evts)))
  405. evt = 0x1f;
  406. if (evt == OHCI1394_evt_bus_reset) {
  407. ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
  408. dir, (header[2] >> 16) & 0xff);
  409. return;
  410. }
  411. switch (tcode) {
  412. case 0x0: case 0x6: case 0x8:
  413. snprintf(specific, sizeof(specific), " = %08x",
  414. be32_to_cpu((__force __be32)header[3]));
  415. break;
  416. case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
  417. snprintf(specific, sizeof(specific), " %x,%x",
  418. header[3] >> 16, header[3] & 0xffff);
  419. break;
  420. default:
  421. specific[0] = '\0';
  422. }
  423. switch (tcode) {
  424. case 0xa:
  425. ohci_notice(ohci, "A%c %s, %s\n",
  426. dir, evts[evt], tcodes[tcode]);
  427. break;
  428. case 0xe:
  429. ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
  430. dir, evts[evt], header[1], header[2]);
  431. break;
  432. case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
  433. ohci_notice(ohci,
  434. "A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
  435. dir, speed, header[0] >> 10 & 0x3f,
  436. header[1] >> 16, header[0] >> 16, evts[evt],
  437. tcodes[tcode], header[1] & 0xffff, header[2], specific);
  438. break;
  439. default:
  440. ohci_notice(ohci,
  441. "A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
  442. dir, speed, header[0] >> 10 & 0x3f,
  443. header[1] >> 16, header[0] >> 16, evts[evt],
  444. tcodes[tcode], specific);
  445. }
  446. }
  447. static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
  448. {
  449. writel(data, ohci->registers + offset);
  450. }
  451. static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
  452. {
  453. return readl(ohci->registers + offset);
  454. }
  455. static inline void flush_writes(const struct fw_ohci *ohci)
  456. {
  457. /* Do a dummy read to flush writes. */
  458. reg_read(ohci, OHCI1394_Version);
  459. }
  460. /*
  461. * Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
  462. * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
  463. * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
  464. * directly. Exceptions are intrinsically serialized contexts like pci_probe.
  465. */
  466. static int read_phy_reg(struct fw_ohci *ohci, int addr)
  467. {
  468. u32 val;
  469. int i;
  470. reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
  471. for (i = 0; i < 3 + 100; i++) {
  472. val = reg_read(ohci, OHCI1394_PhyControl);
  473. if (!~val)
  474. return -ENODEV; /* Card was ejected. */
  475. if (val & OHCI1394_PhyControl_ReadDone)
  476. return OHCI1394_PhyControl_ReadData(val);
  477. /*
  478. * Try a few times without waiting. Sleeping is necessary
  479. * only when the link/PHY interface is busy.
  480. */
  481. if (i >= 3)
  482. msleep(1);
  483. }
  484. ohci_err(ohci, "failed to read phy reg %d\n", addr);
  485. dump_stack();
  486. return -EBUSY;
  487. }
  488. static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
  489. {
  490. int i;
  491. reg_write(ohci, OHCI1394_PhyControl,
  492. OHCI1394_PhyControl_Write(addr, val));
  493. for (i = 0; i < 3 + 100; i++) {
  494. val = reg_read(ohci, OHCI1394_PhyControl);
  495. if (!~val)
  496. return -ENODEV; /* Card was ejected. */
  497. if (!(val & OHCI1394_PhyControl_WritePending))
  498. return 0;
  499. if (i >= 3)
  500. msleep(1);
  501. }
  502. ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
  503. dump_stack();
  504. return -EBUSY;
  505. }
  506. static int update_phy_reg(struct fw_ohci *ohci, int addr,
  507. int clear_bits, int set_bits)
  508. {
  509. int ret = read_phy_reg(ohci, addr);
  510. if (ret < 0)
  511. return ret;
  512. /*
  513. * The interrupt status bits are cleared by writing a one bit.
  514. * Avoid clearing them unless explicitly requested in set_bits.
  515. */
  516. if (addr == 5)
  517. clear_bits |= PHY_INT_STATUS_BITS;
  518. return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
  519. }
  520. static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
  521. {
  522. int ret;
  523. ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
  524. if (ret < 0)
  525. return ret;
  526. return read_phy_reg(ohci, addr);
  527. }
  528. static int ohci_read_phy_reg(struct fw_card *card, int addr)
  529. {
  530. struct fw_ohci *ohci = fw_ohci(card);
  531. int ret;
  532. mutex_lock(&ohci->phy_reg_mutex);
  533. ret = read_phy_reg(ohci, addr);
  534. mutex_unlock(&ohci->phy_reg_mutex);
  535. return ret;
  536. }
  537. static int ohci_update_phy_reg(struct fw_card *card, int addr,
  538. int clear_bits, int set_bits)
  539. {
  540. struct fw_ohci *ohci = fw_ohci(card);
  541. int ret;
  542. mutex_lock(&ohci->phy_reg_mutex);
  543. ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
  544. mutex_unlock(&ohci->phy_reg_mutex);
  545. return ret;
  546. }
  547. static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
  548. {
  549. return page_private(ctx->pages[i]);
  550. }
  551. static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
  552. {
  553. struct descriptor *d;
  554. d = &ctx->descriptors[index];
  555. d->branch_address &= cpu_to_le32(~0xf);
  556. d->res_count = cpu_to_le16(PAGE_SIZE);
  557. d->transfer_status = 0;
  558. wmb(); /* finish init of new descriptors before branch_address update */
  559. d = &ctx->descriptors[ctx->last_buffer_index];
  560. d->branch_address |= cpu_to_le32(1);
  561. ctx->last_buffer_index = index;
  562. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  563. }
  564. static void ar_context_release(struct ar_context *ctx)
  565. {
  566. struct device *dev = ctx->ohci->card.device;
  567. unsigned int i;
  568. vunmap(ctx->buffer);
  569. for (i = 0; i < AR_BUFFERS; i++) {
  570. if (ctx->pages[i])
  571. dma_free_pages(dev, PAGE_SIZE, ctx->pages[i],
  572. ar_buffer_bus(ctx, i), DMA_FROM_DEVICE);
  573. }
  574. }
  575. static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
  576. {
  577. struct fw_ohci *ohci = ctx->ohci;
  578. if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
  579. reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
  580. flush_writes(ohci);
  581. ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
  582. }
  583. /* FIXME: restart? */
  584. }
  585. static inline unsigned int ar_next_buffer_index(unsigned int index)
  586. {
  587. return (index + 1) % AR_BUFFERS;
  588. }
  589. static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
  590. {
  591. return ar_next_buffer_index(ctx->last_buffer_index);
  592. }
  593. /*
  594. * We search for the buffer that contains the last AR packet DMA data written
  595. * by the controller.
  596. */
  597. static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
  598. unsigned int *buffer_offset)
  599. {
  600. unsigned int i, next_i, last = ctx->last_buffer_index;
  601. __le16 res_count, next_res_count;
  602. i = ar_first_buffer_index(ctx);
  603. res_count = READ_ONCE(ctx->descriptors[i].res_count);
  604. /* A buffer that is not yet completely filled must be the last one. */
  605. while (i != last && res_count == 0) {
  606. /* Peek at the next descriptor. */
  607. next_i = ar_next_buffer_index(i);
  608. rmb(); /* read descriptors in order */
  609. next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
  610. /*
  611. * If the next descriptor is still empty, we must stop at this
  612. * descriptor.
  613. */
  614. if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
  615. /*
  616. * The exception is when the DMA data for one packet is
  617. * split over three buffers; in this case, the middle
  618. * buffer's descriptor might be never updated by the
  619. * controller and look still empty, and we have to peek
  620. * at the third one.
  621. */
  622. if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
  623. next_i = ar_next_buffer_index(next_i);
  624. rmb();
  625. next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
  626. if (next_res_count != cpu_to_le16(PAGE_SIZE))
  627. goto next_buffer_is_active;
  628. }
  629. break;
  630. }
  631. next_buffer_is_active:
  632. i = next_i;
  633. res_count = next_res_count;
  634. }
  635. rmb(); /* read res_count before the DMA data */
  636. *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
  637. if (*buffer_offset > PAGE_SIZE) {
  638. *buffer_offset = 0;
  639. ar_context_abort(ctx, "corrupted descriptor");
  640. }
  641. return i;
  642. }
  643. static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
  644. unsigned int end_buffer_index,
  645. unsigned int end_buffer_offset)
  646. {
  647. unsigned int i;
  648. i = ar_first_buffer_index(ctx);
  649. while (i != end_buffer_index) {
  650. dma_sync_single_for_cpu(ctx->ohci->card.device,
  651. ar_buffer_bus(ctx, i),
  652. PAGE_SIZE, DMA_FROM_DEVICE);
  653. i = ar_next_buffer_index(i);
  654. }
  655. if (end_buffer_offset > 0)
  656. dma_sync_single_for_cpu(ctx->ohci->card.device,
  657. ar_buffer_bus(ctx, i),
  658. end_buffer_offset, DMA_FROM_DEVICE);
  659. }
  660. #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
  661. #define cond_le32_to_cpu(v) \
  662. (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
  663. #else
  664. #define cond_le32_to_cpu(v) le32_to_cpu(v)
  665. #endif
  666. static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
  667. {
  668. struct fw_ohci *ohci = ctx->ohci;
  669. struct fw_packet p;
  670. u32 status, length, tcode;
  671. int evt;
  672. p.header[0] = cond_le32_to_cpu(buffer[0]);
  673. p.header[1] = cond_le32_to_cpu(buffer[1]);
  674. p.header[2] = cond_le32_to_cpu(buffer[2]);
  675. tcode = (p.header[0] >> 4) & 0x0f;
  676. switch (tcode) {
  677. case TCODE_WRITE_QUADLET_REQUEST:
  678. case TCODE_READ_QUADLET_RESPONSE:
  679. p.header[3] = (__force __u32) buffer[3];
  680. p.header_length = 16;
  681. p.payload_length = 0;
  682. break;
  683. case TCODE_READ_BLOCK_REQUEST :
  684. p.header[3] = cond_le32_to_cpu(buffer[3]);
  685. p.header_length = 16;
  686. p.payload_length = 0;
  687. break;
  688. case TCODE_WRITE_BLOCK_REQUEST:
  689. case TCODE_READ_BLOCK_RESPONSE:
  690. case TCODE_LOCK_REQUEST:
  691. case TCODE_LOCK_RESPONSE:
  692. p.header[3] = cond_le32_to_cpu(buffer[3]);
  693. p.header_length = 16;
  694. p.payload_length = p.header[3] >> 16;
  695. if (p.payload_length > MAX_ASYNC_PAYLOAD) {
  696. ar_context_abort(ctx, "invalid packet length");
  697. return NULL;
  698. }
  699. break;
  700. case TCODE_WRITE_RESPONSE:
  701. case TCODE_READ_QUADLET_REQUEST:
  702. case OHCI_TCODE_PHY_PACKET:
  703. p.header_length = 12;
  704. p.payload_length = 0;
  705. break;
  706. default:
  707. ar_context_abort(ctx, "invalid tcode");
  708. return NULL;
  709. }
  710. p.payload = (void *) buffer + p.header_length;
  711. /* FIXME: What to do about evt_* errors? */
  712. length = (p.header_length + p.payload_length + 3) / 4;
  713. status = cond_le32_to_cpu(buffer[length]);
  714. evt = (status >> 16) & 0x1f;
  715. p.ack = evt - 16;
  716. p.speed = (status >> 21) & 0x7;
  717. p.timestamp = status & 0xffff;
  718. p.generation = ohci->request_generation;
  719. log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
  720. /*
  721. * Several controllers, notably from NEC and VIA, forget to
  722. * write ack_complete status at PHY packet reception.
  723. */
  724. if (evt == OHCI1394_evt_no_status &&
  725. (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
  726. p.ack = ACK_COMPLETE;
  727. /*
  728. * The OHCI bus reset handler synthesizes a PHY packet with
  729. * the new generation number when a bus reset happens (see
  730. * section 8.4.2.3). This helps us determine when a request
  731. * was received and make sure we send the response in the same
  732. * generation. We only need this for requests; for responses
  733. * we use the unique tlabel for finding the matching
  734. * request.
  735. *
  736. * Alas some chips sometimes emit bus reset packets with a
  737. * wrong generation. We set the correct generation for these
  738. * at a slightly incorrect time (in bus_reset_work).
  739. */
  740. if (evt == OHCI1394_evt_bus_reset) {
  741. if (!(ohci->quirks & QUIRK_RESET_PACKET))
  742. ohci->request_generation = (p.header[2] >> 16) & 0xff;
  743. } else if (ctx == &ohci->ar_request_ctx) {
  744. fw_core_handle_request(&ohci->card, &p);
  745. } else {
  746. fw_core_handle_response(&ohci->card, &p);
  747. }
  748. return buffer + length + 1;
  749. }
  750. static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
  751. {
  752. void *next;
  753. while (p < end) {
  754. next = handle_ar_packet(ctx, p);
  755. if (!next)
  756. return p;
  757. p = next;
  758. }
  759. return p;
  760. }
  761. static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
  762. {
  763. unsigned int i;
  764. i = ar_first_buffer_index(ctx);
  765. while (i != end_buffer) {
  766. dma_sync_single_for_device(ctx->ohci->card.device,
  767. ar_buffer_bus(ctx, i),
  768. PAGE_SIZE, DMA_FROM_DEVICE);
  769. ar_context_link_page(ctx, i);
  770. i = ar_next_buffer_index(i);
  771. }
  772. }
  773. static void ar_context_tasklet(unsigned long data)
  774. {
  775. struct ar_context *ctx = (struct ar_context *)data;
  776. unsigned int end_buffer_index, end_buffer_offset;
  777. void *p, *end;
  778. p = ctx->pointer;
  779. if (!p)
  780. return;
  781. end_buffer_index = ar_search_last_active_buffer(ctx,
  782. &end_buffer_offset);
  783. ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
  784. end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
  785. if (end_buffer_index < ar_first_buffer_index(ctx)) {
  786. /*
  787. * The filled part of the overall buffer wraps around; handle
  788. * all packets up to the buffer end here. If the last packet
  789. * wraps around, its tail will be visible after the buffer end
  790. * because the buffer start pages are mapped there again.
  791. */
  792. void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
  793. p = handle_ar_packets(ctx, p, buffer_end);
  794. if (p < buffer_end)
  795. goto error;
  796. /* adjust p to point back into the actual buffer */
  797. p -= AR_BUFFERS * PAGE_SIZE;
  798. }
  799. p = handle_ar_packets(ctx, p, end);
  800. if (p != end) {
  801. if (p > end)
  802. ar_context_abort(ctx, "inconsistent descriptor");
  803. goto error;
  804. }
  805. ctx->pointer = p;
  806. ar_recycle_buffers(ctx, end_buffer_index);
  807. return;
  808. error:
  809. ctx->pointer = NULL;
  810. }
  811. static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
  812. unsigned int descriptors_offset, u32 regs)
  813. {
  814. struct device *dev = ohci->card.device;
  815. unsigned int i;
  816. dma_addr_t dma_addr;
  817. struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
  818. struct descriptor *d;
  819. ctx->regs = regs;
  820. ctx->ohci = ohci;
  821. tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
  822. for (i = 0; i < AR_BUFFERS; i++) {
  823. ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr,
  824. DMA_FROM_DEVICE, GFP_KERNEL);
  825. if (!ctx->pages[i])
  826. goto out_of_memory;
  827. set_page_private(ctx->pages[i], dma_addr);
  828. dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE,
  829. DMA_FROM_DEVICE);
  830. }
  831. for (i = 0; i < AR_BUFFERS; i++)
  832. pages[i] = ctx->pages[i];
  833. for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
  834. pages[AR_BUFFERS + i] = ctx->pages[i];
  835. ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
  836. if (!ctx->buffer)
  837. goto out_of_memory;
  838. ctx->descriptors = ohci->misc_buffer + descriptors_offset;
  839. ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
  840. for (i = 0; i < AR_BUFFERS; i++) {
  841. d = &ctx->descriptors[i];
  842. d->req_count = cpu_to_le16(PAGE_SIZE);
  843. d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
  844. DESCRIPTOR_STATUS |
  845. DESCRIPTOR_BRANCH_ALWAYS);
  846. d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
  847. d->branch_address = cpu_to_le32(ctx->descriptors_bus +
  848. ar_next_buffer_index(i) * sizeof(struct descriptor));
  849. }
  850. return 0;
  851. out_of_memory:
  852. ar_context_release(ctx);
  853. return -ENOMEM;
  854. }
  855. static void ar_context_run(struct ar_context *ctx)
  856. {
  857. unsigned int i;
  858. for (i = 0; i < AR_BUFFERS; i++)
  859. ar_context_link_page(ctx, i);
  860. ctx->pointer = ctx->buffer;
  861. reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
  862. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
  863. }
  864. static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
  865. {
  866. __le16 branch;
  867. branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
  868. /* figure out which descriptor the branch address goes in */
  869. if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
  870. return d;
  871. else
  872. return d + z - 1;
  873. }
  874. static void context_tasklet(unsigned long data)
  875. {
  876. struct context *ctx = (struct context *) data;
  877. struct descriptor *d, *last;
  878. u32 address;
  879. int z;
  880. struct descriptor_buffer *desc;
  881. desc = list_entry(ctx->buffer_list.next,
  882. struct descriptor_buffer, list);
  883. last = ctx->last;
  884. while (last->branch_address != 0) {
  885. struct descriptor_buffer *old_desc = desc;
  886. address = le32_to_cpu(last->branch_address);
  887. z = address & 0xf;
  888. address &= ~0xf;
  889. ctx->current_bus = address;
  890. /* If the branch address points to a buffer outside of the
  891. * current buffer, advance to the next buffer. */
  892. if (address < desc->buffer_bus ||
  893. address >= desc->buffer_bus + desc->used)
  894. desc = list_entry(desc->list.next,
  895. struct descriptor_buffer, list);
  896. d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
  897. last = find_branch_descriptor(d, z);
  898. if (!ctx->callback(ctx, d, last))
  899. break;
  900. if (old_desc != desc) {
  901. /* If we've advanced to the next buffer, move the
  902. * previous buffer to the free list. */
  903. unsigned long flags;
  904. old_desc->used = 0;
  905. spin_lock_irqsave(&ctx->ohci->lock, flags);
  906. list_move_tail(&old_desc->list, &ctx->buffer_list);
  907. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  908. }
  909. ctx->last = last;
  910. }
  911. }
  912. /*
  913. * Allocate a new buffer and add it to the list of free buffers for this
  914. * context. Must be called with ohci->lock held.
  915. */
  916. static int context_add_buffer(struct context *ctx)
  917. {
  918. struct descriptor_buffer *desc;
  919. dma_addr_t bus_addr;
  920. int offset;
  921. /*
  922. * 16MB of descriptors should be far more than enough for any DMA
  923. * program. This will catch run-away userspace or DoS attacks.
  924. */
  925. if (ctx->total_allocation >= 16*1024*1024)
  926. return -ENOMEM;
  927. desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
  928. &bus_addr, GFP_ATOMIC);
  929. if (!desc)
  930. return -ENOMEM;
  931. offset = (void *)&desc->buffer - (void *)desc;
  932. /*
  933. * Some controllers, like JMicron ones, always issue 0x20-byte DMA reads
  934. * for descriptors, even 0x10-byte ones. This can cause page faults when
  935. * an IOMMU is in use and the oversized read crosses a page boundary.
  936. * Work around this by always leaving at least 0x10 bytes of padding.
  937. */
  938. desc->buffer_size = PAGE_SIZE - offset - 0x10;
  939. desc->buffer_bus = bus_addr + offset;
  940. desc->used = 0;
  941. list_add_tail(&desc->list, &ctx->buffer_list);
  942. ctx->total_allocation += PAGE_SIZE;
  943. return 0;
  944. }
  945. static int context_init(struct context *ctx, struct fw_ohci *ohci,
  946. u32 regs, descriptor_callback_t callback)
  947. {
  948. ctx->ohci = ohci;
  949. ctx->regs = regs;
  950. ctx->total_allocation = 0;
  951. INIT_LIST_HEAD(&ctx->buffer_list);
  952. if (context_add_buffer(ctx) < 0)
  953. return -ENOMEM;
  954. ctx->buffer_tail = list_entry(ctx->buffer_list.next,
  955. struct descriptor_buffer, list);
  956. tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
  957. ctx->callback = callback;
  958. /*
  959. * We put a dummy descriptor in the buffer that has a NULL
  960. * branch address and looks like it's been sent. That way we
  961. * have a descriptor to append DMA programs to.
  962. */
  963. memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
  964. ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
  965. ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
  966. ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
  967. ctx->last = ctx->buffer_tail->buffer;
  968. ctx->prev = ctx->buffer_tail->buffer;
  969. ctx->prev_z = 1;
  970. return 0;
  971. }
  972. static void context_release(struct context *ctx)
  973. {
  974. struct fw_card *card = &ctx->ohci->card;
  975. struct descriptor_buffer *desc, *tmp;
  976. list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
  977. dma_free_coherent(card->device, PAGE_SIZE, desc,
  978. desc->buffer_bus -
  979. ((void *)&desc->buffer - (void *)desc));
  980. }
  981. /* Must be called with ohci->lock held */
  982. static struct descriptor *context_get_descriptors(struct context *ctx,
  983. int z, dma_addr_t *d_bus)
  984. {
  985. struct descriptor *d = NULL;
  986. struct descriptor_buffer *desc = ctx->buffer_tail;
  987. if (z * sizeof(*d) > desc->buffer_size)
  988. return NULL;
  989. if (z * sizeof(*d) > desc->buffer_size - desc->used) {
  990. /* No room for the descriptor in this buffer, so advance to the
  991. * next one. */
  992. if (desc->list.next == &ctx->buffer_list) {
  993. /* If there is no free buffer next in the list,
  994. * allocate one. */
  995. if (context_add_buffer(ctx) < 0)
  996. return NULL;
  997. }
  998. desc = list_entry(desc->list.next,
  999. struct descriptor_buffer, list);
  1000. ctx->buffer_tail = desc;
  1001. }
  1002. d = desc->buffer + desc->used / sizeof(*d);
  1003. memset(d, 0, z * sizeof(*d));
  1004. *d_bus = desc->buffer_bus + desc->used;
  1005. return d;
  1006. }
  1007. static void context_run(struct context *ctx, u32 extra)
  1008. {
  1009. struct fw_ohci *ohci = ctx->ohci;
  1010. reg_write(ohci, COMMAND_PTR(ctx->regs),
  1011. le32_to_cpu(ctx->last->branch_address));
  1012. reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
  1013. reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
  1014. ctx->running = true;
  1015. flush_writes(ohci);
  1016. }
  1017. static void context_append(struct context *ctx,
  1018. struct descriptor *d, int z, int extra)
  1019. {
  1020. dma_addr_t d_bus;
  1021. struct descriptor_buffer *desc = ctx->buffer_tail;
  1022. struct descriptor *d_branch;
  1023. d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
  1024. desc->used += (z + extra) * sizeof(*d);
  1025. wmb(); /* finish init of new descriptors before branch_address update */
  1026. d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
  1027. d_branch->branch_address = cpu_to_le32(d_bus | z);
  1028. /*
  1029. * VT6306 incorrectly checks only the single descriptor at the
  1030. * CommandPtr when the wake bit is written, so if it's a
  1031. * multi-descriptor block starting with an INPUT_MORE, put a copy of
  1032. * the branch address in the first descriptor.
  1033. *
  1034. * Not doing this for transmit contexts since not sure how it interacts
  1035. * with skip addresses.
  1036. */
  1037. if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
  1038. d_branch != ctx->prev &&
  1039. (ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
  1040. cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
  1041. ctx->prev->branch_address = cpu_to_le32(d_bus | z);
  1042. }
  1043. ctx->prev = d;
  1044. ctx->prev_z = z;
  1045. }
  1046. static void context_stop(struct context *ctx)
  1047. {
  1048. struct fw_ohci *ohci = ctx->ohci;
  1049. u32 reg;
  1050. int i;
  1051. reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
  1052. ctx->running = false;
  1053. for (i = 0; i < 1000; i++) {
  1054. reg = reg_read(ohci, CONTROL_SET(ctx->regs));
  1055. if ((reg & CONTEXT_ACTIVE) == 0)
  1056. return;
  1057. if (i)
  1058. udelay(10);
  1059. }
  1060. ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
  1061. }
  1062. struct driver_data {
  1063. u8 inline_data[8];
  1064. struct fw_packet *packet;
  1065. };
  1066. /*
  1067. * This function apppends a packet to the DMA queue for transmission.
  1068. * Must always be called with the ochi->lock held to ensure proper
  1069. * generation handling and locking around packet queue manipulation.
  1070. */
  1071. static int at_context_queue_packet(struct context *ctx,
  1072. struct fw_packet *packet)
  1073. {
  1074. struct fw_ohci *ohci = ctx->ohci;
  1075. dma_addr_t d_bus, payload_bus;
  1076. struct driver_data *driver_data;
  1077. struct descriptor *d, *last;
  1078. __le32 *header;
  1079. int z, tcode;
  1080. d = context_get_descriptors(ctx, 4, &d_bus);
  1081. if (d == NULL) {
  1082. packet->ack = RCODE_SEND_ERROR;
  1083. return -1;
  1084. }
  1085. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  1086. d[0].res_count = cpu_to_le16(packet->timestamp);
  1087. /*
  1088. * The DMA format for asynchronous link packets is different
  1089. * from the IEEE1394 layout, so shift the fields around
  1090. * accordingly.
  1091. */
  1092. tcode = (packet->header[0] >> 4) & 0x0f;
  1093. header = (__le32 *) &d[1];
  1094. switch (tcode) {
  1095. case TCODE_WRITE_QUADLET_REQUEST:
  1096. case TCODE_WRITE_BLOCK_REQUEST:
  1097. case TCODE_WRITE_RESPONSE:
  1098. case TCODE_READ_QUADLET_REQUEST:
  1099. case TCODE_READ_BLOCK_REQUEST:
  1100. case TCODE_READ_QUADLET_RESPONSE:
  1101. case TCODE_READ_BLOCK_RESPONSE:
  1102. case TCODE_LOCK_REQUEST:
  1103. case TCODE_LOCK_RESPONSE:
  1104. header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
  1105. (packet->speed << 16));
  1106. header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
  1107. (packet->header[0] & 0xffff0000));
  1108. header[2] = cpu_to_le32(packet->header[2]);
  1109. if (TCODE_IS_BLOCK_PACKET(tcode))
  1110. header[3] = cpu_to_le32(packet->header[3]);
  1111. else
  1112. header[3] = (__force __le32) packet->header[3];
  1113. d[0].req_count = cpu_to_le16(packet->header_length);
  1114. break;
  1115. case TCODE_LINK_INTERNAL:
  1116. header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
  1117. (packet->speed << 16));
  1118. header[1] = cpu_to_le32(packet->header[1]);
  1119. header[2] = cpu_to_le32(packet->header[2]);
  1120. d[0].req_count = cpu_to_le16(12);
  1121. if (is_ping_packet(&packet->header[1]))
  1122. d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
  1123. break;
  1124. case TCODE_STREAM_DATA:
  1125. header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
  1126. (packet->speed << 16));
  1127. header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
  1128. d[0].req_count = cpu_to_le16(8);
  1129. break;
  1130. default:
  1131. /* BUG(); */
  1132. packet->ack = RCODE_SEND_ERROR;
  1133. return -1;
  1134. }
  1135. BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
  1136. driver_data = (struct driver_data *) &d[3];
  1137. driver_data->packet = packet;
  1138. packet->driver_data = driver_data;
  1139. if (packet->payload_length > 0) {
  1140. if (packet->payload_length > sizeof(driver_data->inline_data)) {
  1141. payload_bus = dma_map_single(ohci->card.device,
  1142. packet->payload,
  1143. packet->payload_length,
  1144. DMA_TO_DEVICE);
  1145. if (dma_mapping_error(ohci->card.device, payload_bus)) {
  1146. packet->ack = RCODE_SEND_ERROR;
  1147. return -1;
  1148. }
  1149. packet->payload_bus = payload_bus;
  1150. packet->payload_mapped = true;
  1151. } else {
  1152. memcpy(driver_data->inline_data, packet->payload,
  1153. packet->payload_length);
  1154. payload_bus = d_bus + 3 * sizeof(*d);
  1155. }
  1156. d[2].req_count = cpu_to_le16(packet->payload_length);
  1157. d[2].data_address = cpu_to_le32(payload_bus);
  1158. last = &d[2];
  1159. z = 3;
  1160. } else {
  1161. last = &d[0];
  1162. z = 2;
  1163. }
  1164. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  1165. DESCRIPTOR_IRQ_ALWAYS |
  1166. DESCRIPTOR_BRANCH_ALWAYS);
  1167. /* FIXME: Document how the locking works. */
  1168. if (ohci->generation != packet->generation) {
  1169. if (packet->payload_mapped)
  1170. dma_unmap_single(ohci->card.device, payload_bus,
  1171. packet->payload_length, DMA_TO_DEVICE);
  1172. packet->ack = RCODE_GENERATION;
  1173. return -1;
  1174. }
  1175. context_append(ctx, d, z, 4 - z);
  1176. if (ctx->running)
  1177. reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  1178. else
  1179. context_run(ctx, 0);
  1180. return 0;
  1181. }
  1182. static void at_context_flush(struct context *ctx)
  1183. {
  1184. tasklet_disable(&ctx->tasklet);
  1185. ctx->flushing = true;
  1186. context_tasklet((unsigned long)ctx);
  1187. ctx->flushing = false;
  1188. tasklet_enable(&ctx->tasklet);
  1189. }
  1190. static int handle_at_packet(struct context *context,
  1191. struct descriptor *d,
  1192. struct descriptor *last)
  1193. {
  1194. struct driver_data *driver_data;
  1195. struct fw_packet *packet;
  1196. struct fw_ohci *ohci = context->ohci;
  1197. int evt;
  1198. if (last->transfer_status == 0 && !context->flushing)
  1199. /* This descriptor isn't done yet, stop iteration. */
  1200. return 0;
  1201. driver_data = (struct driver_data *) &d[3];
  1202. packet = driver_data->packet;
  1203. if (packet == NULL)
  1204. /* This packet was cancelled, just continue. */
  1205. return 1;
  1206. if (packet->payload_mapped)
  1207. dma_unmap_single(ohci->card.device, packet->payload_bus,
  1208. packet->payload_length, DMA_TO_DEVICE);
  1209. evt = le16_to_cpu(last->transfer_status) & 0x1f;
  1210. packet->timestamp = le16_to_cpu(last->res_count);
  1211. log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
  1212. switch (evt) {
  1213. case OHCI1394_evt_timeout:
  1214. /* Async response transmit timed out. */
  1215. packet->ack = RCODE_CANCELLED;
  1216. break;
  1217. case OHCI1394_evt_flushed:
  1218. /*
  1219. * The packet was flushed should give same error as
  1220. * when we try to use a stale generation count.
  1221. */
  1222. packet->ack = RCODE_GENERATION;
  1223. break;
  1224. case OHCI1394_evt_missing_ack:
  1225. if (context->flushing)
  1226. packet->ack = RCODE_GENERATION;
  1227. else {
  1228. /*
  1229. * Using a valid (current) generation count, but the
  1230. * node is not on the bus or not sending acks.
  1231. */
  1232. packet->ack = RCODE_NO_ACK;
  1233. }
  1234. break;
  1235. case ACK_COMPLETE + 0x10:
  1236. case ACK_PENDING + 0x10:
  1237. case ACK_BUSY_X + 0x10:
  1238. case ACK_BUSY_A + 0x10:
  1239. case ACK_BUSY_B + 0x10:
  1240. case ACK_DATA_ERROR + 0x10:
  1241. case ACK_TYPE_ERROR + 0x10:
  1242. packet->ack = evt - 0x10;
  1243. break;
  1244. case OHCI1394_evt_no_status:
  1245. if (context->flushing) {
  1246. packet->ack = RCODE_GENERATION;
  1247. break;
  1248. }
  1249. fallthrough;
  1250. default:
  1251. packet->ack = RCODE_SEND_ERROR;
  1252. break;
  1253. }
  1254. packet->callback(packet, &ohci->card, packet->ack);
  1255. return 1;
  1256. }
  1257. #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
  1258. #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
  1259. #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
  1260. #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
  1261. #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
  1262. static void handle_local_rom(struct fw_ohci *ohci,
  1263. struct fw_packet *packet, u32 csr)
  1264. {
  1265. struct fw_packet response;
  1266. int tcode, length, i;
  1267. tcode = HEADER_GET_TCODE(packet->header[0]);
  1268. if (TCODE_IS_BLOCK_PACKET(tcode))
  1269. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  1270. else
  1271. length = 4;
  1272. i = csr - CSR_CONFIG_ROM;
  1273. if (i + length > CONFIG_ROM_SIZE) {
  1274. fw_fill_response(&response, packet->header,
  1275. RCODE_ADDRESS_ERROR, NULL, 0);
  1276. } else if (!TCODE_IS_READ_REQUEST(tcode)) {
  1277. fw_fill_response(&response, packet->header,
  1278. RCODE_TYPE_ERROR, NULL, 0);
  1279. } else {
  1280. fw_fill_response(&response, packet->header, RCODE_COMPLETE,
  1281. (void *) ohci->config_rom + i, length);
  1282. }
  1283. fw_core_handle_response(&ohci->card, &response);
  1284. }
  1285. static void handle_local_lock(struct fw_ohci *ohci,
  1286. struct fw_packet *packet, u32 csr)
  1287. {
  1288. struct fw_packet response;
  1289. int tcode, length, ext_tcode, sel, try;
  1290. __be32 *payload, lock_old;
  1291. u32 lock_arg, lock_data;
  1292. tcode = HEADER_GET_TCODE(packet->header[0]);
  1293. length = HEADER_GET_DATA_LENGTH(packet->header[3]);
  1294. payload = packet->payload;
  1295. ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
  1296. if (tcode == TCODE_LOCK_REQUEST &&
  1297. ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
  1298. lock_arg = be32_to_cpu(payload[0]);
  1299. lock_data = be32_to_cpu(payload[1]);
  1300. } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
  1301. lock_arg = 0;
  1302. lock_data = 0;
  1303. } else {
  1304. fw_fill_response(&response, packet->header,
  1305. RCODE_TYPE_ERROR, NULL, 0);
  1306. goto out;
  1307. }
  1308. sel = (csr - CSR_BUS_MANAGER_ID) / 4;
  1309. reg_write(ohci, OHCI1394_CSRData, lock_data);
  1310. reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
  1311. reg_write(ohci, OHCI1394_CSRControl, sel);
  1312. for (try = 0; try < 20; try++)
  1313. if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
  1314. lock_old = cpu_to_be32(reg_read(ohci,
  1315. OHCI1394_CSRData));
  1316. fw_fill_response(&response, packet->header,
  1317. RCODE_COMPLETE,
  1318. &lock_old, sizeof(lock_old));
  1319. goto out;
  1320. }
  1321. ohci_err(ohci, "swap not done (CSR lock timeout)\n");
  1322. fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
  1323. out:
  1324. fw_core_handle_response(&ohci->card, &response);
  1325. }
  1326. static void handle_local_request(struct context *ctx, struct fw_packet *packet)
  1327. {
  1328. u64 offset, csr;
  1329. if (ctx == &ctx->ohci->at_request_ctx) {
  1330. packet->ack = ACK_PENDING;
  1331. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1332. }
  1333. offset =
  1334. ((unsigned long long)
  1335. HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
  1336. packet->header[2];
  1337. csr = offset - CSR_REGISTER_BASE;
  1338. /* Handle config rom reads. */
  1339. if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
  1340. handle_local_rom(ctx->ohci, packet, csr);
  1341. else switch (csr) {
  1342. case CSR_BUS_MANAGER_ID:
  1343. case CSR_BANDWIDTH_AVAILABLE:
  1344. case CSR_CHANNELS_AVAILABLE_HI:
  1345. case CSR_CHANNELS_AVAILABLE_LO:
  1346. handle_local_lock(ctx->ohci, packet, csr);
  1347. break;
  1348. default:
  1349. if (ctx == &ctx->ohci->at_request_ctx)
  1350. fw_core_handle_request(&ctx->ohci->card, packet);
  1351. else
  1352. fw_core_handle_response(&ctx->ohci->card, packet);
  1353. break;
  1354. }
  1355. if (ctx == &ctx->ohci->at_response_ctx) {
  1356. packet->ack = ACK_COMPLETE;
  1357. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1358. }
  1359. }
  1360. static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
  1361. {
  1362. unsigned long flags;
  1363. int ret;
  1364. spin_lock_irqsave(&ctx->ohci->lock, flags);
  1365. if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
  1366. ctx->ohci->generation == packet->generation) {
  1367. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1368. handle_local_request(ctx, packet);
  1369. return;
  1370. }
  1371. ret = at_context_queue_packet(ctx, packet);
  1372. spin_unlock_irqrestore(&ctx->ohci->lock, flags);
  1373. if (ret < 0)
  1374. packet->callback(packet, &ctx->ohci->card, packet->ack);
  1375. }
  1376. static void detect_dead_context(struct fw_ohci *ohci,
  1377. const char *name, unsigned int regs)
  1378. {
  1379. u32 ctl;
  1380. ctl = reg_read(ohci, CONTROL_SET(regs));
  1381. if (ctl & CONTEXT_DEAD)
  1382. ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
  1383. name, evts[ctl & 0x1f]);
  1384. }
  1385. static void handle_dead_contexts(struct fw_ohci *ohci)
  1386. {
  1387. unsigned int i;
  1388. char name[8];
  1389. detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
  1390. detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
  1391. detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
  1392. detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
  1393. for (i = 0; i < 32; ++i) {
  1394. if (!(ohci->it_context_support & (1 << i)))
  1395. continue;
  1396. sprintf(name, "IT%u", i);
  1397. detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
  1398. }
  1399. for (i = 0; i < 32; ++i) {
  1400. if (!(ohci->ir_context_support & (1 << i)))
  1401. continue;
  1402. sprintf(name, "IR%u", i);
  1403. detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
  1404. }
  1405. /* TODO: maybe try to flush and restart the dead contexts */
  1406. }
  1407. static u32 cycle_timer_ticks(u32 cycle_timer)
  1408. {
  1409. u32 ticks;
  1410. ticks = cycle_timer & 0xfff;
  1411. ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
  1412. ticks += (3072 * 8000) * (cycle_timer >> 25);
  1413. return ticks;
  1414. }
  1415. /*
  1416. * Some controllers exhibit one or more of the following bugs when updating the
  1417. * iso cycle timer register:
  1418. * - When the lowest six bits are wrapping around to zero, a read that happens
  1419. * at the same time will return garbage in the lowest ten bits.
  1420. * - When the cycleOffset field wraps around to zero, the cycleCount field is
  1421. * not incremented for about 60 ns.
  1422. * - Occasionally, the entire register reads zero.
  1423. *
  1424. * To catch these, we read the register three times and ensure that the
  1425. * difference between each two consecutive reads is approximately the same, i.e.
  1426. * less than twice the other. Furthermore, any negative difference indicates an
  1427. * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
  1428. * execute, so we have enough precision to compute the ratio of the differences.)
  1429. */
  1430. static u32 get_cycle_time(struct fw_ohci *ohci)
  1431. {
  1432. u32 c0, c1, c2;
  1433. u32 t0, t1, t2;
  1434. s32 diff01, diff12;
  1435. int i;
  1436. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1437. if (ohci->quirks & QUIRK_CYCLE_TIMER) {
  1438. i = 0;
  1439. c1 = c2;
  1440. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1441. do {
  1442. c0 = c1;
  1443. c1 = c2;
  1444. c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
  1445. t0 = cycle_timer_ticks(c0);
  1446. t1 = cycle_timer_ticks(c1);
  1447. t2 = cycle_timer_ticks(c2);
  1448. diff01 = t1 - t0;
  1449. diff12 = t2 - t1;
  1450. } while ((diff01 <= 0 || diff12 <= 0 ||
  1451. diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
  1452. && i++ < 20);
  1453. }
  1454. return c2;
  1455. }
  1456. /*
  1457. * This function has to be called at least every 64 seconds. The bus_time
  1458. * field stores not only the upper 25 bits of the BUS_TIME register but also
  1459. * the most significant bit of the cycle timer in bit 6 so that we can detect
  1460. * changes in this bit.
  1461. */
  1462. static u32 update_bus_time(struct fw_ohci *ohci)
  1463. {
  1464. u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
  1465. if (unlikely(!ohci->bus_time_running)) {
  1466. reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
  1467. ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) |
  1468. (cycle_time_seconds & 0x40);
  1469. ohci->bus_time_running = true;
  1470. }
  1471. if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
  1472. ohci->bus_time += 0x40;
  1473. return ohci->bus_time | cycle_time_seconds;
  1474. }
  1475. static int get_status_for_port(struct fw_ohci *ohci, int port_index)
  1476. {
  1477. int reg;
  1478. mutex_lock(&ohci->phy_reg_mutex);
  1479. reg = write_phy_reg(ohci, 7, port_index);
  1480. if (reg >= 0)
  1481. reg = read_phy_reg(ohci, 8);
  1482. mutex_unlock(&ohci->phy_reg_mutex);
  1483. if (reg < 0)
  1484. return reg;
  1485. switch (reg & 0x0f) {
  1486. case 0x06:
  1487. return 2; /* is child node (connected to parent node) */
  1488. case 0x0e:
  1489. return 3; /* is parent node (connected to child node) */
  1490. }
  1491. return 1; /* not connected */
  1492. }
  1493. static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
  1494. int self_id_count)
  1495. {
  1496. int i;
  1497. u32 entry;
  1498. for (i = 0; i < self_id_count; i++) {
  1499. entry = ohci->self_id_buffer[i];
  1500. if ((self_id & 0xff000000) == (entry & 0xff000000))
  1501. return -1;
  1502. if ((self_id & 0xff000000) < (entry & 0xff000000))
  1503. return i;
  1504. }
  1505. return i;
  1506. }
  1507. static int initiated_reset(struct fw_ohci *ohci)
  1508. {
  1509. int reg;
  1510. int ret = 0;
  1511. mutex_lock(&ohci->phy_reg_mutex);
  1512. reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
  1513. if (reg >= 0) {
  1514. reg = read_phy_reg(ohci, 8);
  1515. reg |= 0x40;
  1516. reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
  1517. if (reg >= 0) {
  1518. reg = read_phy_reg(ohci, 12); /* read register 12 */
  1519. if (reg >= 0) {
  1520. if ((reg & 0x08) == 0x08) {
  1521. /* bit 3 indicates "initiated reset" */
  1522. ret = 0x2;
  1523. }
  1524. }
  1525. }
  1526. }
  1527. mutex_unlock(&ohci->phy_reg_mutex);
  1528. return ret;
  1529. }
  1530. /*
  1531. * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
  1532. * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
  1533. * Construct the selfID from phy register contents.
  1534. */
  1535. static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
  1536. {
  1537. int reg, i, pos, status;
  1538. /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
  1539. u32 self_id = 0x8040c800;
  1540. reg = reg_read(ohci, OHCI1394_NodeID);
  1541. if (!(reg & OHCI1394_NodeID_idValid)) {
  1542. ohci_notice(ohci,
  1543. "node ID not valid, new bus reset in progress\n");
  1544. return -EBUSY;
  1545. }
  1546. self_id |= ((reg & 0x3f) << 24); /* phy ID */
  1547. reg = ohci_read_phy_reg(&ohci->card, 4);
  1548. if (reg < 0)
  1549. return reg;
  1550. self_id |= ((reg & 0x07) << 8); /* power class */
  1551. reg = ohci_read_phy_reg(&ohci->card, 1);
  1552. if (reg < 0)
  1553. return reg;
  1554. self_id |= ((reg & 0x3f) << 16); /* gap count */
  1555. for (i = 0; i < 3; i++) {
  1556. status = get_status_for_port(ohci, i);
  1557. if (status < 0)
  1558. return status;
  1559. self_id |= ((status & 0x3) << (6 - (i * 2)));
  1560. }
  1561. self_id |= initiated_reset(ohci);
  1562. pos = get_self_id_pos(ohci, self_id, self_id_count);
  1563. if (pos >= 0) {
  1564. memmove(&(ohci->self_id_buffer[pos+1]),
  1565. &(ohci->self_id_buffer[pos]),
  1566. (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
  1567. ohci->self_id_buffer[pos] = self_id;
  1568. self_id_count++;
  1569. }
  1570. return self_id_count;
  1571. }
  1572. static void bus_reset_work(struct work_struct *work)
  1573. {
  1574. struct fw_ohci *ohci =
  1575. container_of(work, struct fw_ohci, bus_reset_work);
  1576. int self_id_count, generation, new_generation, i, j;
  1577. u32 reg;
  1578. void *free_rom = NULL;
  1579. dma_addr_t free_rom_bus = 0;
  1580. bool is_new_root;
  1581. reg = reg_read(ohci, OHCI1394_NodeID);
  1582. if (!(reg & OHCI1394_NodeID_idValid)) {
  1583. ohci_notice(ohci,
  1584. "node ID not valid, new bus reset in progress\n");
  1585. return;
  1586. }
  1587. if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
  1588. ohci_notice(ohci, "malconfigured bus\n");
  1589. return;
  1590. }
  1591. ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
  1592. OHCI1394_NodeID_nodeNumber);
  1593. is_new_root = (reg & OHCI1394_NodeID_root) != 0;
  1594. if (!(ohci->is_root && is_new_root))
  1595. reg_write(ohci, OHCI1394_LinkControlSet,
  1596. OHCI1394_LinkControl_cycleMaster);
  1597. ohci->is_root = is_new_root;
  1598. reg = reg_read(ohci, OHCI1394_SelfIDCount);
  1599. if (reg & OHCI1394_SelfIDCount_selfIDError) {
  1600. ohci_notice(ohci, "self ID receive error\n");
  1601. return;
  1602. }
  1603. /*
  1604. * The count in the SelfIDCount register is the number of
  1605. * bytes in the self ID receive buffer. Since we also receive
  1606. * the inverted quadlets and a header quadlet, we shift one
  1607. * bit extra to get the actual number of self IDs.
  1608. */
  1609. self_id_count = (reg >> 3) & 0xff;
  1610. if (self_id_count > 252) {
  1611. ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
  1612. return;
  1613. }
  1614. generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
  1615. rmb();
  1616. for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
  1617. u32 id = cond_le32_to_cpu(ohci->self_id[i]);
  1618. u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
  1619. if (id != ~id2) {
  1620. /*
  1621. * If the invalid data looks like a cycle start packet,
  1622. * it's likely to be the result of the cycle master
  1623. * having a wrong gap count. In this case, the self IDs
  1624. * so far are valid and should be processed so that the
  1625. * bus manager can then correct the gap count.
  1626. */
  1627. if (id == 0xffff008f) {
  1628. ohci_notice(ohci, "ignoring spurious self IDs\n");
  1629. self_id_count = j;
  1630. break;
  1631. }
  1632. ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
  1633. j, self_id_count, id, id2);
  1634. return;
  1635. }
  1636. ohci->self_id_buffer[j] = id;
  1637. }
  1638. if (ohci->quirks & QUIRK_TI_SLLZ059) {
  1639. self_id_count = find_and_insert_self_id(ohci, self_id_count);
  1640. if (self_id_count < 0) {
  1641. ohci_notice(ohci,
  1642. "could not construct local self ID\n");
  1643. return;
  1644. }
  1645. }
  1646. if (self_id_count == 0) {
  1647. ohci_notice(ohci, "no self IDs\n");
  1648. return;
  1649. }
  1650. rmb();
  1651. /*
  1652. * Check the consistency of the self IDs we just read. The
  1653. * problem we face is that a new bus reset can start while we
  1654. * read out the self IDs from the DMA buffer. If this happens,
  1655. * the DMA buffer will be overwritten with new self IDs and we
  1656. * will read out inconsistent data. The OHCI specification
  1657. * (section 11.2) recommends a technique similar to
  1658. * linux/seqlock.h, where we remember the generation of the
  1659. * self IDs in the buffer before reading them out and compare
  1660. * it to the current generation after reading them out. If
  1661. * the two generations match we know we have a consistent set
  1662. * of self IDs.
  1663. */
  1664. new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
  1665. if (new_generation != generation) {
  1666. ohci_notice(ohci, "new bus reset, discarding self ids\n");
  1667. return;
  1668. }
  1669. /* FIXME: Document how the locking works. */
  1670. spin_lock_irq(&ohci->lock);
  1671. ohci->generation = -1; /* prevent AT packet queueing */
  1672. context_stop(&ohci->at_request_ctx);
  1673. context_stop(&ohci->at_response_ctx);
  1674. spin_unlock_irq(&ohci->lock);
  1675. /*
  1676. * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
  1677. * packets in the AT queues and software needs to drain them.
  1678. * Some OHCI 1.1 controllers (JMicron) apparently require this too.
  1679. */
  1680. at_context_flush(&ohci->at_request_ctx);
  1681. at_context_flush(&ohci->at_response_ctx);
  1682. spin_lock_irq(&ohci->lock);
  1683. ohci->generation = generation;
  1684. reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
  1685. if (ohci->quirks & QUIRK_RESET_PACKET)
  1686. ohci->request_generation = generation;
  1687. /*
  1688. * This next bit is unrelated to the AT context stuff but we
  1689. * have to do it under the spinlock also. If a new config rom
  1690. * was set up before this reset, the old one is now no longer
  1691. * in use and we can free it. Update the config rom pointers
  1692. * to point to the current config rom and clear the
  1693. * next_config_rom pointer so a new update can take place.
  1694. */
  1695. if (ohci->next_config_rom != NULL) {
  1696. if (ohci->next_config_rom != ohci->config_rom) {
  1697. free_rom = ohci->config_rom;
  1698. free_rom_bus = ohci->config_rom_bus;
  1699. }
  1700. ohci->config_rom = ohci->next_config_rom;
  1701. ohci->config_rom_bus = ohci->next_config_rom_bus;
  1702. ohci->next_config_rom = NULL;
  1703. /*
  1704. * Restore config_rom image and manually update
  1705. * config_rom registers. Writing the header quadlet
  1706. * will indicate that the config rom is ready, so we
  1707. * do that last.
  1708. */
  1709. reg_write(ohci, OHCI1394_BusOptions,
  1710. be32_to_cpu(ohci->config_rom[2]));
  1711. ohci->config_rom[0] = ohci->next_header;
  1712. reg_write(ohci, OHCI1394_ConfigROMhdr,
  1713. be32_to_cpu(ohci->next_header));
  1714. }
  1715. if (param_remote_dma) {
  1716. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
  1717. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
  1718. }
  1719. spin_unlock_irq(&ohci->lock);
  1720. if (free_rom)
  1721. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1722. free_rom, free_rom_bus);
  1723. log_selfids(ohci, generation, self_id_count);
  1724. fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
  1725. self_id_count, ohci->self_id_buffer,
  1726. ohci->csr_state_setclear_abdicate);
  1727. ohci->csr_state_setclear_abdicate = false;
  1728. }
  1729. static irqreturn_t irq_handler(int irq, void *data)
  1730. {
  1731. struct fw_ohci *ohci = data;
  1732. u32 event, iso_event;
  1733. int i;
  1734. event = reg_read(ohci, OHCI1394_IntEventClear);
  1735. if (!event || !~event)
  1736. return IRQ_NONE;
  1737. /*
  1738. * busReset and postedWriteErr must not be cleared yet
  1739. * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
  1740. */
  1741. reg_write(ohci, OHCI1394_IntEventClear,
  1742. event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
  1743. log_irqs(ohci, event);
  1744. if (event & OHCI1394_selfIDComplete)
  1745. queue_work(selfid_workqueue, &ohci->bus_reset_work);
  1746. if (event & OHCI1394_RQPkt)
  1747. tasklet_schedule(&ohci->ar_request_ctx.tasklet);
  1748. if (event & OHCI1394_RSPkt)
  1749. tasklet_schedule(&ohci->ar_response_ctx.tasklet);
  1750. if (event & OHCI1394_reqTxComplete)
  1751. tasklet_schedule(&ohci->at_request_ctx.tasklet);
  1752. if (event & OHCI1394_respTxComplete)
  1753. tasklet_schedule(&ohci->at_response_ctx.tasklet);
  1754. if (event & OHCI1394_isochRx) {
  1755. iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
  1756. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
  1757. while (iso_event) {
  1758. i = ffs(iso_event) - 1;
  1759. tasklet_schedule(
  1760. &ohci->ir_context_list[i].context.tasklet);
  1761. iso_event &= ~(1 << i);
  1762. }
  1763. }
  1764. if (event & OHCI1394_isochTx) {
  1765. iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
  1766. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
  1767. while (iso_event) {
  1768. i = ffs(iso_event) - 1;
  1769. tasklet_schedule(
  1770. &ohci->it_context_list[i].context.tasklet);
  1771. iso_event &= ~(1 << i);
  1772. }
  1773. }
  1774. if (unlikely(event & OHCI1394_regAccessFail))
  1775. ohci_err(ohci, "register access failure\n");
  1776. if (unlikely(event & OHCI1394_postedWriteErr)) {
  1777. reg_read(ohci, OHCI1394_PostedWriteAddressHi);
  1778. reg_read(ohci, OHCI1394_PostedWriteAddressLo);
  1779. reg_write(ohci, OHCI1394_IntEventClear,
  1780. OHCI1394_postedWriteErr);
  1781. if (printk_ratelimit())
  1782. ohci_err(ohci, "PCI posted write error\n");
  1783. }
  1784. if (unlikely(event & OHCI1394_cycleTooLong)) {
  1785. if (printk_ratelimit())
  1786. ohci_notice(ohci, "isochronous cycle too long\n");
  1787. reg_write(ohci, OHCI1394_LinkControlSet,
  1788. OHCI1394_LinkControl_cycleMaster);
  1789. }
  1790. if (unlikely(event & OHCI1394_cycleInconsistent)) {
  1791. /*
  1792. * We need to clear this event bit in order to make
  1793. * cycleMatch isochronous I/O work. In theory we should
  1794. * stop active cycleMatch iso contexts now and restart
  1795. * them at least two cycles later. (FIXME?)
  1796. */
  1797. if (printk_ratelimit())
  1798. ohci_notice(ohci, "isochronous cycle inconsistent\n");
  1799. }
  1800. if (unlikely(event & OHCI1394_unrecoverableError))
  1801. handle_dead_contexts(ohci);
  1802. if (event & OHCI1394_cycle64Seconds) {
  1803. spin_lock(&ohci->lock);
  1804. update_bus_time(ohci);
  1805. spin_unlock(&ohci->lock);
  1806. } else
  1807. flush_writes(ohci);
  1808. return IRQ_HANDLED;
  1809. }
  1810. static int software_reset(struct fw_ohci *ohci)
  1811. {
  1812. u32 val;
  1813. int i;
  1814. reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
  1815. for (i = 0; i < 500; i++) {
  1816. val = reg_read(ohci, OHCI1394_HCControlSet);
  1817. if (!~val)
  1818. return -ENODEV; /* Card was ejected. */
  1819. if (!(val & OHCI1394_HCControl_softReset))
  1820. return 0;
  1821. msleep(1);
  1822. }
  1823. return -EBUSY;
  1824. }
  1825. static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
  1826. {
  1827. size_t size = length * 4;
  1828. memcpy(dest, src, size);
  1829. if (size < CONFIG_ROM_SIZE)
  1830. memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
  1831. }
  1832. static int configure_1394a_enhancements(struct fw_ohci *ohci)
  1833. {
  1834. bool enable_1394a;
  1835. int ret, clear, set, offset;
  1836. /* Check if the driver should configure link and PHY. */
  1837. if (!(reg_read(ohci, OHCI1394_HCControlSet) &
  1838. OHCI1394_HCControl_programPhyEnable))
  1839. return 0;
  1840. /* Paranoia: check whether the PHY supports 1394a, too. */
  1841. enable_1394a = false;
  1842. ret = read_phy_reg(ohci, 2);
  1843. if (ret < 0)
  1844. return ret;
  1845. if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
  1846. ret = read_paged_phy_reg(ohci, 1, 8);
  1847. if (ret < 0)
  1848. return ret;
  1849. if (ret >= 1)
  1850. enable_1394a = true;
  1851. }
  1852. if (ohci->quirks & QUIRK_NO_1394A)
  1853. enable_1394a = false;
  1854. /* Configure PHY and link consistently. */
  1855. if (enable_1394a) {
  1856. clear = 0;
  1857. set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
  1858. } else {
  1859. clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
  1860. set = 0;
  1861. }
  1862. ret = update_phy_reg(ohci, 5, clear, set);
  1863. if (ret < 0)
  1864. return ret;
  1865. if (enable_1394a)
  1866. offset = OHCI1394_HCControlSet;
  1867. else
  1868. offset = OHCI1394_HCControlClear;
  1869. reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
  1870. /* Clean up: configuration has been taken care of. */
  1871. reg_write(ohci, OHCI1394_HCControlClear,
  1872. OHCI1394_HCControl_programPhyEnable);
  1873. return 0;
  1874. }
  1875. static int probe_tsb41ba3d(struct fw_ohci *ohci)
  1876. {
  1877. /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
  1878. static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
  1879. int reg, i;
  1880. reg = read_phy_reg(ohci, 2);
  1881. if (reg < 0)
  1882. return reg;
  1883. if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
  1884. return 0;
  1885. for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
  1886. reg = read_paged_phy_reg(ohci, 1, i + 10);
  1887. if (reg < 0)
  1888. return reg;
  1889. if (reg != id[i])
  1890. return 0;
  1891. }
  1892. return 1;
  1893. }
  1894. static int ohci_enable(struct fw_card *card,
  1895. const __be32 *config_rom, size_t length)
  1896. {
  1897. struct fw_ohci *ohci = fw_ohci(card);
  1898. u32 lps, version, irqs;
  1899. int i, ret;
  1900. ret = software_reset(ohci);
  1901. if (ret < 0) {
  1902. ohci_err(ohci, "failed to reset ohci card\n");
  1903. return ret;
  1904. }
  1905. /*
  1906. * Now enable LPS, which we need in order to start accessing
  1907. * most of the registers. In fact, on some cards (ALI M5251),
  1908. * accessing registers in the SClk domain without LPS enabled
  1909. * will lock up the machine. Wait 50msec to make sure we have
  1910. * full link enabled. However, with some cards (well, at least
  1911. * a JMicron PCIe card), we have to try again sometimes.
  1912. *
  1913. * TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
  1914. * cannot actually use the phy at that time. These need tens of
  1915. * millisecods pause between LPS write and first phy access too.
  1916. */
  1917. reg_write(ohci, OHCI1394_HCControlSet,
  1918. OHCI1394_HCControl_LPS |
  1919. OHCI1394_HCControl_postedWriteEnable);
  1920. flush_writes(ohci);
  1921. for (lps = 0, i = 0; !lps && i < 3; i++) {
  1922. msleep(50);
  1923. lps = reg_read(ohci, OHCI1394_HCControlSet) &
  1924. OHCI1394_HCControl_LPS;
  1925. }
  1926. if (!lps) {
  1927. ohci_err(ohci, "failed to set Link Power Status\n");
  1928. return -EIO;
  1929. }
  1930. if (ohci->quirks & QUIRK_TI_SLLZ059) {
  1931. ret = probe_tsb41ba3d(ohci);
  1932. if (ret < 0)
  1933. return ret;
  1934. if (ret)
  1935. ohci_notice(ohci, "local TSB41BA3D phy\n");
  1936. else
  1937. ohci->quirks &= ~QUIRK_TI_SLLZ059;
  1938. }
  1939. reg_write(ohci, OHCI1394_HCControlClear,
  1940. OHCI1394_HCControl_noByteSwapData);
  1941. reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
  1942. reg_write(ohci, OHCI1394_LinkControlSet,
  1943. OHCI1394_LinkControl_cycleTimerEnable |
  1944. OHCI1394_LinkControl_cycleMaster);
  1945. reg_write(ohci, OHCI1394_ATRetries,
  1946. OHCI1394_MAX_AT_REQ_RETRIES |
  1947. (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
  1948. (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
  1949. (200 << 16));
  1950. ohci->bus_time_running = false;
  1951. for (i = 0; i < 32; i++)
  1952. if (ohci->ir_context_support & (1 << i))
  1953. reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
  1954. IR_CONTEXT_MULTI_CHANNEL_MODE);
  1955. version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
  1956. if (version >= OHCI_VERSION_1_1) {
  1957. reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
  1958. 0xfffffffe);
  1959. card->broadcast_channel_auto_allocated = true;
  1960. }
  1961. /* Get implemented bits of the priority arbitration request counter. */
  1962. reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
  1963. ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
  1964. reg_write(ohci, OHCI1394_FairnessControl, 0);
  1965. card->priority_budget_implemented = ohci->pri_req_max != 0;
  1966. reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
  1967. reg_write(ohci, OHCI1394_IntEventClear, ~0);
  1968. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  1969. ret = configure_1394a_enhancements(ohci);
  1970. if (ret < 0)
  1971. return ret;
  1972. /* Activate link_on bit and contender bit in our self ID packets.*/
  1973. ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
  1974. if (ret < 0)
  1975. return ret;
  1976. /*
  1977. * When the link is not yet enabled, the atomic config rom
  1978. * update mechanism described below in ohci_set_config_rom()
  1979. * is not active. We have to update ConfigRomHeader and
  1980. * BusOptions manually, and the write to ConfigROMmap takes
  1981. * effect immediately. We tie this to the enabling of the
  1982. * link, so we have a valid config rom before enabling - the
  1983. * OHCI requires that ConfigROMhdr and BusOptions have valid
  1984. * values before enabling.
  1985. *
  1986. * However, when the ConfigROMmap is written, some controllers
  1987. * always read back quadlets 0 and 2 from the config rom to
  1988. * the ConfigRomHeader and BusOptions registers on bus reset.
  1989. * They shouldn't do that in this initial case where the link
  1990. * isn't enabled. This means we have to use the same
  1991. * workaround here, setting the bus header to 0 and then write
  1992. * the right values in the bus reset tasklet.
  1993. */
  1994. if (config_rom) {
  1995. ohci->next_config_rom =
  1996. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  1997. &ohci->next_config_rom_bus,
  1998. GFP_KERNEL);
  1999. if (ohci->next_config_rom == NULL)
  2000. return -ENOMEM;
  2001. copy_config_rom(ohci->next_config_rom, config_rom, length);
  2002. } else {
  2003. /*
  2004. * In the suspend case, config_rom is NULL, which
  2005. * means that we just reuse the old config rom.
  2006. */
  2007. ohci->next_config_rom = ohci->config_rom;
  2008. ohci->next_config_rom_bus = ohci->config_rom_bus;
  2009. }
  2010. ohci->next_header = ohci->next_config_rom[0];
  2011. ohci->next_config_rom[0] = 0;
  2012. reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
  2013. reg_write(ohci, OHCI1394_BusOptions,
  2014. be32_to_cpu(ohci->next_config_rom[2]));
  2015. reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
  2016. reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
  2017. irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
  2018. OHCI1394_RQPkt | OHCI1394_RSPkt |
  2019. OHCI1394_isochTx | OHCI1394_isochRx |
  2020. OHCI1394_postedWriteErr |
  2021. OHCI1394_selfIDComplete |
  2022. OHCI1394_regAccessFail |
  2023. OHCI1394_cycleInconsistent |
  2024. OHCI1394_unrecoverableError |
  2025. OHCI1394_cycleTooLong |
  2026. OHCI1394_masterIntEnable;
  2027. if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
  2028. irqs |= OHCI1394_busReset;
  2029. reg_write(ohci, OHCI1394_IntMaskSet, irqs);
  2030. reg_write(ohci, OHCI1394_HCControlSet,
  2031. OHCI1394_HCControl_linkEnable |
  2032. OHCI1394_HCControl_BIBimageValid);
  2033. reg_write(ohci, OHCI1394_LinkControlSet,
  2034. OHCI1394_LinkControl_rcvSelfID |
  2035. OHCI1394_LinkControl_rcvPhyPkt);
  2036. ar_context_run(&ohci->ar_request_ctx);
  2037. ar_context_run(&ohci->ar_response_ctx);
  2038. flush_writes(ohci);
  2039. /* We are ready to go, reset bus to finish initialization. */
  2040. fw_schedule_bus_reset(&ohci->card, false, true);
  2041. return 0;
  2042. }
  2043. static int ohci_set_config_rom(struct fw_card *card,
  2044. const __be32 *config_rom, size_t length)
  2045. {
  2046. struct fw_ohci *ohci;
  2047. __be32 *next_config_rom;
  2048. dma_addr_t next_config_rom_bus;
  2049. ohci = fw_ohci(card);
  2050. /*
  2051. * When the OHCI controller is enabled, the config rom update
  2052. * mechanism is a bit tricky, but easy enough to use. See
  2053. * section 5.5.6 in the OHCI specification.
  2054. *
  2055. * The OHCI controller caches the new config rom address in a
  2056. * shadow register (ConfigROMmapNext) and needs a bus reset
  2057. * for the changes to take place. When the bus reset is
  2058. * detected, the controller loads the new values for the
  2059. * ConfigRomHeader and BusOptions registers from the specified
  2060. * config rom and loads ConfigROMmap from the ConfigROMmapNext
  2061. * shadow register. All automatically and atomically.
  2062. *
  2063. * Now, there's a twist to this story. The automatic load of
  2064. * ConfigRomHeader and BusOptions doesn't honor the
  2065. * noByteSwapData bit, so with a be32 config rom, the
  2066. * controller will load be32 values in to these registers
  2067. * during the atomic update, even on litte endian
  2068. * architectures. The workaround we use is to put a 0 in the
  2069. * header quadlet; 0 is endian agnostic and means that the
  2070. * config rom isn't ready yet. In the bus reset tasklet we
  2071. * then set up the real values for the two registers.
  2072. *
  2073. * We use ohci->lock to avoid racing with the code that sets
  2074. * ohci->next_config_rom to NULL (see bus_reset_work).
  2075. */
  2076. next_config_rom =
  2077. dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  2078. &next_config_rom_bus, GFP_KERNEL);
  2079. if (next_config_rom == NULL)
  2080. return -ENOMEM;
  2081. spin_lock_irq(&ohci->lock);
  2082. /*
  2083. * If there is not an already pending config_rom update,
  2084. * push our new allocation into the ohci->next_config_rom
  2085. * and then mark the local variable as null so that we
  2086. * won't deallocate the new buffer.
  2087. *
  2088. * OTOH, if there is a pending config_rom update, just
  2089. * use that buffer with the new config_rom data, and
  2090. * let this routine free the unused DMA allocation.
  2091. */
  2092. if (ohci->next_config_rom == NULL) {
  2093. ohci->next_config_rom = next_config_rom;
  2094. ohci->next_config_rom_bus = next_config_rom_bus;
  2095. next_config_rom = NULL;
  2096. }
  2097. copy_config_rom(ohci->next_config_rom, config_rom, length);
  2098. ohci->next_header = config_rom[0];
  2099. ohci->next_config_rom[0] = 0;
  2100. reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
  2101. spin_unlock_irq(&ohci->lock);
  2102. /* If we didn't use the DMA allocation, delete it. */
  2103. if (next_config_rom != NULL)
  2104. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  2105. next_config_rom, next_config_rom_bus);
  2106. /*
  2107. * Now initiate a bus reset to have the changes take
  2108. * effect. We clean up the old config rom memory and DMA
  2109. * mappings in the bus reset tasklet, since the OHCI
  2110. * controller could need to access it before the bus reset
  2111. * takes effect.
  2112. */
  2113. fw_schedule_bus_reset(&ohci->card, true, true);
  2114. return 0;
  2115. }
  2116. static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
  2117. {
  2118. struct fw_ohci *ohci = fw_ohci(card);
  2119. at_context_transmit(&ohci->at_request_ctx, packet);
  2120. }
  2121. static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
  2122. {
  2123. struct fw_ohci *ohci = fw_ohci(card);
  2124. at_context_transmit(&ohci->at_response_ctx, packet);
  2125. }
  2126. static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
  2127. {
  2128. struct fw_ohci *ohci = fw_ohci(card);
  2129. struct context *ctx = &ohci->at_request_ctx;
  2130. struct driver_data *driver_data = packet->driver_data;
  2131. int ret = -ENOENT;
  2132. tasklet_disable(&ctx->tasklet);
  2133. if (packet->ack != 0)
  2134. goto out;
  2135. if (packet->payload_mapped)
  2136. dma_unmap_single(ohci->card.device, packet->payload_bus,
  2137. packet->payload_length, DMA_TO_DEVICE);
  2138. log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
  2139. driver_data->packet = NULL;
  2140. packet->ack = RCODE_CANCELLED;
  2141. packet->callback(packet, &ohci->card, packet->ack);
  2142. ret = 0;
  2143. out:
  2144. tasklet_enable(&ctx->tasklet);
  2145. return ret;
  2146. }
  2147. static int ohci_enable_phys_dma(struct fw_card *card,
  2148. int node_id, int generation)
  2149. {
  2150. struct fw_ohci *ohci = fw_ohci(card);
  2151. unsigned long flags;
  2152. int n, ret = 0;
  2153. if (param_remote_dma)
  2154. return 0;
  2155. /*
  2156. * FIXME: Make sure this bitmask is cleared when we clear the busReset
  2157. * interrupt bit. Clear physReqResourceAllBuses on bus reset.
  2158. */
  2159. spin_lock_irqsave(&ohci->lock, flags);
  2160. if (ohci->generation != generation) {
  2161. ret = -ESTALE;
  2162. goto out;
  2163. }
  2164. /*
  2165. * Note, if the node ID contains a non-local bus ID, physical DMA is
  2166. * enabled for _all_ nodes on remote buses.
  2167. */
  2168. n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
  2169. if (n < 32)
  2170. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
  2171. else
  2172. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
  2173. flush_writes(ohci);
  2174. out:
  2175. spin_unlock_irqrestore(&ohci->lock, flags);
  2176. return ret;
  2177. }
  2178. static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
  2179. {
  2180. struct fw_ohci *ohci = fw_ohci(card);
  2181. unsigned long flags;
  2182. u32 value;
  2183. switch (csr_offset) {
  2184. case CSR_STATE_CLEAR:
  2185. case CSR_STATE_SET:
  2186. if (ohci->is_root &&
  2187. (reg_read(ohci, OHCI1394_LinkControlSet) &
  2188. OHCI1394_LinkControl_cycleMaster))
  2189. value = CSR_STATE_BIT_CMSTR;
  2190. else
  2191. value = 0;
  2192. if (ohci->csr_state_setclear_abdicate)
  2193. value |= CSR_STATE_BIT_ABDICATE;
  2194. return value;
  2195. case CSR_NODE_IDS:
  2196. return reg_read(ohci, OHCI1394_NodeID) << 16;
  2197. case CSR_CYCLE_TIME:
  2198. return get_cycle_time(ohci);
  2199. case CSR_BUS_TIME:
  2200. /*
  2201. * We might be called just after the cycle timer has wrapped
  2202. * around but just before the cycle64Seconds handler, so we
  2203. * better check here, too, if the bus time needs to be updated.
  2204. */
  2205. spin_lock_irqsave(&ohci->lock, flags);
  2206. value = update_bus_time(ohci);
  2207. spin_unlock_irqrestore(&ohci->lock, flags);
  2208. return value;
  2209. case CSR_BUSY_TIMEOUT:
  2210. value = reg_read(ohci, OHCI1394_ATRetries);
  2211. return (value >> 4) & 0x0ffff00f;
  2212. case CSR_PRIORITY_BUDGET:
  2213. return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
  2214. (ohci->pri_req_max << 8);
  2215. default:
  2216. WARN_ON(1);
  2217. return 0;
  2218. }
  2219. }
  2220. static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
  2221. {
  2222. struct fw_ohci *ohci = fw_ohci(card);
  2223. unsigned long flags;
  2224. switch (csr_offset) {
  2225. case CSR_STATE_CLEAR:
  2226. if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
  2227. reg_write(ohci, OHCI1394_LinkControlClear,
  2228. OHCI1394_LinkControl_cycleMaster);
  2229. flush_writes(ohci);
  2230. }
  2231. if (value & CSR_STATE_BIT_ABDICATE)
  2232. ohci->csr_state_setclear_abdicate = false;
  2233. break;
  2234. case CSR_STATE_SET:
  2235. if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
  2236. reg_write(ohci, OHCI1394_LinkControlSet,
  2237. OHCI1394_LinkControl_cycleMaster);
  2238. flush_writes(ohci);
  2239. }
  2240. if (value & CSR_STATE_BIT_ABDICATE)
  2241. ohci->csr_state_setclear_abdicate = true;
  2242. break;
  2243. case CSR_NODE_IDS:
  2244. reg_write(ohci, OHCI1394_NodeID, value >> 16);
  2245. flush_writes(ohci);
  2246. break;
  2247. case CSR_CYCLE_TIME:
  2248. reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
  2249. reg_write(ohci, OHCI1394_IntEventSet,
  2250. OHCI1394_cycleInconsistent);
  2251. flush_writes(ohci);
  2252. break;
  2253. case CSR_BUS_TIME:
  2254. spin_lock_irqsave(&ohci->lock, flags);
  2255. ohci->bus_time = (update_bus_time(ohci) & 0x40) |
  2256. (value & ~0x7f);
  2257. spin_unlock_irqrestore(&ohci->lock, flags);
  2258. break;
  2259. case CSR_BUSY_TIMEOUT:
  2260. value = (value & 0xf) | ((value & 0xf) << 4) |
  2261. ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
  2262. reg_write(ohci, OHCI1394_ATRetries, value);
  2263. flush_writes(ohci);
  2264. break;
  2265. case CSR_PRIORITY_BUDGET:
  2266. reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
  2267. flush_writes(ohci);
  2268. break;
  2269. default:
  2270. WARN_ON(1);
  2271. break;
  2272. }
  2273. }
  2274. static void flush_iso_completions(struct iso_context *ctx)
  2275. {
  2276. ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
  2277. ctx->header_length, ctx->header,
  2278. ctx->base.callback_data);
  2279. ctx->header_length = 0;
  2280. }
  2281. static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
  2282. {
  2283. u32 *ctx_hdr;
  2284. if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
  2285. if (ctx->base.drop_overflow_headers)
  2286. return;
  2287. flush_iso_completions(ctx);
  2288. }
  2289. ctx_hdr = ctx->header + ctx->header_length;
  2290. ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
  2291. /*
  2292. * The two iso header quadlets are byteswapped to little
  2293. * endian by the controller, but we want to present them
  2294. * as big endian for consistency with the bus endianness.
  2295. */
  2296. if (ctx->base.header_size > 0)
  2297. ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
  2298. if (ctx->base.header_size > 4)
  2299. ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
  2300. if (ctx->base.header_size > 8)
  2301. memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
  2302. ctx->header_length += ctx->base.header_size;
  2303. }
  2304. static int handle_ir_packet_per_buffer(struct context *context,
  2305. struct descriptor *d,
  2306. struct descriptor *last)
  2307. {
  2308. struct iso_context *ctx =
  2309. container_of(context, struct iso_context, context);
  2310. struct descriptor *pd;
  2311. u32 buffer_dma;
  2312. for (pd = d; pd <= last; pd++)
  2313. if (pd->transfer_status)
  2314. break;
  2315. if (pd > last)
  2316. /* Descriptor(s) not done yet, stop iteration */
  2317. return 0;
  2318. while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
  2319. d++;
  2320. buffer_dma = le32_to_cpu(d->data_address);
  2321. dma_sync_single_range_for_cpu(context->ohci->card.device,
  2322. buffer_dma & PAGE_MASK,
  2323. buffer_dma & ~PAGE_MASK,
  2324. le16_to_cpu(d->req_count),
  2325. DMA_FROM_DEVICE);
  2326. }
  2327. copy_iso_headers(ctx, (u32 *) (last + 1));
  2328. if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
  2329. flush_iso_completions(ctx);
  2330. return 1;
  2331. }
  2332. /* d == last because each descriptor block is only a single descriptor. */
  2333. static int handle_ir_buffer_fill(struct context *context,
  2334. struct descriptor *d,
  2335. struct descriptor *last)
  2336. {
  2337. struct iso_context *ctx =
  2338. container_of(context, struct iso_context, context);
  2339. unsigned int req_count, res_count, completed;
  2340. u32 buffer_dma;
  2341. req_count = le16_to_cpu(last->req_count);
  2342. res_count = le16_to_cpu(READ_ONCE(last->res_count));
  2343. completed = req_count - res_count;
  2344. buffer_dma = le32_to_cpu(last->data_address);
  2345. if (completed > 0) {
  2346. ctx->mc_buffer_bus = buffer_dma;
  2347. ctx->mc_completed = completed;
  2348. }
  2349. if (res_count != 0)
  2350. /* Descriptor(s) not done yet, stop iteration */
  2351. return 0;
  2352. dma_sync_single_range_for_cpu(context->ohci->card.device,
  2353. buffer_dma & PAGE_MASK,
  2354. buffer_dma & ~PAGE_MASK,
  2355. completed, DMA_FROM_DEVICE);
  2356. if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
  2357. ctx->base.callback.mc(&ctx->base,
  2358. buffer_dma + completed,
  2359. ctx->base.callback_data);
  2360. ctx->mc_completed = 0;
  2361. }
  2362. return 1;
  2363. }
  2364. static void flush_ir_buffer_fill(struct iso_context *ctx)
  2365. {
  2366. dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
  2367. ctx->mc_buffer_bus & PAGE_MASK,
  2368. ctx->mc_buffer_bus & ~PAGE_MASK,
  2369. ctx->mc_completed, DMA_FROM_DEVICE);
  2370. ctx->base.callback.mc(&ctx->base,
  2371. ctx->mc_buffer_bus + ctx->mc_completed,
  2372. ctx->base.callback_data);
  2373. ctx->mc_completed = 0;
  2374. }
  2375. static inline void sync_it_packet_for_cpu(struct context *context,
  2376. struct descriptor *pd)
  2377. {
  2378. __le16 control;
  2379. u32 buffer_dma;
  2380. /* only packets beginning with OUTPUT_MORE* have data buffers */
  2381. if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
  2382. return;
  2383. /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
  2384. pd += 2;
  2385. /*
  2386. * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
  2387. * data buffer is in the context program's coherent page and must not
  2388. * be synced.
  2389. */
  2390. if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
  2391. (context->current_bus & PAGE_MASK)) {
  2392. if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
  2393. return;
  2394. pd++;
  2395. }
  2396. do {
  2397. buffer_dma = le32_to_cpu(pd->data_address);
  2398. dma_sync_single_range_for_cpu(context->ohci->card.device,
  2399. buffer_dma & PAGE_MASK,
  2400. buffer_dma & ~PAGE_MASK,
  2401. le16_to_cpu(pd->req_count),
  2402. DMA_TO_DEVICE);
  2403. control = pd->control;
  2404. pd++;
  2405. } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
  2406. }
  2407. static int handle_it_packet(struct context *context,
  2408. struct descriptor *d,
  2409. struct descriptor *last)
  2410. {
  2411. struct iso_context *ctx =
  2412. container_of(context, struct iso_context, context);
  2413. struct descriptor *pd;
  2414. __be32 *ctx_hdr;
  2415. for (pd = d; pd <= last; pd++)
  2416. if (pd->transfer_status)
  2417. break;
  2418. if (pd > last)
  2419. /* Descriptor(s) not done yet, stop iteration */
  2420. return 0;
  2421. sync_it_packet_for_cpu(context, d);
  2422. if (ctx->header_length + 4 > PAGE_SIZE) {
  2423. if (ctx->base.drop_overflow_headers)
  2424. return 1;
  2425. flush_iso_completions(ctx);
  2426. }
  2427. ctx_hdr = ctx->header + ctx->header_length;
  2428. ctx->last_timestamp = le16_to_cpu(last->res_count);
  2429. /* Present this value as big-endian to match the receive code */
  2430. *ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
  2431. le16_to_cpu(pd->res_count));
  2432. ctx->header_length += 4;
  2433. if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
  2434. flush_iso_completions(ctx);
  2435. return 1;
  2436. }
  2437. static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
  2438. {
  2439. u32 hi = channels >> 32, lo = channels;
  2440. reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
  2441. reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
  2442. reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
  2443. reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
  2444. ohci->mc_channels = channels;
  2445. }
  2446. static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
  2447. int type, int channel, size_t header_size)
  2448. {
  2449. struct fw_ohci *ohci = fw_ohci(card);
  2450. struct iso_context *ctx;
  2451. descriptor_callback_t callback;
  2452. u64 *channels;
  2453. u32 *mask, regs;
  2454. int index, ret = -EBUSY;
  2455. spin_lock_irq(&ohci->lock);
  2456. switch (type) {
  2457. case FW_ISO_CONTEXT_TRANSMIT:
  2458. mask = &ohci->it_context_mask;
  2459. callback = handle_it_packet;
  2460. index = ffs(*mask) - 1;
  2461. if (index >= 0) {
  2462. *mask &= ~(1 << index);
  2463. regs = OHCI1394_IsoXmitContextBase(index);
  2464. ctx = &ohci->it_context_list[index];
  2465. }
  2466. break;
  2467. case FW_ISO_CONTEXT_RECEIVE:
  2468. channels = &ohci->ir_context_channels;
  2469. mask = &ohci->ir_context_mask;
  2470. callback = handle_ir_packet_per_buffer;
  2471. index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
  2472. if (index >= 0) {
  2473. *channels &= ~(1ULL << channel);
  2474. *mask &= ~(1 << index);
  2475. regs = OHCI1394_IsoRcvContextBase(index);
  2476. ctx = &ohci->ir_context_list[index];
  2477. }
  2478. break;
  2479. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2480. mask = &ohci->ir_context_mask;
  2481. callback = handle_ir_buffer_fill;
  2482. index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
  2483. if (index >= 0) {
  2484. ohci->mc_allocated = true;
  2485. *mask &= ~(1 << index);
  2486. regs = OHCI1394_IsoRcvContextBase(index);
  2487. ctx = &ohci->ir_context_list[index];
  2488. }
  2489. break;
  2490. default:
  2491. index = -1;
  2492. ret = -ENOSYS;
  2493. }
  2494. spin_unlock_irq(&ohci->lock);
  2495. if (index < 0)
  2496. return ERR_PTR(ret);
  2497. memset(ctx, 0, sizeof(*ctx));
  2498. ctx->header_length = 0;
  2499. ctx->header = (void *) __get_free_page(GFP_KERNEL);
  2500. if (ctx->header == NULL) {
  2501. ret = -ENOMEM;
  2502. goto out;
  2503. }
  2504. ret = context_init(&ctx->context, ohci, regs, callback);
  2505. if (ret < 0)
  2506. goto out_with_header;
  2507. if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
  2508. set_multichannel_mask(ohci, 0);
  2509. ctx->mc_completed = 0;
  2510. }
  2511. return &ctx->base;
  2512. out_with_header:
  2513. free_page((unsigned long)ctx->header);
  2514. out:
  2515. spin_lock_irq(&ohci->lock);
  2516. switch (type) {
  2517. case FW_ISO_CONTEXT_RECEIVE:
  2518. *channels |= 1ULL << channel;
  2519. break;
  2520. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2521. ohci->mc_allocated = false;
  2522. break;
  2523. }
  2524. *mask |= 1 << index;
  2525. spin_unlock_irq(&ohci->lock);
  2526. return ERR_PTR(ret);
  2527. }
  2528. static int ohci_start_iso(struct fw_iso_context *base,
  2529. s32 cycle, u32 sync, u32 tags)
  2530. {
  2531. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2532. struct fw_ohci *ohci = ctx->context.ohci;
  2533. u32 control = IR_CONTEXT_ISOCH_HEADER, match;
  2534. int index;
  2535. /* the controller cannot start without any queued packets */
  2536. if (ctx->context.last->branch_address == 0)
  2537. return -ENODATA;
  2538. switch (ctx->base.type) {
  2539. case FW_ISO_CONTEXT_TRANSMIT:
  2540. index = ctx - ohci->it_context_list;
  2541. match = 0;
  2542. if (cycle >= 0)
  2543. match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
  2544. (cycle & 0x7fff) << 16;
  2545. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
  2546. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
  2547. context_run(&ctx->context, match);
  2548. break;
  2549. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2550. control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
  2551. fallthrough;
  2552. case FW_ISO_CONTEXT_RECEIVE:
  2553. index = ctx - ohci->ir_context_list;
  2554. match = (tags << 28) | (sync << 8) | ctx->base.channel;
  2555. if (cycle >= 0) {
  2556. match |= (cycle & 0x07fff) << 12;
  2557. control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
  2558. }
  2559. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
  2560. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
  2561. reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
  2562. context_run(&ctx->context, control);
  2563. ctx->sync = sync;
  2564. ctx->tags = tags;
  2565. break;
  2566. }
  2567. return 0;
  2568. }
  2569. static int ohci_stop_iso(struct fw_iso_context *base)
  2570. {
  2571. struct fw_ohci *ohci = fw_ohci(base->card);
  2572. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2573. int index;
  2574. switch (ctx->base.type) {
  2575. case FW_ISO_CONTEXT_TRANSMIT:
  2576. index = ctx - ohci->it_context_list;
  2577. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
  2578. break;
  2579. case FW_ISO_CONTEXT_RECEIVE:
  2580. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2581. index = ctx - ohci->ir_context_list;
  2582. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
  2583. break;
  2584. }
  2585. flush_writes(ohci);
  2586. context_stop(&ctx->context);
  2587. tasklet_kill(&ctx->context.tasklet);
  2588. return 0;
  2589. }
  2590. static void ohci_free_iso_context(struct fw_iso_context *base)
  2591. {
  2592. struct fw_ohci *ohci = fw_ohci(base->card);
  2593. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2594. unsigned long flags;
  2595. int index;
  2596. ohci_stop_iso(base);
  2597. context_release(&ctx->context);
  2598. free_page((unsigned long)ctx->header);
  2599. spin_lock_irqsave(&ohci->lock, flags);
  2600. switch (base->type) {
  2601. case FW_ISO_CONTEXT_TRANSMIT:
  2602. index = ctx - ohci->it_context_list;
  2603. ohci->it_context_mask |= 1 << index;
  2604. break;
  2605. case FW_ISO_CONTEXT_RECEIVE:
  2606. index = ctx - ohci->ir_context_list;
  2607. ohci->ir_context_mask |= 1 << index;
  2608. ohci->ir_context_channels |= 1ULL << base->channel;
  2609. break;
  2610. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2611. index = ctx - ohci->ir_context_list;
  2612. ohci->ir_context_mask |= 1 << index;
  2613. ohci->ir_context_channels |= ohci->mc_channels;
  2614. ohci->mc_channels = 0;
  2615. ohci->mc_allocated = false;
  2616. break;
  2617. }
  2618. spin_unlock_irqrestore(&ohci->lock, flags);
  2619. }
  2620. static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
  2621. {
  2622. struct fw_ohci *ohci = fw_ohci(base->card);
  2623. unsigned long flags;
  2624. int ret;
  2625. switch (base->type) {
  2626. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2627. spin_lock_irqsave(&ohci->lock, flags);
  2628. /* Don't allow multichannel to grab other contexts' channels. */
  2629. if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
  2630. *channels = ohci->ir_context_channels;
  2631. ret = -EBUSY;
  2632. } else {
  2633. set_multichannel_mask(ohci, *channels);
  2634. ret = 0;
  2635. }
  2636. spin_unlock_irqrestore(&ohci->lock, flags);
  2637. break;
  2638. default:
  2639. ret = -EINVAL;
  2640. }
  2641. return ret;
  2642. }
  2643. #ifdef CONFIG_PM
  2644. static void ohci_resume_iso_dma(struct fw_ohci *ohci)
  2645. {
  2646. int i;
  2647. struct iso_context *ctx;
  2648. for (i = 0 ; i < ohci->n_ir ; i++) {
  2649. ctx = &ohci->ir_context_list[i];
  2650. if (ctx->context.running)
  2651. ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
  2652. }
  2653. for (i = 0 ; i < ohci->n_it ; i++) {
  2654. ctx = &ohci->it_context_list[i];
  2655. if (ctx->context.running)
  2656. ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
  2657. }
  2658. }
  2659. #endif
  2660. static int queue_iso_transmit(struct iso_context *ctx,
  2661. struct fw_iso_packet *packet,
  2662. struct fw_iso_buffer *buffer,
  2663. unsigned long payload)
  2664. {
  2665. struct descriptor *d, *last, *pd;
  2666. struct fw_iso_packet *p;
  2667. __le32 *header;
  2668. dma_addr_t d_bus, page_bus;
  2669. u32 z, header_z, payload_z, irq;
  2670. u32 payload_index, payload_end_index, next_page_index;
  2671. int page, end_page, i, length, offset;
  2672. p = packet;
  2673. payload_index = payload;
  2674. if (p->skip)
  2675. z = 1;
  2676. else
  2677. z = 2;
  2678. if (p->header_length > 0)
  2679. z++;
  2680. /* Determine the first page the payload isn't contained in. */
  2681. end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
  2682. if (p->payload_length > 0)
  2683. payload_z = end_page - (payload_index >> PAGE_SHIFT);
  2684. else
  2685. payload_z = 0;
  2686. z += payload_z;
  2687. /* Get header size in number of descriptors. */
  2688. header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
  2689. d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
  2690. if (d == NULL)
  2691. return -ENOMEM;
  2692. if (!p->skip) {
  2693. d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
  2694. d[0].req_count = cpu_to_le16(8);
  2695. /*
  2696. * Link the skip address to this descriptor itself. This causes
  2697. * a context to skip a cycle whenever lost cycles or FIFO
  2698. * overruns occur, without dropping the data. The application
  2699. * should then decide whether this is an error condition or not.
  2700. * FIXME: Make the context's cycle-lost behaviour configurable?
  2701. */
  2702. d[0].branch_address = cpu_to_le32(d_bus | z);
  2703. header = (__le32 *) &d[1];
  2704. header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
  2705. IT_HEADER_TAG(p->tag) |
  2706. IT_HEADER_TCODE(TCODE_STREAM_DATA) |
  2707. IT_HEADER_CHANNEL(ctx->base.channel) |
  2708. IT_HEADER_SPEED(ctx->base.speed));
  2709. header[1] =
  2710. cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
  2711. p->payload_length));
  2712. }
  2713. if (p->header_length > 0) {
  2714. d[2].req_count = cpu_to_le16(p->header_length);
  2715. d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
  2716. memcpy(&d[z], p->header, p->header_length);
  2717. }
  2718. pd = d + z - payload_z;
  2719. payload_end_index = payload_index + p->payload_length;
  2720. for (i = 0; i < payload_z; i++) {
  2721. page = payload_index >> PAGE_SHIFT;
  2722. offset = payload_index & ~PAGE_MASK;
  2723. next_page_index = (page + 1) << PAGE_SHIFT;
  2724. length =
  2725. min(next_page_index, payload_end_index) - payload_index;
  2726. pd[i].req_count = cpu_to_le16(length);
  2727. page_bus = page_private(buffer->pages[page]);
  2728. pd[i].data_address = cpu_to_le32(page_bus + offset);
  2729. dma_sync_single_range_for_device(ctx->context.ohci->card.device,
  2730. page_bus, offset, length,
  2731. DMA_TO_DEVICE);
  2732. payload_index += length;
  2733. }
  2734. if (p->interrupt)
  2735. irq = DESCRIPTOR_IRQ_ALWAYS;
  2736. else
  2737. irq = DESCRIPTOR_NO_IRQ;
  2738. last = z == 2 ? d : d + z - 1;
  2739. last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
  2740. DESCRIPTOR_STATUS |
  2741. DESCRIPTOR_BRANCH_ALWAYS |
  2742. irq);
  2743. context_append(&ctx->context, d, z, header_z);
  2744. return 0;
  2745. }
  2746. static int queue_iso_packet_per_buffer(struct iso_context *ctx,
  2747. struct fw_iso_packet *packet,
  2748. struct fw_iso_buffer *buffer,
  2749. unsigned long payload)
  2750. {
  2751. struct device *device = ctx->context.ohci->card.device;
  2752. struct descriptor *d, *pd;
  2753. dma_addr_t d_bus, page_bus;
  2754. u32 z, header_z, rest;
  2755. int i, j, length;
  2756. int page, offset, packet_count, header_size, payload_per_buffer;
  2757. /*
  2758. * The OHCI controller puts the isochronous header and trailer in the
  2759. * buffer, so we need at least 8 bytes.
  2760. */
  2761. packet_count = packet->header_length / ctx->base.header_size;
  2762. header_size = max(ctx->base.header_size, (size_t)8);
  2763. /* Get header size in number of descriptors. */
  2764. header_z = DIV_ROUND_UP(header_size, sizeof(*d));
  2765. page = payload >> PAGE_SHIFT;
  2766. offset = payload & ~PAGE_MASK;
  2767. payload_per_buffer = packet->payload_length / packet_count;
  2768. for (i = 0; i < packet_count; i++) {
  2769. /* d points to the header descriptor */
  2770. z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
  2771. d = context_get_descriptors(&ctx->context,
  2772. z + header_z, &d_bus);
  2773. if (d == NULL)
  2774. return -ENOMEM;
  2775. d->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2776. DESCRIPTOR_INPUT_MORE);
  2777. if (packet->skip && i == 0)
  2778. d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  2779. d->req_count = cpu_to_le16(header_size);
  2780. d->res_count = d->req_count;
  2781. d->transfer_status = 0;
  2782. d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
  2783. rest = payload_per_buffer;
  2784. pd = d;
  2785. for (j = 1; j < z; j++) {
  2786. pd++;
  2787. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2788. DESCRIPTOR_INPUT_MORE);
  2789. if (offset + rest < PAGE_SIZE)
  2790. length = rest;
  2791. else
  2792. length = PAGE_SIZE - offset;
  2793. pd->req_count = cpu_to_le16(length);
  2794. pd->res_count = pd->req_count;
  2795. pd->transfer_status = 0;
  2796. page_bus = page_private(buffer->pages[page]);
  2797. pd->data_address = cpu_to_le32(page_bus + offset);
  2798. dma_sync_single_range_for_device(device, page_bus,
  2799. offset, length,
  2800. DMA_FROM_DEVICE);
  2801. offset = (offset + length) & ~PAGE_MASK;
  2802. rest -= length;
  2803. if (offset == 0)
  2804. page++;
  2805. }
  2806. pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
  2807. DESCRIPTOR_INPUT_LAST |
  2808. DESCRIPTOR_BRANCH_ALWAYS);
  2809. if (packet->interrupt && i == packet_count - 1)
  2810. pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  2811. context_append(&ctx->context, d, z, header_z);
  2812. }
  2813. return 0;
  2814. }
  2815. static int queue_iso_buffer_fill(struct iso_context *ctx,
  2816. struct fw_iso_packet *packet,
  2817. struct fw_iso_buffer *buffer,
  2818. unsigned long payload)
  2819. {
  2820. struct descriptor *d;
  2821. dma_addr_t d_bus, page_bus;
  2822. int page, offset, rest, z, i, length;
  2823. page = payload >> PAGE_SHIFT;
  2824. offset = payload & ~PAGE_MASK;
  2825. rest = packet->payload_length;
  2826. /* We need one descriptor for each page in the buffer. */
  2827. z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
  2828. if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
  2829. return -EFAULT;
  2830. for (i = 0; i < z; i++) {
  2831. d = context_get_descriptors(&ctx->context, 1, &d_bus);
  2832. if (d == NULL)
  2833. return -ENOMEM;
  2834. d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
  2835. DESCRIPTOR_BRANCH_ALWAYS);
  2836. if (packet->skip && i == 0)
  2837. d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
  2838. if (packet->interrupt && i == z - 1)
  2839. d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
  2840. if (offset + rest < PAGE_SIZE)
  2841. length = rest;
  2842. else
  2843. length = PAGE_SIZE - offset;
  2844. d->req_count = cpu_to_le16(length);
  2845. d->res_count = d->req_count;
  2846. d->transfer_status = 0;
  2847. page_bus = page_private(buffer->pages[page]);
  2848. d->data_address = cpu_to_le32(page_bus + offset);
  2849. dma_sync_single_range_for_device(ctx->context.ohci->card.device,
  2850. page_bus, offset, length,
  2851. DMA_FROM_DEVICE);
  2852. rest -= length;
  2853. offset = 0;
  2854. page++;
  2855. context_append(&ctx->context, d, 1, 0);
  2856. }
  2857. return 0;
  2858. }
  2859. static int ohci_queue_iso(struct fw_iso_context *base,
  2860. struct fw_iso_packet *packet,
  2861. struct fw_iso_buffer *buffer,
  2862. unsigned long payload)
  2863. {
  2864. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2865. unsigned long flags;
  2866. int ret = -ENOSYS;
  2867. spin_lock_irqsave(&ctx->context.ohci->lock, flags);
  2868. switch (base->type) {
  2869. case FW_ISO_CONTEXT_TRANSMIT:
  2870. ret = queue_iso_transmit(ctx, packet, buffer, payload);
  2871. break;
  2872. case FW_ISO_CONTEXT_RECEIVE:
  2873. ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
  2874. break;
  2875. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2876. ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
  2877. break;
  2878. }
  2879. spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
  2880. return ret;
  2881. }
  2882. static void ohci_flush_queue_iso(struct fw_iso_context *base)
  2883. {
  2884. struct context *ctx =
  2885. &container_of(base, struct iso_context, base)->context;
  2886. reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
  2887. }
  2888. static int ohci_flush_iso_completions(struct fw_iso_context *base)
  2889. {
  2890. struct iso_context *ctx = container_of(base, struct iso_context, base);
  2891. int ret = 0;
  2892. tasklet_disable(&ctx->context.tasklet);
  2893. if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
  2894. context_tasklet((unsigned long)&ctx->context);
  2895. switch (base->type) {
  2896. case FW_ISO_CONTEXT_TRANSMIT:
  2897. case FW_ISO_CONTEXT_RECEIVE:
  2898. if (ctx->header_length != 0)
  2899. flush_iso_completions(ctx);
  2900. break;
  2901. case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
  2902. if (ctx->mc_completed != 0)
  2903. flush_ir_buffer_fill(ctx);
  2904. break;
  2905. default:
  2906. ret = -ENOSYS;
  2907. }
  2908. clear_bit_unlock(0, &ctx->flushing_completions);
  2909. smp_mb__after_atomic();
  2910. }
  2911. tasklet_enable(&ctx->context.tasklet);
  2912. return ret;
  2913. }
  2914. static const struct fw_card_driver ohci_driver = {
  2915. .enable = ohci_enable,
  2916. .read_phy_reg = ohci_read_phy_reg,
  2917. .update_phy_reg = ohci_update_phy_reg,
  2918. .set_config_rom = ohci_set_config_rom,
  2919. .send_request = ohci_send_request,
  2920. .send_response = ohci_send_response,
  2921. .cancel_packet = ohci_cancel_packet,
  2922. .enable_phys_dma = ohci_enable_phys_dma,
  2923. .read_csr = ohci_read_csr,
  2924. .write_csr = ohci_write_csr,
  2925. .allocate_iso_context = ohci_allocate_iso_context,
  2926. .free_iso_context = ohci_free_iso_context,
  2927. .set_iso_channels = ohci_set_iso_channels,
  2928. .queue_iso = ohci_queue_iso,
  2929. .flush_queue_iso = ohci_flush_queue_iso,
  2930. .flush_iso_completions = ohci_flush_iso_completions,
  2931. .start_iso = ohci_start_iso,
  2932. .stop_iso = ohci_stop_iso,
  2933. };
  2934. #ifdef CONFIG_PPC_PMAC
  2935. static void pmac_ohci_on(struct pci_dev *dev)
  2936. {
  2937. if (machine_is(powermac)) {
  2938. struct device_node *ofn = pci_device_to_OF_node(dev);
  2939. if (ofn) {
  2940. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
  2941. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
  2942. }
  2943. }
  2944. }
  2945. static void pmac_ohci_off(struct pci_dev *dev)
  2946. {
  2947. if (machine_is(powermac)) {
  2948. struct device_node *ofn = pci_device_to_OF_node(dev);
  2949. if (ofn) {
  2950. pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
  2951. pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
  2952. }
  2953. }
  2954. }
  2955. #else
  2956. static inline void pmac_ohci_on(struct pci_dev *dev) {}
  2957. static inline void pmac_ohci_off(struct pci_dev *dev) {}
  2958. #endif /* CONFIG_PPC_PMAC */
  2959. static int pci_probe(struct pci_dev *dev,
  2960. const struct pci_device_id *ent)
  2961. {
  2962. struct fw_ohci *ohci;
  2963. u32 bus_options, max_receive, link_speed, version;
  2964. u64 guid;
  2965. int i, err;
  2966. size_t size;
  2967. if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
  2968. dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
  2969. return -ENOSYS;
  2970. }
  2971. ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
  2972. if (ohci == NULL) {
  2973. err = -ENOMEM;
  2974. goto fail;
  2975. }
  2976. fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
  2977. pmac_ohci_on(dev);
  2978. err = pci_enable_device(dev);
  2979. if (err) {
  2980. dev_err(&dev->dev, "failed to enable OHCI hardware\n");
  2981. goto fail_free;
  2982. }
  2983. pci_set_master(dev);
  2984. pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
  2985. pci_set_drvdata(dev, ohci);
  2986. spin_lock_init(&ohci->lock);
  2987. mutex_init(&ohci->phy_reg_mutex);
  2988. INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
  2989. if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
  2990. pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
  2991. ohci_err(ohci, "invalid MMIO resource\n");
  2992. err = -ENXIO;
  2993. goto fail_disable;
  2994. }
  2995. err = pci_request_region(dev, 0, ohci_driver_name);
  2996. if (err) {
  2997. ohci_err(ohci, "MMIO resource unavailable\n");
  2998. goto fail_disable;
  2999. }
  3000. ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
  3001. if (ohci->registers == NULL) {
  3002. ohci_err(ohci, "failed to remap registers\n");
  3003. err = -ENXIO;
  3004. goto fail_iomem;
  3005. }
  3006. for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
  3007. if ((ohci_quirks[i].vendor == dev->vendor) &&
  3008. (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
  3009. ohci_quirks[i].device == dev->device) &&
  3010. (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
  3011. ohci_quirks[i].revision >= dev->revision)) {
  3012. ohci->quirks = ohci_quirks[i].flags;
  3013. break;
  3014. }
  3015. if (param_quirks)
  3016. ohci->quirks = param_quirks;
  3017. /*
  3018. * Because dma_alloc_coherent() allocates at least one page,
  3019. * we save space by using a common buffer for the AR request/
  3020. * response descriptors and the self IDs buffer.
  3021. */
  3022. BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
  3023. BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
  3024. ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
  3025. PAGE_SIZE,
  3026. &ohci->misc_buffer_bus,
  3027. GFP_KERNEL);
  3028. if (!ohci->misc_buffer) {
  3029. err = -ENOMEM;
  3030. goto fail_iounmap;
  3031. }
  3032. err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
  3033. OHCI1394_AsReqRcvContextControlSet);
  3034. if (err < 0)
  3035. goto fail_misc_buf;
  3036. err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
  3037. OHCI1394_AsRspRcvContextControlSet);
  3038. if (err < 0)
  3039. goto fail_arreq_ctx;
  3040. err = context_init(&ohci->at_request_ctx, ohci,
  3041. OHCI1394_AsReqTrContextControlSet, handle_at_packet);
  3042. if (err < 0)
  3043. goto fail_arrsp_ctx;
  3044. err = context_init(&ohci->at_response_ctx, ohci,
  3045. OHCI1394_AsRspTrContextControlSet, handle_at_packet);
  3046. if (err < 0)
  3047. goto fail_atreq_ctx;
  3048. reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
  3049. ohci->ir_context_channels = ~0ULL;
  3050. ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
  3051. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
  3052. ohci->ir_context_mask = ohci->ir_context_support;
  3053. ohci->n_ir = hweight32(ohci->ir_context_mask);
  3054. size = sizeof(struct iso_context) * ohci->n_ir;
  3055. ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
  3056. reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
  3057. ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
  3058. /* JMicron JMB38x often shows 0 at first read, just ignore it */
  3059. if (!ohci->it_context_support) {
  3060. ohci_notice(ohci, "overriding IsoXmitIntMask\n");
  3061. ohci->it_context_support = 0xf;
  3062. }
  3063. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
  3064. ohci->it_context_mask = ohci->it_context_support;
  3065. ohci->n_it = hweight32(ohci->it_context_mask);
  3066. size = sizeof(struct iso_context) * ohci->n_it;
  3067. ohci->it_context_list = kzalloc(size, GFP_KERNEL);
  3068. if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
  3069. err = -ENOMEM;
  3070. goto fail_contexts;
  3071. }
  3072. ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
  3073. ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
  3074. bus_options = reg_read(ohci, OHCI1394_BusOptions);
  3075. max_receive = (bus_options >> 12) & 0xf;
  3076. link_speed = bus_options & 0x7;
  3077. guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
  3078. reg_read(ohci, OHCI1394_GUIDLo);
  3079. if (!(ohci->quirks & QUIRK_NO_MSI))
  3080. pci_enable_msi(dev);
  3081. if (request_irq(dev->irq, irq_handler,
  3082. pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
  3083. ohci_driver_name, ohci)) {
  3084. ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
  3085. err = -EIO;
  3086. goto fail_msi;
  3087. }
  3088. err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
  3089. if (err)
  3090. goto fail_irq;
  3091. version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
  3092. ohci_notice(ohci,
  3093. "added OHCI v%x.%x device as card %d, "
  3094. "%d IR + %d IT contexts, quirks 0x%x%s\n",
  3095. version >> 16, version & 0xff, ohci->card.index,
  3096. ohci->n_ir, ohci->n_it, ohci->quirks,
  3097. reg_read(ohci, OHCI1394_PhyUpperBound) ?
  3098. ", physUB" : "");
  3099. return 0;
  3100. fail_irq:
  3101. free_irq(dev->irq, ohci);
  3102. fail_msi:
  3103. pci_disable_msi(dev);
  3104. fail_contexts:
  3105. kfree(ohci->ir_context_list);
  3106. kfree(ohci->it_context_list);
  3107. context_release(&ohci->at_response_ctx);
  3108. fail_atreq_ctx:
  3109. context_release(&ohci->at_request_ctx);
  3110. fail_arrsp_ctx:
  3111. ar_context_release(&ohci->ar_response_ctx);
  3112. fail_arreq_ctx:
  3113. ar_context_release(&ohci->ar_request_ctx);
  3114. fail_misc_buf:
  3115. dma_free_coherent(ohci->card.device, PAGE_SIZE,
  3116. ohci->misc_buffer, ohci->misc_buffer_bus);
  3117. fail_iounmap:
  3118. pci_iounmap(dev, ohci->registers);
  3119. fail_iomem:
  3120. pci_release_region(dev, 0);
  3121. fail_disable:
  3122. pci_disable_device(dev);
  3123. fail_free:
  3124. kfree(ohci);
  3125. pmac_ohci_off(dev);
  3126. fail:
  3127. return err;
  3128. }
  3129. static void pci_remove(struct pci_dev *dev)
  3130. {
  3131. struct fw_ohci *ohci = pci_get_drvdata(dev);
  3132. /*
  3133. * If the removal is happening from the suspend state, LPS won't be
  3134. * enabled and host registers (eg., IntMaskClear) won't be accessible.
  3135. */
  3136. if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
  3137. reg_write(ohci, OHCI1394_IntMaskClear, ~0);
  3138. flush_writes(ohci);
  3139. }
  3140. cancel_work_sync(&ohci->bus_reset_work);
  3141. fw_core_remove_card(&ohci->card);
  3142. /*
  3143. * FIXME: Fail all pending packets here, now that the upper
  3144. * layers can't queue any more.
  3145. */
  3146. software_reset(ohci);
  3147. free_irq(dev->irq, ohci);
  3148. if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
  3149. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  3150. ohci->next_config_rom, ohci->next_config_rom_bus);
  3151. if (ohci->config_rom)
  3152. dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
  3153. ohci->config_rom, ohci->config_rom_bus);
  3154. ar_context_release(&ohci->ar_request_ctx);
  3155. ar_context_release(&ohci->ar_response_ctx);
  3156. dma_free_coherent(ohci->card.device, PAGE_SIZE,
  3157. ohci->misc_buffer, ohci->misc_buffer_bus);
  3158. context_release(&ohci->at_request_ctx);
  3159. context_release(&ohci->at_response_ctx);
  3160. kfree(ohci->it_context_list);
  3161. kfree(ohci->ir_context_list);
  3162. pci_disable_msi(dev);
  3163. pci_iounmap(dev, ohci->registers);
  3164. pci_release_region(dev, 0);
  3165. pci_disable_device(dev);
  3166. kfree(ohci);
  3167. pmac_ohci_off(dev);
  3168. dev_notice(&dev->dev, "removed fw-ohci device\n");
  3169. }
  3170. #ifdef CONFIG_PM
  3171. static int pci_suspend(struct pci_dev *dev, pm_message_t state)
  3172. {
  3173. struct fw_ohci *ohci = pci_get_drvdata(dev);
  3174. int err;
  3175. software_reset(ohci);
  3176. err = pci_save_state(dev);
  3177. if (err) {
  3178. ohci_err(ohci, "pci_save_state failed\n");
  3179. return err;
  3180. }
  3181. err = pci_set_power_state(dev, pci_choose_state(dev, state));
  3182. if (err)
  3183. ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
  3184. pmac_ohci_off(dev);
  3185. return 0;
  3186. }
  3187. static int pci_resume(struct pci_dev *dev)
  3188. {
  3189. struct fw_ohci *ohci = pci_get_drvdata(dev);
  3190. int err;
  3191. pmac_ohci_on(dev);
  3192. pci_set_power_state(dev, PCI_D0);
  3193. pci_restore_state(dev);
  3194. err = pci_enable_device(dev);
  3195. if (err) {
  3196. ohci_err(ohci, "pci_enable_device failed\n");
  3197. return err;
  3198. }
  3199. /* Some systems don't setup GUID register on resume from ram */
  3200. if (!reg_read(ohci, OHCI1394_GUIDLo) &&
  3201. !reg_read(ohci, OHCI1394_GUIDHi)) {
  3202. reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
  3203. reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
  3204. }
  3205. err = ohci_enable(&ohci->card, NULL, 0);
  3206. if (err)
  3207. return err;
  3208. ohci_resume_iso_dma(ohci);
  3209. return 0;
  3210. }
  3211. #endif
  3212. static const struct pci_device_id pci_table[] = {
  3213. { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
  3214. { }
  3215. };
  3216. MODULE_DEVICE_TABLE(pci, pci_table);
  3217. static struct pci_driver fw_ohci_pci_driver = {
  3218. .name = ohci_driver_name,
  3219. .id_table = pci_table,
  3220. .probe = pci_probe,
  3221. .remove = pci_remove,
  3222. #ifdef CONFIG_PM
  3223. .resume = pci_resume,
  3224. .suspend = pci_suspend,
  3225. #endif
  3226. };
  3227. static int __init fw_ohci_init(void)
  3228. {
  3229. selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
  3230. if (!selfid_workqueue)
  3231. return -ENOMEM;
  3232. return pci_register_driver(&fw_ohci_pci_driver);
  3233. }
  3234. static void __exit fw_ohci_cleanup(void)
  3235. {
  3236. pci_unregister_driver(&fw_ohci_pci_driver);
  3237. destroy_workqueue(selfid_workqueue);
  3238. }
  3239. module_init(fw_ohci_init);
  3240. module_exit(fw_ohci_cleanup);
  3241. MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
  3242. MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
  3243. MODULE_LICENSE("GPL");
  3244. /* Provide a module alias so root-on-sbp2 initrds don't break. */
  3245. MODULE_ALIAS("ohci1394");