init_ohci1394_dma.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * init_ohci1394_dma.c - Initializes physical DMA on all OHCI 1394 controllers
  4. *
  5. * Copyright (C) 2006-2007 Bernhard Kaindl <bk@suse.de>
  6. *
  7. * Derived from drivers/ieee1394/ohci1394.c and arch/x86/kernel/early-quirks.c
  8. * this file has functions to:
  9. * - scan the PCI very early on boot for all OHCI 1394-compliant controllers
  10. * - reset and initialize them and make them join the IEEE1394 bus and
  11. * - enable physical DMA on them to allow remote debugging
  12. *
  13. * All code and data is marked as __init and __initdata, respective as
  14. * during boot, all OHCI1394 controllers may be claimed by the firewire
  15. * stack and at this point, this code should not touch them anymore.
  16. *
  17. * To use physical DMA after the initialization of the firewire stack,
  18. * be sure that the stack enables it and (re-)attach after the bus reset
  19. * which may be caused by the firewire stack initialization.
  20. */
  21. #include <linux/delay.h>
  22. #include <linux/io.h>
  23. #include <linux/kernel.h>
  24. #include <linux/pci.h> /* for PCI defines */
  25. #include <linux/string.h>
  26. #include <asm/pci-direct.h> /* for direct PCI config space access */
  27. #include <asm/fixmap.h>
  28. #include <linux/init_ohci1394_dma.h>
  29. #include "ohci.h"
  30. int __initdata init_ohci1394_dma_early;
  31. struct ohci {
  32. void __iomem *registers;
  33. };
  34. static inline void reg_write(const struct ohci *ohci, int offset, u32 data)
  35. {
  36. writel(data, ohci->registers + offset);
  37. }
  38. static inline u32 reg_read(const struct ohci *ohci, int offset)
  39. {
  40. return readl(ohci->registers + offset);
  41. }
  42. #define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */
  43. /* Reads a PHY register of an OHCI-1394 controller */
  44. static inline u8 __init get_phy_reg(struct ohci *ohci, u8 addr)
  45. {
  46. int i;
  47. u32 r;
  48. reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000);
  49. for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  50. if (reg_read(ohci, OHCI1394_PhyControl) & 0x80000000)
  51. break;
  52. mdelay(1);
  53. }
  54. r = reg_read(ohci, OHCI1394_PhyControl);
  55. return (r & 0x00ff0000) >> 16;
  56. }
  57. /* Writes to a PHY register of an OHCI-1394 controller */
  58. static inline void __init set_phy_reg(struct ohci *ohci, u8 addr, u8 data)
  59. {
  60. int i;
  61. reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000);
  62. for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  63. if (!(reg_read(ohci, OHCI1394_PhyControl) & 0x00004000))
  64. break;
  65. mdelay(1);
  66. }
  67. }
  68. /* Resets an OHCI-1394 controller (for sane state before initialization) */
  69. static inline void __init init_ohci1394_soft_reset(struct ohci *ohci)
  70. {
  71. int i;
  72. reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
  73. for (i = 0; i < OHCI_LOOP_COUNT; i++) {
  74. if (!(reg_read(ohci, OHCI1394_HCControlSet)
  75. & OHCI1394_HCControl_softReset))
  76. break;
  77. mdelay(1);
  78. }
  79. }
  80. #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
  81. #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
  82. #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
  83. /* Basic OHCI-1394 register and port inititalization */
  84. static inline void __init init_ohci1394_initialize(struct ohci *ohci)
  85. {
  86. u32 bus_options;
  87. int num_ports, i;
  88. /* Put some defaults to these undefined bus options */
  89. bus_options = reg_read(ohci, OHCI1394_BusOptions);
  90. bus_options |= 0x60000000; /* Enable CMC and ISC */
  91. bus_options &= ~0x00ff0000; /* XXX: Set cyc_clk_acc to zero for now */
  92. bus_options &= ~0x18000000; /* Disable PMC and BMC */
  93. reg_write(ohci, OHCI1394_BusOptions, bus_options);
  94. /* Set the bus number */
  95. reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0);
  96. /* Enable posted writes */
  97. reg_write(ohci, OHCI1394_HCControlSet,
  98. OHCI1394_HCControl_postedWriteEnable);
  99. /* Clear link control register */
  100. reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff);
  101. /* enable phys */
  102. reg_write(ohci, OHCI1394_LinkControlSet,
  103. OHCI1394_LinkControl_rcvPhyPkt);
  104. /* Don't accept phy packets into AR request context */
  105. reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400);
  106. /* Clear the Isochonouys interrupt masks */
  107. reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 0xffffffff);
  108. reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 0xffffffff);
  109. reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 0xffffffff);
  110. reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 0xffffffff);
  111. /* Accept asynchronous transfer requests from all nodes for now */
  112. reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
  113. /* Specify asynchronous transfer retries */
  114. reg_write(ohci, OHCI1394_ATRetries,
  115. OHCI1394_MAX_AT_REQ_RETRIES |
  116. (OHCI1394_MAX_AT_RESP_RETRIES<<4) |
  117. (OHCI1394_MAX_PHYS_RESP_RETRIES<<8));
  118. /* We don't want hardware swapping */
  119. reg_write(ohci, OHCI1394_HCControlClear,
  120. OHCI1394_HCControl_noByteSwapData);
  121. /* Enable link */
  122. reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_linkEnable);
  123. /* If anything is connected to a port, make sure it is enabled */
  124. num_ports = get_phy_reg(ohci, 2) & 0xf;
  125. for (i = 0; i < num_ports; i++) {
  126. unsigned int status;
  127. set_phy_reg(ohci, 7, i);
  128. status = get_phy_reg(ohci, 8);
  129. if (status & 0x20)
  130. set_phy_reg(ohci, 8, status & ~1);
  131. }
  132. }
  133. /**
  134. * init_ohci1394_wait_for_busresets - wait until bus resets are completed
  135. *
  136. * OHCI1394 initialization itself and any device going on- or offline
  137. * and any cable issue cause a IEEE1394 bus reset. The OHCI1394 spec
  138. * specifies that physical DMA is disabled on each bus reset and it
  139. * has to be enabled after each bus reset when needed. We resort
  140. * to polling here because on early boot, we have no interrupts.
  141. */
  142. static inline void __init init_ohci1394_wait_for_busresets(struct ohci *ohci)
  143. {
  144. int i, events;
  145. for (i = 0; i < 9; i++) {
  146. mdelay(200);
  147. events = reg_read(ohci, OHCI1394_IntEventSet);
  148. if (events & OHCI1394_busReset)
  149. reg_write(ohci, OHCI1394_IntEventClear,
  150. OHCI1394_busReset);
  151. }
  152. }
  153. /**
  154. * init_ohci1394_enable_physical_dma - Enable physical DMA for remote debugging
  155. * This enables remote DMA access over IEEE1394 from every host for the low
  156. * 4GB of address space. DMA accesses above 4GB are not available currently.
  157. */
  158. static inline void __init init_ohci1394_enable_physical_dma(struct ohci *ohci)
  159. {
  160. reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 0xffffffff);
  161. reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 0xffffffff);
  162. reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000);
  163. }
  164. /**
  165. * init_ohci1394_reset_and_init_dma - init controller and enable DMA
  166. * This initializes the given controller and enables physical DMA engine in it.
  167. */
  168. static inline void __init init_ohci1394_reset_and_init_dma(struct ohci *ohci)
  169. {
  170. /* Start off with a soft reset, clears everything to a sane state. */
  171. init_ohci1394_soft_reset(ohci);
  172. /* Accessing some registers without LPS enabled may cause lock up */
  173. reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_LPS);
  174. /* Disable and clear interrupts */
  175. reg_write(ohci, OHCI1394_IntEventClear, 0xffffffff);
  176. reg_write(ohci, OHCI1394_IntMaskClear, 0xffffffff);
  177. mdelay(50); /* Wait 50msec to make sure we have full link enabled */
  178. init_ohci1394_initialize(ohci);
  179. /*
  180. * The initialization causes at least one IEEE1394 bus reset. Enabling
  181. * physical DMA only works *after* *all* bus resets have calmed down:
  182. */
  183. init_ohci1394_wait_for_busresets(ohci);
  184. /* We had to wait and do this now if we want to debug early problems */
  185. init_ohci1394_enable_physical_dma(ohci);
  186. }
  187. /**
  188. * init_ohci1394_controller - Map the registers of the controller and init DMA
  189. * This maps the registers of the specified controller and initializes it
  190. */
  191. static inline void __init init_ohci1394_controller(int num, int slot, int func)
  192. {
  193. unsigned long ohci_base;
  194. struct ohci ohci;
  195. printk(KERN_INFO "init_ohci1394_dma: initializing OHCI-1394"
  196. " at %02x:%02x.%x\n", num, slot, func);
  197. ohci_base = read_pci_config(num, slot, func, PCI_BASE_ADDRESS_0+(0<<2))
  198. & PCI_BASE_ADDRESS_MEM_MASK;
  199. set_fixmap_nocache(FIX_OHCI1394_BASE, ohci_base);
  200. ohci.registers = (void __iomem *)fix_to_virt(FIX_OHCI1394_BASE);
  201. init_ohci1394_reset_and_init_dma(&ohci);
  202. }
  203. /**
  204. * debug_init_ohci1394_dma - scan for OHCI1394 controllers and init DMA on them
  205. * Scans the whole PCI space for OHCI1394 controllers and inits DMA on them
  206. */
  207. void __init init_ohci1394_dma_on_all_controllers(void)
  208. {
  209. int num, slot, func;
  210. u32 class;
  211. if (!early_pci_allowed())
  212. return;
  213. /* Poor man's PCI discovery, the only thing we can do at early boot */
  214. for (num = 0; num < 32; num++) {
  215. for (slot = 0; slot < 32; slot++) {
  216. for (func = 0; func < 8; func++) {
  217. class = read_pci_config(num, slot, func,
  218. PCI_CLASS_REVISION);
  219. if (class == 0xffffffff)
  220. continue; /* No device at this func */
  221. if (class>>8 != PCI_CLASS_SERIAL_FIREWIRE_OHCI)
  222. continue; /* Not an OHCI-1394 device */
  223. init_ohci1394_controller(num, slot, func);
  224. break; /* Assume one controller per device */
  225. }
  226. }
  227. }
  228. printk(KERN_INFO "init_ohci1394_dma: finished initializing OHCI DMA\n");
  229. }
  230. /**
  231. * setup_init_ohci1394_early - enables early OHCI1394 DMA initialization
  232. */
  233. static int __init setup_ohci1394_dma(char *opt)
  234. {
  235. if (!strcmp(opt, "early"))
  236. init_ohci1394_dma_early = 1;
  237. return 0;
  238. }
  239. /* passing ohci1394_dma=early on boot causes early OHCI1394 DMA initialization */
  240. early_param("ohci1394_dma", setup_ohci1394_dma);