extcon-rt8973a.h 7.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /*
  3. * rt8973a.h
  4. *
  5. * Copyright (c) 2014 Samsung Electronics Co., Ltd
  6. */
  7. #ifndef __LINUX_EXTCON_RT8973A_H
  8. #define __LINUX_EXTCON_RT8973A_H
  9. enum rt8973a_types {
  10. TYPE_RT8973A,
  11. };
  12. /* RT8973A registers */
  13. enum rt8973A_reg {
  14. RT8973A_REG_DEVICE_ID = 0x1,
  15. RT8973A_REG_CONTROL1,
  16. RT8973A_REG_INT1,
  17. RT8973A_REG_INT2,
  18. RT8973A_REG_INTM1,
  19. RT8973A_REG_INTM2,
  20. RT8973A_REG_ADC,
  21. RT8973A_REG_RSVD_1,
  22. RT8973A_REG_RSVD_2,
  23. RT8973A_REG_DEV1,
  24. RT8973A_REG_DEV2,
  25. RT8973A_REG_RSVD_3,
  26. RT8973A_REG_RSVD_4,
  27. RT8973A_REG_RSVD_5,
  28. RT8973A_REG_RSVD_6,
  29. RT8973A_REG_RSVD_7,
  30. RT8973A_REG_RSVD_8,
  31. RT8973A_REG_RSVD_9,
  32. RT8973A_REG_MANUAL_SW1,
  33. RT8973A_REG_MANUAL_SW2,
  34. RT8973A_REG_RSVD_10,
  35. RT8973A_REG_RSVD_11,
  36. RT8973A_REG_RSVD_12,
  37. RT8973A_REG_RSVD_13,
  38. RT8973A_REG_RSVD_14,
  39. RT8973A_REG_RSVD_15,
  40. RT8973A_REG_RESET,
  41. RT8973A_REG_END,
  42. };
  43. /* Define RT8973A MASK/SHIFT constant */
  44. #define RT8973A_REG_DEVICE_ID_VENDOR_SHIFT 0
  45. #define RT8973A_REG_DEVICE_ID_VERSION_SHIFT 3
  46. #define RT8973A_REG_DEVICE_ID_VENDOR_MASK (0x7 << RT8973A_REG_DEVICE_ID_VENDOR_SHIFT)
  47. #define RT8973A_REG_DEVICE_ID_VERSION_MASK (0x1f << RT8973A_REG_DEVICE_ID_VERSION_SHIFT)
  48. #define RT8973A_REG_CONTROL1_INTM_SHIFT 0
  49. #define RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT 2
  50. #define RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT 3
  51. #define RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT 4
  52. #define RT8973A_REG_CONTROL1_CHGTYP_SHIFT 5
  53. #define RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT 6
  54. #define RT8973A_REG_CONTROL1_ADC_EN_SHIFT 7
  55. #define RT8973A_REG_CONTROL1_INTM_MASK (0x1 << RT8973A_REG_CONTROL1_INTM_SHIFT)
  56. #define RT8973A_REG_CONTROL1_AUTO_CONFIG_MASK (0x1 << RT8973A_REG_CONTROL1_AUTO_CONFIG_SHIFT)
  57. #define RT8973A_REG_CONTROL1_I2C_RST_EN_MASK (0x1 << RT8973A_REG_CONTROL1_I2C_RST_EN_SHIFT)
  58. #define RT8973A_REG_CONTROL1_SWITCH_OPEN_MASK (0x1 << RT8973A_REG_CONTROL1_SWITCH_OPEN_SHIFT)
  59. #define RT8973A_REG_CONTROL1_CHGTYP_MASK (0x1 << RT8973A_REG_CONTROL1_CHGTYP_SHIFT)
  60. #define RT8973A_REG_CONTROL1_USB_CHD_EN_MASK (0x1 << RT8973A_REG_CONTROL1_USB_CHD_EN_SHIFT)
  61. #define RT8973A_REG_CONTROL1_ADC_EN_MASK (0x1 << RT8973A_REG_CONTROL1_ADC_EN_SHIFT)
  62. #define RT9873A_REG_INTM1_ATTACH_SHIFT 0
  63. #define RT9873A_REG_INTM1_DETACH_SHIFT 1
  64. #define RT9873A_REG_INTM1_CHGDET_SHIFT 2
  65. #define RT9873A_REG_INTM1_DCD_T_SHIFT 3
  66. #define RT9873A_REG_INTM1_OVP_SHIFT 4
  67. #define RT9873A_REG_INTM1_CONNECT_SHIFT 5
  68. #define RT9873A_REG_INTM1_ADC_CHG_SHIFT 6
  69. #define RT9873A_REG_INTM1_OTP_SHIFT 7
  70. #define RT9873A_REG_INTM1_ATTACH_MASK (0x1 << RT9873A_REG_INTM1_ATTACH_SHIFT)
  71. #define RT9873A_REG_INTM1_DETACH_MASK (0x1 << RT9873A_REG_INTM1_DETACH_SHIFT)
  72. #define RT9873A_REG_INTM1_CHGDET_MASK (0x1 << RT9873A_REG_INTM1_CHGDET_SHIFT)
  73. #define RT9873A_REG_INTM1_DCD_T_MASK (0x1 << RT9873A_REG_INTM1_DCD_T_SHIFT)
  74. #define RT9873A_REG_INTM1_OVP_MASK (0x1 << RT9873A_REG_INTM1_OVP_SHIFT)
  75. #define RT9873A_REG_INTM1_CONNECT_MASK (0x1 << RT9873A_REG_INTM1_CONNECT_SHIFT)
  76. #define RT9873A_REG_INTM1_ADC_CHG_MASK (0x1 << RT9873A_REG_INTM1_ADC_CHG_SHIFT)
  77. #define RT9873A_REG_INTM1_OTP_MASK (0x1 << RT9873A_REG_INTM1_OTP_SHIFT)
  78. #define RT9873A_REG_INTM2_UVLO_SHIFT 1
  79. #define RT9873A_REG_INTM2_POR_SHIFT 2
  80. #define RT9873A_REG_INTM2_OTP_FET_SHIFT 3
  81. #define RT9873A_REG_INTM2_OVP_FET_SHIFT 4
  82. #define RT9873A_REG_INTM2_OCP_LATCH_SHIFT 5
  83. #define RT9873A_REG_INTM2_OCP_SHIFT 6
  84. #define RT9873A_REG_INTM2_OVP_OCP_SHIFT 7
  85. #define RT9873A_REG_INTM2_UVLO_MASK (0x1 << RT9873A_REG_INTM2_UVLO_SHIFT)
  86. #define RT9873A_REG_INTM2_POR_MASK (0x1 << RT9873A_REG_INTM2_POR_SHIFT)
  87. #define RT9873A_REG_INTM2_OTP_FET_MASK (0x1 << RT9873A_REG_INTM2_OTP_FET_SHIFT)
  88. #define RT9873A_REG_INTM2_OVP_FET_MASK (0x1 << RT9873A_REG_INTM2_OVP_FET_SHIFT)
  89. #define RT9873A_REG_INTM2_OCP_LATCH_MASK (0x1 << RT9873A_REG_INTM2_OCP_LATCH_SHIFT)
  90. #define RT9873A_REG_INTM2_OCP_MASK (0x1 << RT9873A_REG_INTM2_OCP_SHIFT)
  91. #define RT9873A_REG_INTM2_OVP_OCP_MASK (0x1 << RT9873A_REG_INTM2_OVP_OCP_SHIFT)
  92. #define RT8973A_REG_ADC_SHIFT 0
  93. #define RT8973A_REG_ADC_MASK (0x1f << RT8973A_REG_ADC_SHIFT)
  94. #define RT8973A_REG_DEV1_OTG_SHIFT 0
  95. #define RT8973A_REG_DEV1_SDP_SHIFT 2
  96. #define RT8973A_REG_DEV1_UART_SHIFT 3
  97. #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT 4
  98. #define RT8973A_REG_DEV1_CDPORT_SHIFT 5
  99. #define RT8973A_REG_DEV1_DCPORT_SHIFT 6
  100. #define RT8973A_REG_DEV1_OTG_MASK (0x1 << RT8973A_REG_DEV1_OTG_SHIFT)
  101. #define RT8973A_REG_DEV1_SDP_MASK (0x1 << RT8973A_REG_DEV1_SDP_SHIFT)
  102. #define RT8973A_REG_DEV1_UART_MASK (0x1 << RT8973A_REG_DEV1_UART_SHIFT)
  103. #define RT8973A_REG_DEV1_CAR_KIT_TYPE1_MASK (0x1 << RT8973A_REG_DEV1_CAR_KIT_TYPE1_SHIFT)
  104. #define RT8973A_REG_DEV1_CDPORT_MASK (0x1 << RT8973A_REG_DEV1_CDPORT_SHIFT)
  105. #define RT8973A_REG_DEV1_DCPORT_MASK (0x1 << RT8973A_REG_DEV1_DCPORT_SHIFT)
  106. #define RT8973A_REG_DEV1_USB_MASK (RT8973A_REG_DEV1_SDP_MASK \
  107. | RT8973A_REG_DEV1_CDPORT_MASK)
  108. #define RT8973A_REG_DEV2_JIG_USB_ON_SHIFT 0
  109. #define RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT 1
  110. #define RT8973A_REG_DEV2_JIG_UART_ON_SHIFT 2
  111. #define RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT 3
  112. #define RT8973A_REG_DEV2_JIG_USB_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_ON_SHIFT)
  113. #define RT8973A_REG_DEV2_JIG_USB_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_USB_OFF_SHIFT)
  114. #define RT8973A_REG_DEV2_JIG_UART_ON_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_ON_SHIFT)
  115. #define RT8973A_REG_DEV2_JIG_UART_OFF_MASK (0x1 << RT8973A_REG_DEV2_JIG_UART_OFF_SHIFT)
  116. #define RT8973A_REG_MANUAL_SW1_DP_SHIFT 2
  117. #define RT8973A_REG_MANUAL_SW1_DM_SHIFT 5
  118. #define RT8973A_REG_MANUAL_SW1_DP_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DP_SHIFT)
  119. #define RT8973A_REG_MANUAL_SW1_DM_MASK (0x7 << RT8973A_REG_MANUAL_SW1_DM_SHIFT)
  120. #define DM_DP_CON_SWITCH_OPEN 0x0
  121. #define DM_DP_CON_SWITCH_USB 0x1
  122. #define DM_DP_CON_SWITCH_UART 0x3
  123. #define DM_DP_SWITCH_OPEN ((DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
  124. | (DM_DP_CON_SWITCH_OPEN << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
  125. #define DM_DP_SWITCH_USB ((DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
  126. | (DM_DP_CON_SWITCH_USB << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
  127. #define DM_DP_SWITCH_UART ((DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DP_SHIFT) \
  128. | (DM_DP_CON_SWITCH_UART << RT8973A_REG_MANUAL_SW1_DM_SHIFT))
  129. #define RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT 0
  130. #define RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT 2
  131. #define RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT 3
  132. #define RT8973A_REG_MANUAL_SW2_FET_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_FET_ON_SHIFT)
  133. #define RT8973A_REG_MANUAL_SW2_JIG_ON_MASK (0x1 << RT8973A_REG_MANUAL_SW2_JIG_ON_SHIFT)
  134. #define RT8973A_REG_MANUAL_SW2_BOOT_SW_MASK (0x1 << RT8973A_REG_MANUAL_SW2_BOOT_SW_SHIFT)
  135. #define RT8973A_REG_MANUAL_SW2_FET_ON 0
  136. #define RT8973A_REG_MANUAL_SW2_FET_OFF 0x1
  137. #define RT8973A_REG_MANUAL_SW2_JIG_OFF 0
  138. #define RT8973A_REG_MANUAL_SW2_JIG_ON 0x1
  139. #define RT8973A_REG_MANUAL_SW2_BOOT_SW_ON 0
  140. #define RT8973A_REG_MANUAL_SW2_BOOT_SW_OFF 0x1
  141. #define RT8973A_REG_RESET_SHIFT 0
  142. #define RT8973A_REG_RESET_MASK (0x1 << RT8973A_REG_RESET_SHIFT)
  143. #define RT8973A_REG_RESET 0x1
  144. /* RT8973A Interrupts */
  145. enum rt8973a_irq {
  146. /* Interrupt1*/
  147. RT8973A_INT1_ATTACH,
  148. RT8973A_INT1_DETACH,
  149. RT8973A_INT1_CHGDET,
  150. RT8973A_INT1_DCD_T,
  151. RT8973A_INT1_OVP,
  152. RT8973A_INT1_CONNECT,
  153. RT8973A_INT1_ADC_CHG,
  154. RT8973A_INT1_OTP,
  155. /* Interrupt2*/
  156. RT8973A_INT2_UVLO,
  157. RT8973A_INT2_POR,
  158. RT8973A_INT2_OTP_FET,
  159. RT8973A_INT2_OVP_FET,
  160. RT8973A_INT2_OCP_LATCH,
  161. RT8973A_INT2_OCP,
  162. RT8973A_INT2_OVP_OCP,
  163. RT8973A_NUM,
  164. };
  165. #define RT8973A_INT1_ATTACH_MASK BIT(0)
  166. #define RT8973A_INT1_DETACH_MASK BIT(1)
  167. #define RT8973A_INT1_CHGDET_MASK BIT(2)
  168. #define RT8973A_INT1_DCD_T_MASK BIT(3)
  169. #define RT8973A_INT1_OVP_MASK BIT(4)
  170. #define RT8973A_INT1_CONNECT_MASK BIT(5)
  171. #define RT8973A_INT1_ADC_CHG_MASK BIT(6)
  172. #define RT8973A_INT1_OTP_MASK BIT(7)
  173. #define RT8973A_INT2_UVLOT_MASK BIT(0)
  174. #define RT8973A_INT2_POR_MASK BIT(1)
  175. #define RT8973A_INT2_OTP_FET_MASK BIT(2)
  176. #define RT8973A_INT2_OVP_FET_MASK BIT(3)
  177. #define RT8973A_INT2_OCP_LATCH_MASK BIT(4)
  178. #define RT8973A_INT2_OCP_MASK BIT(5)
  179. #define RT8973A_INT2_OVP_OCP_MASK BIT(6)
  180. #endif /* __LINUX_EXTCON_RT8973A_H */