synopsys_edac.c 38 KB

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  1. /*
  2. * Synopsys DDR ECC Driver
  3. * This driver is based on ppc4xx_edac.c drivers
  4. *
  5. * Copyright (C) 2012 - 2014 Xilinx, Inc.
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation, either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * This file is subject to the terms and conditions of the GNU General Public
  18. * License. See the file "COPYING" in the main directory of this archive
  19. * for more details
  20. */
  21. #include <linux/edac.h>
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include "edac_module.h"
  28. /* Number of cs_rows needed per memory controller */
  29. #define SYNPS_EDAC_NR_CSROWS 1
  30. /* Number of channels per memory controller */
  31. #define SYNPS_EDAC_NR_CHANS 1
  32. /* Granularity of reported error in bytes */
  33. #define SYNPS_EDAC_ERR_GRAIN 1
  34. #define SYNPS_EDAC_MSG_SIZE 256
  35. #define SYNPS_EDAC_MOD_STRING "synps_edac"
  36. #define SYNPS_EDAC_MOD_VER "1"
  37. /* Synopsys DDR memory controller registers that are relevant to ECC */
  38. #define CTRL_OFST 0x0
  39. #define T_ZQ_OFST 0xA4
  40. /* ECC control register */
  41. #define ECC_CTRL_OFST 0xC4
  42. /* ECC log register */
  43. #define CE_LOG_OFST 0xC8
  44. /* ECC address register */
  45. #define CE_ADDR_OFST 0xCC
  46. /* ECC data[31:0] register */
  47. #define CE_DATA_31_0_OFST 0xD0
  48. /* Uncorrectable error info registers */
  49. #define UE_LOG_OFST 0xDC
  50. #define UE_ADDR_OFST 0xE0
  51. #define UE_DATA_31_0_OFST 0xE4
  52. #define STAT_OFST 0xF0
  53. #define SCRUB_OFST 0xF4
  54. /* Control register bit field definitions */
  55. #define CTRL_BW_MASK 0xC
  56. #define CTRL_BW_SHIFT 2
  57. #define DDRCTL_WDTH_16 1
  58. #define DDRCTL_WDTH_32 0
  59. /* ZQ register bit field definitions */
  60. #define T_ZQ_DDRMODE_MASK 0x2
  61. /* ECC control register bit field definitions */
  62. #define ECC_CTRL_CLR_CE_ERR 0x2
  63. #define ECC_CTRL_CLR_UE_ERR 0x1
  64. /* ECC correctable/uncorrectable error log register definitions */
  65. #define LOG_VALID 0x1
  66. #define CE_LOG_BITPOS_MASK 0xFE
  67. #define CE_LOG_BITPOS_SHIFT 1
  68. /* ECC correctable/uncorrectable error address register definitions */
  69. #define ADDR_COL_MASK 0xFFF
  70. #define ADDR_ROW_MASK 0xFFFF000
  71. #define ADDR_ROW_SHIFT 12
  72. #define ADDR_BANK_MASK 0x70000000
  73. #define ADDR_BANK_SHIFT 28
  74. /* ECC statistic register definitions */
  75. #define STAT_UECNT_MASK 0xFF
  76. #define STAT_CECNT_MASK 0xFF00
  77. #define STAT_CECNT_SHIFT 8
  78. /* ECC scrub register definitions */
  79. #define SCRUB_MODE_MASK 0x7
  80. #define SCRUB_MODE_SECDED 0x4
  81. /* DDR ECC Quirks */
  82. #define DDR_ECC_INTR_SUPPORT BIT(0)
  83. #define DDR_ECC_DATA_POISON_SUPPORT BIT(1)
  84. /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
  85. /* ECC Configuration Registers */
  86. #define ECC_CFG0_OFST 0x70
  87. #define ECC_CFG1_OFST 0x74
  88. /* ECC Status Register */
  89. #define ECC_STAT_OFST 0x78
  90. /* ECC Clear Register */
  91. #define ECC_CLR_OFST 0x7C
  92. /* ECC Error count Register */
  93. #define ECC_ERRCNT_OFST 0x80
  94. /* ECC Corrected Error Address Register */
  95. #define ECC_CEADDR0_OFST 0x84
  96. #define ECC_CEADDR1_OFST 0x88
  97. /* ECC Syndrome Registers */
  98. #define ECC_CSYND0_OFST 0x8C
  99. #define ECC_CSYND1_OFST 0x90
  100. #define ECC_CSYND2_OFST 0x94
  101. /* ECC Bit Mask0 Address Register */
  102. #define ECC_BITMASK0_OFST 0x98
  103. #define ECC_BITMASK1_OFST 0x9C
  104. #define ECC_BITMASK2_OFST 0xA0
  105. /* ECC UnCorrected Error Address Register */
  106. #define ECC_UEADDR0_OFST 0xA4
  107. #define ECC_UEADDR1_OFST 0xA8
  108. /* ECC Syndrome Registers */
  109. #define ECC_UESYND0_OFST 0xAC
  110. #define ECC_UESYND1_OFST 0xB0
  111. #define ECC_UESYND2_OFST 0xB4
  112. /* ECC Poison Address Reg */
  113. #define ECC_POISON0_OFST 0xB8
  114. #define ECC_POISON1_OFST 0xBC
  115. #define ECC_ADDRMAP0_OFFSET 0x200
  116. /* Control register bitfield definitions */
  117. #define ECC_CTRL_BUSWIDTH_MASK 0x3000
  118. #define ECC_CTRL_BUSWIDTH_SHIFT 12
  119. #define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
  120. #define ECC_CTRL_CLR_UE_ERRCNT BIT(3)
  121. /* DDR Control Register width definitions */
  122. #define DDRCTL_EWDTH_16 2
  123. #define DDRCTL_EWDTH_32 1
  124. #define DDRCTL_EWDTH_64 0
  125. /* ECC status register definitions */
  126. #define ECC_STAT_UECNT_MASK 0xF0000
  127. #define ECC_STAT_UECNT_SHIFT 16
  128. #define ECC_STAT_CECNT_MASK 0xF00
  129. #define ECC_STAT_CECNT_SHIFT 8
  130. #define ECC_STAT_BITNUM_MASK 0x7F
  131. /* ECC error count register definitions */
  132. #define ECC_ERRCNT_UECNT_MASK 0xFFFF0000
  133. #define ECC_ERRCNT_UECNT_SHIFT 16
  134. #define ECC_ERRCNT_CECNT_MASK 0xFFFF
  135. /* DDR QOS Interrupt register definitions */
  136. #define DDR_QOS_IRQ_STAT_OFST 0x20200
  137. #define DDR_QOSUE_MASK 0x4
  138. #define DDR_QOSCE_MASK 0x2
  139. #define ECC_CE_UE_INTR_MASK 0x6
  140. #define DDR_QOS_IRQ_EN_OFST 0x20208
  141. #define DDR_QOS_IRQ_DB_OFST 0x2020C
  142. /* ECC Corrected Error Register Mask and Shifts*/
  143. #define ECC_CEADDR0_RW_MASK 0x3FFFF
  144. #define ECC_CEADDR0_RNK_MASK BIT(24)
  145. #define ECC_CEADDR1_BNKGRP_MASK 0x3000000
  146. #define ECC_CEADDR1_BNKNR_MASK 0x70000
  147. #define ECC_CEADDR1_BLKNR_MASK 0xFFF
  148. #define ECC_CEADDR1_BNKGRP_SHIFT 24
  149. #define ECC_CEADDR1_BNKNR_SHIFT 16
  150. /* ECC Poison register shifts */
  151. #define ECC_POISON0_RANK_SHIFT 24
  152. #define ECC_POISON0_RANK_MASK BIT(24)
  153. #define ECC_POISON0_COLUMN_SHIFT 0
  154. #define ECC_POISON0_COLUMN_MASK 0xFFF
  155. #define ECC_POISON1_BG_SHIFT 28
  156. #define ECC_POISON1_BG_MASK 0x30000000
  157. #define ECC_POISON1_BANKNR_SHIFT 24
  158. #define ECC_POISON1_BANKNR_MASK 0x7000000
  159. #define ECC_POISON1_ROW_SHIFT 0
  160. #define ECC_POISON1_ROW_MASK 0x3FFFF
  161. /* DDR Memory type defines */
  162. #define MEM_TYPE_DDR3 0x1
  163. #define MEM_TYPE_LPDDR3 0x8
  164. #define MEM_TYPE_DDR2 0x4
  165. #define MEM_TYPE_DDR4 0x10
  166. #define MEM_TYPE_LPDDR4 0x20
  167. /* DDRC Software control register */
  168. #define DDRC_SWCTL 0x320
  169. /* DDRC ECC CE & UE poison mask */
  170. #define ECC_CEPOISON_MASK 0x3
  171. #define ECC_UEPOISON_MASK 0x1
  172. /* DDRC Device config masks */
  173. #define DDRC_MSTR_CFG_MASK 0xC0000000
  174. #define DDRC_MSTR_CFG_SHIFT 30
  175. #define DDRC_MSTR_CFG_X4_MASK 0x0
  176. #define DDRC_MSTR_CFG_X8_MASK 0x1
  177. #define DDRC_MSTR_CFG_X16_MASK 0x2
  178. #define DDRC_MSTR_CFG_X32_MASK 0x3
  179. #define DDR_MAX_ROW_SHIFT 18
  180. #define DDR_MAX_COL_SHIFT 14
  181. #define DDR_MAX_BANK_SHIFT 3
  182. #define DDR_MAX_BANKGRP_SHIFT 2
  183. #define ROW_MAX_VAL_MASK 0xF
  184. #define COL_MAX_VAL_MASK 0xF
  185. #define BANK_MAX_VAL_MASK 0x1F
  186. #define BANKGRP_MAX_VAL_MASK 0x1F
  187. #define RANK_MAX_VAL_MASK 0x1F
  188. #define ROW_B0_BASE 6
  189. #define ROW_B1_BASE 7
  190. #define ROW_B2_BASE 8
  191. #define ROW_B3_BASE 9
  192. #define ROW_B4_BASE 10
  193. #define ROW_B5_BASE 11
  194. #define ROW_B6_BASE 12
  195. #define ROW_B7_BASE 13
  196. #define ROW_B8_BASE 14
  197. #define ROW_B9_BASE 15
  198. #define ROW_B10_BASE 16
  199. #define ROW_B11_BASE 17
  200. #define ROW_B12_BASE 18
  201. #define ROW_B13_BASE 19
  202. #define ROW_B14_BASE 20
  203. #define ROW_B15_BASE 21
  204. #define ROW_B16_BASE 22
  205. #define ROW_B17_BASE 23
  206. #define COL_B2_BASE 2
  207. #define COL_B3_BASE 3
  208. #define COL_B4_BASE 4
  209. #define COL_B5_BASE 5
  210. #define COL_B6_BASE 6
  211. #define COL_B7_BASE 7
  212. #define COL_B8_BASE 8
  213. #define COL_B9_BASE 9
  214. #define COL_B10_BASE 10
  215. #define COL_B11_BASE 11
  216. #define COL_B12_BASE 12
  217. #define COL_B13_BASE 13
  218. #define BANK_B0_BASE 2
  219. #define BANK_B1_BASE 3
  220. #define BANK_B2_BASE 4
  221. #define BANKGRP_B0_BASE 2
  222. #define BANKGRP_B1_BASE 3
  223. #define RANK_B0_BASE 6
  224. /**
  225. * struct ecc_error_info - ECC error log information.
  226. * @row: Row number.
  227. * @col: Column number.
  228. * @bank: Bank number.
  229. * @bitpos: Bit position.
  230. * @data: Data causing the error.
  231. * @bankgrpnr: Bank group number.
  232. * @blknr: Block number.
  233. */
  234. struct ecc_error_info {
  235. u32 row;
  236. u32 col;
  237. u32 bank;
  238. u32 bitpos;
  239. u32 data;
  240. u32 bankgrpnr;
  241. u32 blknr;
  242. };
  243. /**
  244. * struct synps_ecc_status - ECC status information to report.
  245. * @ce_cnt: Correctable error count.
  246. * @ue_cnt: Uncorrectable error count.
  247. * @ceinfo: Correctable error log information.
  248. * @ueinfo: Uncorrectable error log information.
  249. */
  250. struct synps_ecc_status {
  251. u32 ce_cnt;
  252. u32 ue_cnt;
  253. struct ecc_error_info ceinfo;
  254. struct ecc_error_info ueinfo;
  255. };
  256. /**
  257. * struct synps_edac_priv - DDR memory controller private instance data.
  258. * @baseaddr: Base address of the DDR controller.
  259. * @message: Buffer for framing the event specific info.
  260. * @stat: ECC status information.
  261. * @p_data: Platform data.
  262. * @ce_cnt: Correctable Error count.
  263. * @ue_cnt: Uncorrectable Error count.
  264. * @poison_addr: Data poison address.
  265. * @row_shift: Bit shifts for row bit.
  266. * @col_shift: Bit shifts for column bit.
  267. * @bank_shift: Bit shifts for bank bit.
  268. * @bankgrp_shift: Bit shifts for bank group bit.
  269. * @rank_shift: Bit shifts for rank bit.
  270. */
  271. struct synps_edac_priv {
  272. void __iomem *baseaddr;
  273. char message[SYNPS_EDAC_MSG_SIZE];
  274. struct synps_ecc_status stat;
  275. const struct synps_platform_data *p_data;
  276. u32 ce_cnt;
  277. u32 ue_cnt;
  278. #ifdef CONFIG_EDAC_DEBUG
  279. ulong poison_addr;
  280. u32 row_shift[18];
  281. u32 col_shift[14];
  282. u32 bank_shift[3];
  283. u32 bankgrp_shift[2];
  284. u32 rank_shift[1];
  285. #endif
  286. };
  287. /**
  288. * struct synps_platform_data - synps platform data structure.
  289. * @get_error_info: Get EDAC error info.
  290. * @get_mtype: Get mtype.
  291. * @get_dtype: Get dtype.
  292. * @get_ecc_state: Get ECC state.
  293. * @quirks: To differentiate IPs.
  294. */
  295. struct synps_platform_data {
  296. int (*get_error_info)(struct synps_edac_priv *priv);
  297. enum mem_type (*get_mtype)(const void __iomem *base);
  298. enum dev_type (*get_dtype)(const void __iomem *base);
  299. bool (*get_ecc_state)(void __iomem *base);
  300. int quirks;
  301. };
  302. /**
  303. * zynq_get_error_info - Get the current ECC error info.
  304. * @priv: DDR memory controller private instance data.
  305. *
  306. * Return: one if there is no error, otherwise zero.
  307. */
  308. static int zynq_get_error_info(struct synps_edac_priv *priv)
  309. {
  310. struct synps_ecc_status *p;
  311. u32 regval, clearval = 0;
  312. void __iomem *base;
  313. base = priv->baseaddr;
  314. p = &priv->stat;
  315. regval = readl(base + STAT_OFST);
  316. if (!regval)
  317. return 1;
  318. p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT;
  319. p->ue_cnt = regval & STAT_UECNT_MASK;
  320. regval = readl(base + CE_LOG_OFST);
  321. if (!(p->ce_cnt && (regval & LOG_VALID)))
  322. goto ue_err;
  323. p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT;
  324. regval = readl(base + CE_ADDR_OFST);
  325. p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
  326. p->ceinfo.col = regval & ADDR_COL_MASK;
  327. p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
  328. p->ceinfo.data = readl(base + CE_DATA_31_0_OFST);
  329. edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos,
  330. p->ceinfo.data);
  331. clearval = ECC_CTRL_CLR_CE_ERR;
  332. ue_err:
  333. regval = readl(base + UE_LOG_OFST);
  334. if (!(p->ue_cnt && (regval & LOG_VALID)))
  335. goto out;
  336. regval = readl(base + UE_ADDR_OFST);
  337. p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT;
  338. p->ueinfo.col = regval & ADDR_COL_MASK;
  339. p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT;
  340. p->ueinfo.data = readl(base + UE_DATA_31_0_OFST);
  341. clearval |= ECC_CTRL_CLR_UE_ERR;
  342. out:
  343. writel(clearval, base + ECC_CTRL_OFST);
  344. writel(0x0, base + ECC_CTRL_OFST);
  345. return 0;
  346. }
  347. /**
  348. * zynqmp_get_error_info - Get the current ECC error info.
  349. * @priv: DDR memory controller private instance data.
  350. *
  351. * Return: one if there is no error otherwise returns zero.
  352. */
  353. static int zynqmp_get_error_info(struct synps_edac_priv *priv)
  354. {
  355. struct synps_ecc_status *p;
  356. u32 regval, clearval = 0;
  357. void __iomem *base;
  358. base = priv->baseaddr;
  359. p = &priv->stat;
  360. regval = readl(base + ECC_ERRCNT_OFST);
  361. p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
  362. p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
  363. if (!p->ce_cnt)
  364. goto ue_err;
  365. regval = readl(base + ECC_STAT_OFST);
  366. if (!regval)
  367. return 1;
  368. p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
  369. regval = readl(base + ECC_CEADDR0_OFST);
  370. p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
  371. regval = readl(base + ECC_CEADDR1_OFST);
  372. p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
  373. ECC_CEADDR1_BNKNR_SHIFT;
  374. p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
  375. ECC_CEADDR1_BNKGRP_SHIFT;
  376. p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
  377. p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
  378. edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
  379. readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
  380. readl(base + ECC_CSYND2_OFST));
  381. ue_err:
  382. if (!p->ue_cnt)
  383. goto out;
  384. regval = readl(base + ECC_UEADDR0_OFST);
  385. p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
  386. regval = readl(base + ECC_UEADDR1_OFST);
  387. p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
  388. ECC_CEADDR1_BNKGRP_SHIFT;
  389. p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
  390. ECC_CEADDR1_BNKNR_SHIFT;
  391. p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
  392. p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
  393. out:
  394. clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
  395. clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
  396. writel(clearval, base + ECC_CLR_OFST);
  397. writel(0x0, base + ECC_CLR_OFST);
  398. return 0;
  399. }
  400. /**
  401. * handle_error - Handle Correctable and Uncorrectable errors.
  402. * @mci: EDAC memory controller instance.
  403. * @p: Synopsys ECC status structure.
  404. *
  405. * Handles ECC correctable and uncorrectable errors.
  406. */
  407. static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
  408. {
  409. struct synps_edac_priv *priv = mci->pvt_info;
  410. struct ecc_error_info *pinf;
  411. if (p->ce_cnt) {
  412. pinf = &p->ceinfo;
  413. if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
  414. snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
  415. "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x",
  416. "CE", pinf->row, pinf->bank,
  417. pinf->bankgrpnr, pinf->blknr,
  418. pinf->bitpos, pinf->data);
  419. } else {
  420. snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
  421. "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x",
  422. "CE", pinf->row, pinf->bank, pinf->col,
  423. pinf->bitpos, pinf->data);
  424. }
  425. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
  426. p->ce_cnt, 0, 0, 0, 0, 0, -1,
  427. priv->message, "");
  428. }
  429. if (p->ue_cnt) {
  430. pinf = &p->ueinfo;
  431. if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
  432. snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
  433. "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d",
  434. "UE", pinf->row, pinf->bank,
  435. pinf->bankgrpnr, pinf->blknr);
  436. } else {
  437. snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
  438. "DDR ECC error type :%s Row %d Bank %d Col %d ",
  439. "UE", pinf->row, pinf->bank, pinf->col);
  440. }
  441. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
  442. p->ue_cnt, 0, 0, 0, 0, 0, -1,
  443. priv->message, "");
  444. }
  445. memset(p, 0, sizeof(*p));
  446. }
  447. /**
  448. * intr_handler - Interrupt Handler for ECC interrupts.
  449. * @irq: IRQ number.
  450. * @dev_id: Device ID.
  451. *
  452. * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise.
  453. */
  454. static irqreturn_t intr_handler(int irq, void *dev_id)
  455. {
  456. const struct synps_platform_data *p_data;
  457. struct mem_ctl_info *mci = dev_id;
  458. struct synps_edac_priv *priv;
  459. int status, regval;
  460. priv = mci->pvt_info;
  461. p_data = priv->p_data;
  462. regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
  463. regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
  464. if (!(regval & ECC_CE_UE_INTR_MASK))
  465. return IRQ_NONE;
  466. status = p_data->get_error_info(priv);
  467. if (status)
  468. return IRQ_NONE;
  469. priv->ce_cnt += priv->stat.ce_cnt;
  470. priv->ue_cnt += priv->stat.ue_cnt;
  471. handle_error(mci, &priv->stat);
  472. edac_dbg(3, "Total error count CE %d UE %d\n",
  473. priv->ce_cnt, priv->ue_cnt);
  474. writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
  475. return IRQ_HANDLED;
  476. }
  477. /**
  478. * check_errors - Check controller for ECC errors.
  479. * @mci: EDAC memory controller instance.
  480. *
  481. * Check and post ECC errors. Called by the polling thread.
  482. */
  483. static void check_errors(struct mem_ctl_info *mci)
  484. {
  485. const struct synps_platform_data *p_data;
  486. struct synps_edac_priv *priv;
  487. int status;
  488. priv = mci->pvt_info;
  489. p_data = priv->p_data;
  490. status = p_data->get_error_info(priv);
  491. if (status)
  492. return;
  493. priv->ce_cnt += priv->stat.ce_cnt;
  494. priv->ue_cnt += priv->stat.ue_cnt;
  495. handle_error(mci, &priv->stat);
  496. edac_dbg(3, "Total error count CE %d UE %d\n",
  497. priv->ce_cnt, priv->ue_cnt);
  498. }
  499. /**
  500. * zynq_get_dtype - Return the controller memory width.
  501. * @base: DDR memory controller base address.
  502. *
  503. * Get the EDAC device type width appropriate for the current controller
  504. * configuration.
  505. *
  506. * Return: a device type width enumeration.
  507. */
  508. static enum dev_type zynq_get_dtype(const void __iomem *base)
  509. {
  510. enum dev_type dt;
  511. u32 width;
  512. width = readl(base + CTRL_OFST);
  513. width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT;
  514. switch (width) {
  515. case DDRCTL_WDTH_16:
  516. dt = DEV_X2;
  517. break;
  518. case DDRCTL_WDTH_32:
  519. dt = DEV_X4;
  520. break;
  521. default:
  522. dt = DEV_UNKNOWN;
  523. }
  524. return dt;
  525. }
  526. /**
  527. * zynqmp_get_dtype - Return the controller memory width.
  528. * @base: DDR memory controller base address.
  529. *
  530. * Get the EDAC device type width appropriate for the current controller
  531. * configuration.
  532. *
  533. * Return: a device type width enumeration.
  534. */
  535. static enum dev_type zynqmp_get_dtype(const void __iomem *base)
  536. {
  537. enum dev_type dt;
  538. u32 width;
  539. width = readl(base + CTRL_OFST);
  540. width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
  541. switch (width) {
  542. case DDRCTL_EWDTH_16:
  543. dt = DEV_X2;
  544. break;
  545. case DDRCTL_EWDTH_32:
  546. dt = DEV_X4;
  547. break;
  548. case DDRCTL_EWDTH_64:
  549. dt = DEV_X8;
  550. break;
  551. default:
  552. dt = DEV_UNKNOWN;
  553. }
  554. return dt;
  555. }
  556. /**
  557. * zynq_get_ecc_state - Return the controller ECC enable/disable status.
  558. * @base: DDR memory controller base address.
  559. *
  560. * Get the ECC enable/disable status of the controller.
  561. *
  562. * Return: true if enabled, otherwise false.
  563. */
  564. static bool zynq_get_ecc_state(void __iomem *base)
  565. {
  566. enum dev_type dt;
  567. u32 ecctype;
  568. dt = zynq_get_dtype(base);
  569. if (dt == DEV_UNKNOWN)
  570. return false;
  571. ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
  572. if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
  573. return true;
  574. return false;
  575. }
  576. /**
  577. * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
  578. * @base: DDR memory controller base address.
  579. *
  580. * Get the ECC enable/disable status for the controller.
  581. *
  582. * Return: a ECC status boolean i.e true/false - enabled/disabled.
  583. */
  584. static bool zynqmp_get_ecc_state(void __iomem *base)
  585. {
  586. enum dev_type dt;
  587. u32 ecctype;
  588. dt = zynqmp_get_dtype(base);
  589. if (dt == DEV_UNKNOWN)
  590. return false;
  591. ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
  592. if ((ecctype == SCRUB_MODE_SECDED) &&
  593. ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8)))
  594. return true;
  595. return false;
  596. }
  597. /**
  598. * get_memsize - Read the size of the attached memory device.
  599. *
  600. * Return: the memory size in bytes.
  601. */
  602. static u32 get_memsize(void)
  603. {
  604. struct sysinfo inf;
  605. si_meminfo(&inf);
  606. return inf.totalram * inf.mem_unit;
  607. }
  608. /**
  609. * zynq_get_mtype - Return the controller memory type.
  610. * @base: Synopsys ECC status structure.
  611. *
  612. * Get the EDAC memory type appropriate for the current controller
  613. * configuration.
  614. *
  615. * Return: a memory type enumeration.
  616. */
  617. static enum mem_type zynq_get_mtype(const void __iomem *base)
  618. {
  619. enum mem_type mt;
  620. u32 memtype;
  621. memtype = readl(base + T_ZQ_OFST);
  622. if (memtype & T_ZQ_DDRMODE_MASK)
  623. mt = MEM_DDR3;
  624. else
  625. mt = MEM_DDR2;
  626. return mt;
  627. }
  628. /**
  629. * zynqmp_get_mtype - Returns controller memory type.
  630. * @base: Synopsys ECC status structure.
  631. *
  632. * Get the EDAC memory type appropriate for the current controller
  633. * configuration.
  634. *
  635. * Return: a memory type enumeration.
  636. */
  637. static enum mem_type zynqmp_get_mtype(const void __iomem *base)
  638. {
  639. enum mem_type mt;
  640. u32 memtype;
  641. memtype = readl(base + CTRL_OFST);
  642. if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3))
  643. mt = MEM_DDR3;
  644. else if (memtype & MEM_TYPE_DDR2)
  645. mt = MEM_RDDR2;
  646. else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4))
  647. mt = MEM_DDR4;
  648. else
  649. mt = MEM_EMPTY;
  650. return mt;
  651. }
  652. /**
  653. * init_csrows - Initialize the csrow data.
  654. * @mci: EDAC memory controller instance.
  655. *
  656. * Initialize the chip select rows associated with the EDAC memory
  657. * controller instance.
  658. */
  659. static void init_csrows(struct mem_ctl_info *mci)
  660. {
  661. struct synps_edac_priv *priv = mci->pvt_info;
  662. const struct synps_platform_data *p_data;
  663. struct csrow_info *csi;
  664. struct dimm_info *dimm;
  665. u32 size, row;
  666. int j;
  667. p_data = priv->p_data;
  668. for (row = 0; row < mci->nr_csrows; row++) {
  669. csi = mci->csrows[row];
  670. size = get_memsize();
  671. for (j = 0; j < csi->nr_channels; j++) {
  672. dimm = csi->channels[j]->dimm;
  673. dimm->edac_mode = EDAC_SECDED;
  674. dimm->mtype = p_data->get_mtype(priv->baseaddr);
  675. dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels;
  676. dimm->grain = SYNPS_EDAC_ERR_GRAIN;
  677. dimm->dtype = p_data->get_dtype(priv->baseaddr);
  678. }
  679. }
  680. }
  681. /**
  682. * mc_init - Initialize one driver instance.
  683. * @mci: EDAC memory controller instance.
  684. * @pdev: platform device.
  685. *
  686. * Perform initialization of the EDAC memory controller instance and
  687. * related driver-private data associated with the memory controller the
  688. * instance is bound to.
  689. */
  690. static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev)
  691. {
  692. struct synps_edac_priv *priv;
  693. mci->pdev = &pdev->dev;
  694. priv = mci->pvt_info;
  695. platform_set_drvdata(pdev, mci);
  696. /* Initialize controller capabilities and configuration */
  697. mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2;
  698. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
  699. mci->scrub_cap = SCRUB_HW_SRC;
  700. mci->scrub_mode = SCRUB_NONE;
  701. mci->edac_cap = EDAC_FLAG_SECDED;
  702. mci->ctl_name = "synps_ddr_controller";
  703. mci->dev_name = SYNPS_EDAC_MOD_STRING;
  704. mci->mod_name = SYNPS_EDAC_MOD_VER;
  705. if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
  706. edac_op_state = EDAC_OPSTATE_INT;
  707. } else {
  708. edac_op_state = EDAC_OPSTATE_POLL;
  709. mci->edac_check = check_errors;
  710. }
  711. mci->ctl_page_to_phys = NULL;
  712. init_csrows(mci);
  713. }
  714. static void enable_intr(struct synps_edac_priv *priv)
  715. {
  716. /* Enable UE/CE Interrupts */
  717. writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
  718. priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
  719. }
  720. static void disable_intr(struct synps_edac_priv *priv)
  721. {
  722. /* Disable UE/CE Interrupts */
  723. writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
  724. priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
  725. }
  726. static int setup_irq(struct mem_ctl_info *mci,
  727. struct platform_device *pdev)
  728. {
  729. struct synps_edac_priv *priv = mci->pvt_info;
  730. int ret, irq;
  731. irq = platform_get_irq(pdev, 0);
  732. if (irq < 0) {
  733. edac_printk(KERN_ERR, EDAC_MC,
  734. "No IRQ %d in DT\n", irq);
  735. return irq;
  736. }
  737. ret = devm_request_irq(&pdev->dev, irq, intr_handler,
  738. 0, dev_name(&pdev->dev), mci);
  739. if (ret < 0) {
  740. edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n");
  741. return ret;
  742. }
  743. enable_intr(priv);
  744. return 0;
  745. }
  746. static const struct synps_platform_data zynq_edac_def = {
  747. .get_error_info = zynq_get_error_info,
  748. .get_mtype = zynq_get_mtype,
  749. .get_dtype = zynq_get_dtype,
  750. .get_ecc_state = zynq_get_ecc_state,
  751. .quirks = 0,
  752. };
  753. static const struct synps_platform_data zynqmp_edac_def = {
  754. .get_error_info = zynqmp_get_error_info,
  755. .get_mtype = zynqmp_get_mtype,
  756. .get_dtype = zynqmp_get_dtype,
  757. .get_ecc_state = zynqmp_get_ecc_state,
  758. .quirks = (DDR_ECC_INTR_SUPPORT
  759. #ifdef CONFIG_EDAC_DEBUG
  760. | DDR_ECC_DATA_POISON_SUPPORT
  761. #endif
  762. ),
  763. };
  764. static const struct of_device_id synps_edac_match[] = {
  765. {
  766. .compatible = "xlnx,zynq-ddrc-a05",
  767. .data = (void *)&zynq_edac_def
  768. },
  769. {
  770. .compatible = "xlnx,zynqmp-ddrc-2.40a",
  771. .data = (void *)&zynqmp_edac_def
  772. },
  773. {
  774. /* end of table */
  775. }
  776. };
  777. MODULE_DEVICE_TABLE(of, synps_edac_match);
  778. #ifdef CONFIG_EDAC_DEBUG
  779. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  780. /**
  781. * ddr_poison_setup - Update poison registers.
  782. * @priv: DDR memory controller private instance data.
  783. *
  784. * Update poison registers as per DDR mapping.
  785. * Return: none.
  786. */
  787. static void ddr_poison_setup(struct synps_edac_priv *priv)
  788. {
  789. int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval;
  790. int index;
  791. ulong hif_addr = 0;
  792. hif_addr = priv->poison_addr >> 3;
  793. for (index = 0; index < DDR_MAX_ROW_SHIFT; index++) {
  794. if (priv->row_shift[index])
  795. row |= (((hif_addr >> priv->row_shift[index]) &
  796. BIT(0)) << index);
  797. else
  798. break;
  799. }
  800. for (index = 0; index < DDR_MAX_COL_SHIFT; index++) {
  801. if (priv->col_shift[index] || index < 3)
  802. col |= (((hif_addr >> priv->col_shift[index]) &
  803. BIT(0)) << index);
  804. else
  805. break;
  806. }
  807. for (index = 0; index < DDR_MAX_BANK_SHIFT; index++) {
  808. if (priv->bank_shift[index])
  809. bank |= (((hif_addr >> priv->bank_shift[index]) &
  810. BIT(0)) << index);
  811. else
  812. break;
  813. }
  814. for (index = 0; index < DDR_MAX_BANKGRP_SHIFT; index++) {
  815. if (priv->bankgrp_shift[index])
  816. bankgrp |= (((hif_addr >> priv->bankgrp_shift[index])
  817. & BIT(0)) << index);
  818. else
  819. break;
  820. }
  821. if (priv->rank_shift[0])
  822. rank = (hif_addr >> priv->rank_shift[0]) & BIT(0);
  823. regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK;
  824. regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK;
  825. writel(regval, priv->baseaddr + ECC_POISON0_OFST);
  826. regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK;
  827. regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK;
  828. regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK;
  829. writel(regval, priv->baseaddr + ECC_POISON1_OFST);
  830. }
  831. static ssize_t inject_data_error_show(struct device *dev,
  832. struct device_attribute *mattr,
  833. char *data)
  834. {
  835. struct mem_ctl_info *mci = to_mci(dev);
  836. struct synps_edac_priv *priv = mci->pvt_info;
  837. return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r"
  838. "Error injection Address: 0x%lx\n\r",
  839. readl(priv->baseaddr + ECC_POISON0_OFST),
  840. readl(priv->baseaddr + ECC_POISON1_OFST),
  841. priv->poison_addr);
  842. }
  843. static ssize_t inject_data_error_store(struct device *dev,
  844. struct device_attribute *mattr,
  845. const char *data, size_t count)
  846. {
  847. struct mem_ctl_info *mci = to_mci(dev);
  848. struct synps_edac_priv *priv = mci->pvt_info;
  849. if (kstrtoul(data, 0, &priv->poison_addr))
  850. return -EINVAL;
  851. ddr_poison_setup(priv);
  852. return count;
  853. }
  854. static ssize_t inject_data_poison_show(struct device *dev,
  855. struct device_attribute *mattr,
  856. char *data)
  857. {
  858. struct mem_ctl_info *mci = to_mci(dev);
  859. struct synps_edac_priv *priv = mci->pvt_info;
  860. return sprintf(data, "Data Poisoning: %s\n\r",
  861. (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3)
  862. ? ("Correctable Error") : ("UnCorrectable Error"));
  863. }
  864. static ssize_t inject_data_poison_store(struct device *dev,
  865. struct device_attribute *mattr,
  866. const char *data, size_t count)
  867. {
  868. struct mem_ctl_info *mci = to_mci(dev);
  869. struct synps_edac_priv *priv = mci->pvt_info;
  870. writel(0, priv->baseaddr + DDRC_SWCTL);
  871. if (strncmp(data, "CE", 2) == 0)
  872. writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
  873. else
  874. writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST);
  875. writel(1, priv->baseaddr + DDRC_SWCTL);
  876. return count;
  877. }
  878. static DEVICE_ATTR_RW(inject_data_error);
  879. static DEVICE_ATTR_RW(inject_data_poison);
  880. static int edac_create_sysfs_attributes(struct mem_ctl_info *mci)
  881. {
  882. int rc;
  883. rc = device_create_file(&mci->dev, &dev_attr_inject_data_error);
  884. if (rc < 0)
  885. return rc;
  886. rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison);
  887. if (rc < 0)
  888. return rc;
  889. return 0;
  890. }
  891. static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci)
  892. {
  893. device_remove_file(&mci->dev, &dev_attr_inject_data_error);
  894. device_remove_file(&mci->dev, &dev_attr_inject_data_poison);
  895. }
  896. static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap)
  897. {
  898. u32 addrmap_row_b2_10;
  899. int index;
  900. priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE;
  901. priv->row_shift[1] = ((addrmap[5] >> 8) &
  902. ROW_MAX_VAL_MASK) + ROW_B1_BASE;
  903. addrmap_row_b2_10 = (addrmap[5] >> 16) & ROW_MAX_VAL_MASK;
  904. if (addrmap_row_b2_10 != ROW_MAX_VAL_MASK) {
  905. for (index = 2; index < 11; index++)
  906. priv->row_shift[index] = addrmap_row_b2_10 +
  907. index + ROW_B0_BASE;
  908. } else {
  909. priv->row_shift[2] = (addrmap[9] &
  910. ROW_MAX_VAL_MASK) + ROW_B2_BASE;
  911. priv->row_shift[3] = ((addrmap[9] >> 8) &
  912. ROW_MAX_VAL_MASK) + ROW_B3_BASE;
  913. priv->row_shift[4] = ((addrmap[9] >> 16) &
  914. ROW_MAX_VAL_MASK) + ROW_B4_BASE;
  915. priv->row_shift[5] = ((addrmap[9] >> 24) &
  916. ROW_MAX_VAL_MASK) + ROW_B5_BASE;
  917. priv->row_shift[6] = (addrmap[10] &
  918. ROW_MAX_VAL_MASK) + ROW_B6_BASE;
  919. priv->row_shift[7] = ((addrmap[10] >> 8) &
  920. ROW_MAX_VAL_MASK) + ROW_B7_BASE;
  921. priv->row_shift[8] = ((addrmap[10] >> 16) &
  922. ROW_MAX_VAL_MASK) + ROW_B8_BASE;
  923. priv->row_shift[9] = ((addrmap[10] >> 24) &
  924. ROW_MAX_VAL_MASK) + ROW_B9_BASE;
  925. priv->row_shift[10] = (addrmap[11] &
  926. ROW_MAX_VAL_MASK) + ROW_B10_BASE;
  927. }
  928. priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) ==
  929. ROW_MAX_VAL_MASK) ? 0 : (((addrmap[5] >> 24) &
  930. ROW_MAX_VAL_MASK) + ROW_B11_BASE);
  931. priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) ==
  932. ROW_MAX_VAL_MASK) ? 0 : ((addrmap[6] &
  933. ROW_MAX_VAL_MASK) + ROW_B12_BASE);
  934. priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) ==
  935. ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 8) &
  936. ROW_MAX_VAL_MASK) + ROW_B13_BASE);
  937. priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) ==
  938. ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 16) &
  939. ROW_MAX_VAL_MASK) + ROW_B14_BASE);
  940. priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) ==
  941. ROW_MAX_VAL_MASK) ? 0 : (((addrmap[6] >> 24) &
  942. ROW_MAX_VAL_MASK) + ROW_B15_BASE);
  943. priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) ==
  944. ROW_MAX_VAL_MASK) ? 0 : ((addrmap[7] &
  945. ROW_MAX_VAL_MASK) + ROW_B16_BASE);
  946. priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) ==
  947. ROW_MAX_VAL_MASK) ? 0 : (((addrmap[7] >> 8) &
  948. ROW_MAX_VAL_MASK) + ROW_B17_BASE);
  949. }
  950. static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap)
  951. {
  952. u32 width, memtype;
  953. int index;
  954. memtype = readl(priv->baseaddr + CTRL_OFST);
  955. width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
  956. priv->col_shift[0] = 0;
  957. priv->col_shift[1] = 1;
  958. priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE;
  959. priv->col_shift[3] = ((addrmap[2] >> 8) &
  960. COL_MAX_VAL_MASK) + COL_B3_BASE;
  961. priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) ==
  962. COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 16) &
  963. COL_MAX_VAL_MASK) + COL_B4_BASE);
  964. priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) ==
  965. COL_MAX_VAL_MASK) ? 0 : (((addrmap[2] >> 24) &
  966. COL_MAX_VAL_MASK) + COL_B5_BASE);
  967. priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) ==
  968. COL_MAX_VAL_MASK) ? 0 : ((addrmap[3] &
  969. COL_MAX_VAL_MASK) + COL_B6_BASE);
  970. priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) ==
  971. COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 8) &
  972. COL_MAX_VAL_MASK) + COL_B7_BASE);
  973. priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) ==
  974. COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) &
  975. COL_MAX_VAL_MASK) + COL_B8_BASE);
  976. priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) ==
  977. COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) &
  978. COL_MAX_VAL_MASK) + COL_B9_BASE);
  979. if (width == DDRCTL_EWDTH_64) {
  980. if (memtype & MEM_TYPE_LPDDR3) {
  981. priv->col_shift[10] = ((addrmap[4] &
  982. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  983. ((addrmap[4] & COL_MAX_VAL_MASK) +
  984. COL_B10_BASE);
  985. priv->col_shift[11] = (((addrmap[4] >> 8) &
  986. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  987. (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
  988. COL_B11_BASE);
  989. } else {
  990. priv->col_shift[11] = ((addrmap[4] &
  991. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  992. ((addrmap[4] & COL_MAX_VAL_MASK) +
  993. COL_B10_BASE);
  994. priv->col_shift[13] = (((addrmap[4] >> 8) &
  995. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  996. (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) +
  997. COL_B11_BASE);
  998. }
  999. } else if (width == DDRCTL_EWDTH_32) {
  1000. if (memtype & MEM_TYPE_LPDDR3) {
  1001. priv->col_shift[10] = (((addrmap[3] >> 24) &
  1002. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1003. (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
  1004. COL_B9_BASE);
  1005. priv->col_shift[11] = ((addrmap[4] &
  1006. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1007. ((addrmap[4] & COL_MAX_VAL_MASK) +
  1008. COL_B10_BASE);
  1009. } else {
  1010. priv->col_shift[11] = (((addrmap[3] >> 24) &
  1011. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1012. (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
  1013. COL_B9_BASE);
  1014. priv->col_shift[13] = ((addrmap[4] &
  1015. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1016. ((addrmap[4] & COL_MAX_VAL_MASK) +
  1017. COL_B10_BASE);
  1018. }
  1019. } else {
  1020. if (memtype & MEM_TYPE_LPDDR3) {
  1021. priv->col_shift[10] = (((addrmap[3] >> 16) &
  1022. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1023. (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
  1024. COL_B8_BASE);
  1025. priv->col_shift[11] = (((addrmap[3] >> 24) &
  1026. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1027. (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
  1028. COL_B9_BASE);
  1029. priv->col_shift[13] = ((addrmap[4] &
  1030. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1031. ((addrmap[4] & COL_MAX_VAL_MASK) +
  1032. COL_B10_BASE);
  1033. } else {
  1034. priv->col_shift[11] = (((addrmap[3] >> 16) &
  1035. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1036. (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) +
  1037. COL_B8_BASE);
  1038. priv->col_shift[13] = (((addrmap[3] >> 24) &
  1039. COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 :
  1040. (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) +
  1041. COL_B9_BASE);
  1042. }
  1043. }
  1044. if (width) {
  1045. for (index = 9; index > width; index--) {
  1046. priv->col_shift[index] = priv->col_shift[index - width];
  1047. priv->col_shift[index - width] = 0;
  1048. }
  1049. }
  1050. }
  1051. static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
  1052. {
  1053. priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE;
  1054. priv->bank_shift[1] = ((addrmap[1] >> 8) &
  1055. BANK_MAX_VAL_MASK) + BANK_B1_BASE;
  1056. priv->bank_shift[2] = (((addrmap[1] >> 16) &
  1057. BANK_MAX_VAL_MASK) == BANK_MAX_VAL_MASK) ? 0 :
  1058. (((addrmap[1] >> 16) & BANK_MAX_VAL_MASK) +
  1059. BANK_B2_BASE);
  1060. }
  1061. static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap)
  1062. {
  1063. priv->bankgrp_shift[0] = (addrmap[8] &
  1064. BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE;
  1065. priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) ==
  1066. BANKGRP_MAX_VAL_MASK) ? 0 : (((addrmap[8] >> 8)
  1067. & BANKGRP_MAX_VAL_MASK) + BANKGRP_B1_BASE);
  1068. }
  1069. static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap)
  1070. {
  1071. priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) ==
  1072. RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] &
  1073. RANK_MAX_VAL_MASK) + RANK_B0_BASE);
  1074. }
  1075. /**
  1076. * setup_address_map - Set Address Map by querying ADDRMAP registers.
  1077. * @priv: DDR memory controller private instance data.
  1078. *
  1079. * Set Address Map by querying ADDRMAP registers.
  1080. *
  1081. * Return: none.
  1082. */
  1083. static void setup_address_map(struct synps_edac_priv *priv)
  1084. {
  1085. u32 addrmap[12];
  1086. int index;
  1087. for (index = 0; index < 12; index++) {
  1088. u32 addrmap_offset;
  1089. addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4);
  1090. addrmap[index] = readl(priv->baseaddr + addrmap_offset);
  1091. }
  1092. setup_row_address_map(priv, addrmap);
  1093. setup_column_address_map(priv, addrmap);
  1094. setup_bank_address_map(priv, addrmap);
  1095. setup_bg_address_map(priv, addrmap);
  1096. setup_rank_address_map(priv, addrmap);
  1097. }
  1098. #endif /* CONFIG_EDAC_DEBUG */
  1099. /**
  1100. * mc_probe - Check controller and bind driver.
  1101. * @pdev: platform device.
  1102. *
  1103. * Probe a specific controller instance for binding with the driver.
  1104. *
  1105. * Return: 0 if the controller instance was successfully bound to the
  1106. * driver; otherwise, < 0 on error.
  1107. */
  1108. static int mc_probe(struct platform_device *pdev)
  1109. {
  1110. const struct synps_platform_data *p_data;
  1111. struct edac_mc_layer layers[2];
  1112. struct synps_edac_priv *priv;
  1113. struct mem_ctl_info *mci;
  1114. void __iomem *baseaddr;
  1115. struct resource *res;
  1116. int rc;
  1117. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1118. baseaddr = devm_ioremap_resource(&pdev->dev, res);
  1119. if (IS_ERR(baseaddr))
  1120. return PTR_ERR(baseaddr);
  1121. p_data = of_device_get_match_data(&pdev->dev);
  1122. if (!p_data)
  1123. return -ENODEV;
  1124. if (!p_data->get_ecc_state(baseaddr)) {
  1125. edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n");
  1126. return -ENXIO;
  1127. }
  1128. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  1129. layers[0].size = SYNPS_EDAC_NR_CSROWS;
  1130. layers[0].is_virt_csrow = true;
  1131. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  1132. layers[1].size = SYNPS_EDAC_NR_CHANS;
  1133. layers[1].is_virt_csrow = false;
  1134. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
  1135. sizeof(struct synps_edac_priv));
  1136. if (!mci) {
  1137. edac_printk(KERN_ERR, EDAC_MC,
  1138. "Failed memory allocation for mc instance\n");
  1139. return -ENOMEM;
  1140. }
  1141. priv = mci->pvt_info;
  1142. priv->baseaddr = baseaddr;
  1143. priv->p_data = p_data;
  1144. mc_init(mci, pdev);
  1145. if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
  1146. rc = setup_irq(mci, pdev);
  1147. if (rc)
  1148. goto free_edac_mc;
  1149. }
  1150. rc = edac_mc_add_mc(mci);
  1151. if (rc) {
  1152. edac_printk(KERN_ERR, EDAC_MC,
  1153. "Failed to register with EDAC core\n");
  1154. goto free_edac_mc;
  1155. }
  1156. #ifdef CONFIG_EDAC_DEBUG
  1157. if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) {
  1158. if (edac_create_sysfs_attributes(mci)) {
  1159. edac_printk(KERN_ERR, EDAC_MC,
  1160. "Failed to create sysfs entries\n");
  1161. goto free_edac_mc;
  1162. }
  1163. }
  1164. if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
  1165. setup_address_map(priv);
  1166. #endif
  1167. /*
  1168. * Start capturing the correctable and uncorrectable errors. A write of
  1169. * 0 starts the counters.
  1170. */
  1171. if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
  1172. writel(0x0, baseaddr + ECC_CTRL_OFST);
  1173. return rc;
  1174. free_edac_mc:
  1175. edac_mc_free(mci);
  1176. return rc;
  1177. }
  1178. /**
  1179. * mc_remove - Unbind driver from controller.
  1180. * @pdev: Platform device.
  1181. *
  1182. * Return: Unconditionally 0
  1183. */
  1184. static int mc_remove(struct platform_device *pdev)
  1185. {
  1186. struct mem_ctl_info *mci = platform_get_drvdata(pdev);
  1187. struct synps_edac_priv *priv = mci->pvt_info;
  1188. if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
  1189. disable_intr(priv);
  1190. #ifdef CONFIG_EDAC_DEBUG
  1191. if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT)
  1192. edac_remove_sysfs_attributes(mci);
  1193. #endif
  1194. edac_mc_del_mc(&pdev->dev);
  1195. edac_mc_free(mci);
  1196. return 0;
  1197. }
  1198. static struct platform_driver synps_edac_mc_driver = {
  1199. .driver = {
  1200. .name = "synopsys-edac",
  1201. .of_match_table = synps_edac_match,
  1202. },
  1203. .probe = mc_probe,
  1204. .remove = mc_remove,
  1205. };
  1206. module_platform_driver(synps_edac_mc_driver);
  1207. MODULE_AUTHOR("Xilinx Inc");
  1208. MODULE_DESCRIPTION("Synopsys DDR ECC driver");
  1209. MODULE_LICENSE("GPL v2");