skx_common.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. *
  4. * Shared code by both skx_edac and i10nm_edac. Originally split out
  5. * from the skx_edac driver.
  6. *
  7. * This file is linked into both skx_edac and i10nm_edac drivers. In
  8. * order to avoid link errors, this file must be like a pure library
  9. * without including symbols and defines which would otherwise conflict,
  10. * when linked once into a module and into a built-in object, at the
  11. * same time. For example, __this_module symbol references when that
  12. * file is being linked into a built-in object.
  13. *
  14. * Copyright (c) 2018, Intel Corporation.
  15. */
  16. #include <linux/acpi.h>
  17. #include <linux/dmi.h>
  18. #include <linux/adxl.h>
  19. #include <acpi/nfit.h>
  20. #include <asm/mce.h>
  21. #include "edac_module.h"
  22. #include "skx_common.h"
  23. static const char * const component_names[] = {
  24. [INDEX_SOCKET] = "ProcessorSocketId",
  25. [INDEX_MEMCTRL] = "MemoryControllerId",
  26. [INDEX_CHANNEL] = "ChannelId",
  27. [INDEX_DIMM] = "DimmSlotId",
  28. };
  29. static int component_indices[ARRAY_SIZE(component_names)];
  30. static int adxl_component_count;
  31. static const char * const *adxl_component_names;
  32. static u64 *adxl_values;
  33. static char *adxl_msg;
  34. static char skx_msg[MSG_SIZE];
  35. static skx_decode_f skx_decode;
  36. static skx_show_retry_log_f skx_show_retry_rd_err_log;
  37. static u64 skx_tolm, skx_tohm;
  38. static LIST_HEAD(dev_edac_list);
  39. int __init skx_adxl_get(void)
  40. {
  41. const char * const *names;
  42. int i, j;
  43. names = adxl_get_component_names();
  44. if (!names) {
  45. skx_printk(KERN_NOTICE, "No firmware support for address translation.\n");
  46. return -ENODEV;
  47. }
  48. for (i = 0; i < INDEX_MAX; i++) {
  49. for (j = 0; names[j]; j++) {
  50. if (!strcmp(component_names[i], names[j])) {
  51. component_indices[i] = j;
  52. break;
  53. }
  54. }
  55. if (!names[j])
  56. goto err;
  57. }
  58. adxl_component_names = names;
  59. while (*names++)
  60. adxl_component_count++;
  61. adxl_values = kcalloc(adxl_component_count, sizeof(*adxl_values),
  62. GFP_KERNEL);
  63. if (!adxl_values) {
  64. adxl_component_count = 0;
  65. return -ENOMEM;
  66. }
  67. adxl_msg = kzalloc(MSG_SIZE, GFP_KERNEL);
  68. if (!adxl_msg) {
  69. adxl_component_count = 0;
  70. kfree(adxl_values);
  71. return -ENOMEM;
  72. }
  73. return 0;
  74. err:
  75. skx_printk(KERN_ERR, "'%s' is not matched from DSM parameters: ",
  76. component_names[i]);
  77. for (j = 0; names[j]; j++)
  78. skx_printk(KERN_CONT, "%s ", names[j]);
  79. skx_printk(KERN_CONT, "\n");
  80. return -ENODEV;
  81. }
  82. void __exit skx_adxl_put(void)
  83. {
  84. kfree(adxl_values);
  85. kfree(adxl_msg);
  86. }
  87. static bool skx_adxl_decode(struct decoded_addr *res)
  88. {
  89. struct skx_dev *d;
  90. int i, len = 0;
  91. if (res->addr >= skx_tohm || (res->addr >= skx_tolm &&
  92. res->addr < BIT_ULL(32))) {
  93. edac_dbg(0, "Address 0x%llx out of range\n", res->addr);
  94. return false;
  95. }
  96. if (adxl_decode(res->addr, adxl_values)) {
  97. edac_dbg(0, "Failed to decode 0x%llx\n", res->addr);
  98. return false;
  99. }
  100. res->socket = (int)adxl_values[component_indices[INDEX_SOCKET]];
  101. res->imc = (int)adxl_values[component_indices[INDEX_MEMCTRL]];
  102. res->channel = (int)adxl_values[component_indices[INDEX_CHANNEL]];
  103. res->dimm = (int)adxl_values[component_indices[INDEX_DIMM]];
  104. if (res->imc > NUM_IMC - 1) {
  105. skx_printk(KERN_ERR, "Bad imc %d\n", res->imc);
  106. return false;
  107. }
  108. list_for_each_entry(d, &dev_edac_list, list) {
  109. if (d->imc[0].src_id == res->socket) {
  110. res->dev = d;
  111. break;
  112. }
  113. }
  114. if (!res->dev) {
  115. skx_printk(KERN_ERR, "No device for src_id %d imc %d\n",
  116. res->socket, res->imc);
  117. return false;
  118. }
  119. for (i = 0; i < adxl_component_count; i++) {
  120. if (adxl_values[i] == ~0x0ull)
  121. continue;
  122. len += snprintf(adxl_msg + len, MSG_SIZE - len, " %s:0x%llx",
  123. adxl_component_names[i], adxl_values[i]);
  124. if (MSG_SIZE - len <= 0)
  125. break;
  126. }
  127. return true;
  128. }
  129. void skx_set_decode(skx_decode_f decode, skx_show_retry_log_f show_retry_log)
  130. {
  131. skx_decode = decode;
  132. skx_show_retry_rd_err_log = show_retry_log;
  133. }
  134. int skx_get_src_id(struct skx_dev *d, int off, u8 *id)
  135. {
  136. u32 reg;
  137. if (pci_read_config_dword(d->util_all, off, &reg)) {
  138. skx_printk(KERN_ERR, "Failed to read src id\n");
  139. return -ENODEV;
  140. }
  141. *id = GET_BITFIELD(reg, 12, 14);
  142. return 0;
  143. }
  144. int skx_get_node_id(struct skx_dev *d, u8 *id)
  145. {
  146. u32 reg;
  147. if (pci_read_config_dword(d->util_all, 0xf4, &reg)) {
  148. skx_printk(KERN_ERR, "Failed to read node id\n");
  149. return -ENODEV;
  150. }
  151. *id = GET_BITFIELD(reg, 0, 2);
  152. return 0;
  153. }
  154. static int get_width(u32 mtr)
  155. {
  156. switch (GET_BITFIELD(mtr, 8, 9)) {
  157. case 0:
  158. return DEV_X4;
  159. case 1:
  160. return DEV_X8;
  161. case 2:
  162. return DEV_X16;
  163. }
  164. return DEV_UNKNOWN;
  165. }
  166. /*
  167. * We use the per-socket device @cfg->did to count how many sockets are present,
  168. * and to detemine which PCI buses are associated with each socket. Allocate
  169. * and build the full list of all the skx_dev structures that we need here.
  170. */
  171. int skx_get_all_bus_mappings(struct res_config *cfg, struct list_head **list)
  172. {
  173. struct pci_dev *pdev, *prev;
  174. struct skx_dev *d;
  175. u32 reg;
  176. int ndev = 0;
  177. prev = NULL;
  178. for (;;) {
  179. pdev = pci_get_device(PCI_VENDOR_ID_INTEL, cfg->decs_did, prev);
  180. if (!pdev)
  181. break;
  182. ndev++;
  183. d = kzalloc(sizeof(*d), GFP_KERNEL);
  184. if (!d) {
  185. pci_dev_put(pdev);
  186. return -ENOMEM;
  187. }
  188. if (pci_read_config_dword(pdev, cfg->busno_cfg_offset, &reg)) {
  189. kfree(d);
  190. pci_dev_put(pdev);
  191. skx_printk(KERN_ERR, "Failed to read bus idx\n");
  192. return -ENODEV;
  193. }
  194. d->bus[0] = GET_BITFIELD(reg, 0, 7);
  195. d->bus[1] = GET_BITFIELD(reg, 8, 15);
  196. if (cfg->type == SKX) {
  197. d->seg = pci_domain_nr(pdev->bus);
  198. d->bus[2] = GET_BITFIELD(reg, 16, 23);
  199. d->bus[3] = GET_BITFIELD(reg, 24, 31);
  200. } else {
  201. d->seg = GET_BITFIELD(reg, 16, 23);
  202. }
  203. edac_dbg(2, "busses: 0x%x, 0x%x, 0x%x, 0x%x\n",
  204. d->bus[0], d->bus[1], d->bus[2], d->bus[3]);
  205. list_add_tail(&d->list, &dev_edac_list);
  206. prev = pdev;
  207. }
  208. if (list)
  209. *list = &dev_edac_list;
  210. return ndev;
  211. }
  212. int skx_get_hi_lo(unsigned int did, int off[], u64 *tolm, u64 *tohm)
  213. {
  214. struct pci_dev *pdev;
  215. u32 reg;
  216. pdev = pci_get_device(PCI_VENDOR_ID_INTEL, did, NULL);
  217. if (!pdev) {
  218. edac_dbg(2, "Can't get tolm/tohm\n");
  219. return -ENODEV;
  220. }
  221. if (pci_read_config_dword(pdev, off[0], &reg)) {
  222. skx_printk(KERN_ERR, "Failed to read tolm\n");
  223. goto fail;
  224. }
  225. skx_tolm = reg;
  226. if (pci_read_config_dword(pdev, off[1], &reg)) {
  227. skx_printk(KERN_ERR, "Failed to read lower tohm\n");
  228. goto fail;
  229. }
  230. skx_tohm = reg;
  231. if (pci_read_config_dword(pdev, off[2], &reg)) {
  232. skx_printk(KERN_ERR, "Failed to read upper tohm\n");
  233. goto fail;
  234. }
  235. skx_tohm |= (u64)reg << 32;
  236. pci_dev_put(pdev);
  237. *tolm = skx_tolm;
  238. *tohm = skx_tohm;
  239. edac_dbg(2, "tolm = 0x%llx tohm = 0x%llx\n", skx_tolm, skx_tohm);
  240. return 0;
  241. fail:
  242. pci_dev_put(pdev);
  243. return -ENODEV;
  244. }
  245. static int skx_get_dimm_attr(u32 reg, int lobit, int hibit, int add,
  246. int minval, int maxval, const char *name)
  247. {
  248. u32 val = GET_BITFIELD(reg, lobit, hibit);
  249. if (val < minval || val > maxval) {
  250. edac_dbg(2, "bad %s = %d (raw=0x%x)\n", name, val, reg);
  251. return -EINVAL;
  252. }
  253. return val + add;
  254. }
  255. #define numrank(reg) skx_get_dimm_attr(reg, 12, 13, 0, 0, 2, "ranks")
  256. #define numrow(reg) skx_get_dimm_attr(reg, 2, 4, 12, 1, 6, "rows")
  257. #define numcol(reg) skx_get_dimm_attr(reg, 0, 1, 10, 0, 2, "cols")
  258. int skx_get_dimm_info(u32 mtr, u32 mcmtr, u32 amap, struct dimm_info *dimm,
  259. struct skx_imc *imc, int chan, int dimmno)
  260. {
  261. int banks = 16, ranks, rows, cols, npages;
  262. u64 size;
  263. ranks = numrank(mtr);
  264. rows = numrow(mtr);
  265. cols = numcol(mtr);
  266. /*
  267. * Compute size in 8-byte (2^3) words, then shift to MiB (2^20)
  268. */
  269. size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3);
  270. npages = MiB_TO_PAGES(size);
  271. edac_dbg(0, "mc#%d: channel %d, dimm %d, %lld MiB (%d pages) bank: %d, rank: %d, row: 0x%x, col: 0x%x\n",
  272. imc->mc, chan, dimmno, size, npages,
  273. banks, 1 << ranks, rows, cols);
  274. imc->chan[chan].dimms[dimmno].close_pg = GET_BITFIELD(mcmtr, 0, 0);
  275. imc->chan[chan].dimms[dimmno].bank_xor_enable = GET_BITFIELD(mcmtr, 9, 9);
  276. imc->chan[chan].dimms[dimmno].fine_grain_bank = GET_BITFIELD(amap, 0, 0);
  277. imc->chan[chan].dimms[dimmno].rowbits = rows;
  278. imc->chan[chan].dimms[dimmno].colbits = cols;
  279. dimm->nr_pages = npages;
  280. dimm->grain = 32;
  281. dimm->dtype = get_width(mtr);
  282. dimm->mtype = MEM_DDR4;
  283. dimm->edac_mode = EDAC_SECDED; /* likely better than this */
  284. snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
  285. imc->src_id, imc->lmc, chan, dimmno);
  286. return 1;
  287. }
  288. int skx_get_nvdimm_info(struct dimm_info *dimm, struct skx_imc *imc,
  289. int chan, int dimmno, const char *mod_str)
  290. {
  291. int smbios_handle;
  292. u32 dev_handle;
  293. u16 flags;
  294. u64 size = 0;
  295. dev_handle = ACPI_NFIT_BUILD_DEVICE_HANDLE(dimmno, chan, imc->lmc,
  296. imc->src_id, 0);
  297. smbios_handle = nfit_get_smbios_id(dev_handle, &flags);
  298. if (smbios_handle == -EOPNOTSUPP) {
  299. pr_warn_once("%s: Can't find size of NVDIMM. Try enabling CONFIG_ACPI_NFIT\n", mod_str);
  300. goto unknown_size;
  301. }
  302. if (smbios_handle < 0) {
  303. skx_printk(KERN_ERR, "Can't find handle for NVDIMM ADR=0x%x\n", dev_handle);
  304. goto unknown_size;
  305. }
  306. if (flags & ACPI_NFIT_MEM_MAP_FAILED) {
  307. skx_printk(KERN_ERR, "NVDIMM ADR=0x%x is not mapped\n", dev_handle);
  308. goto unknown_size;
  309. }
  310. size = dmi_memdev_size(smbios_handle);
  311. if (size == ~0ull)
  312. skx_printk(KERN_ERR, "Can't find size for NVDIMM ADR=0x%x/SMBIOS=0x%x\n",
  313. dev_handle, smbios_handle);
  314. unknown_size:
  315. dimm->nr_pages = size >> PAGE_SHIFT;
  316. dimm->grain = 32;
  317. dimm->dtype = DEV_UNKNOWN;
  318. dimm->mtype = MEM_NVDIMM;
  319. dimm->edac_mode = EDAC_SECDED; /* likely better than this */
  320. edac_dbg(0, "mc#%d: channel %d, dimm %d, %llu MiB (%u pages)\n",
  321. imc->mc, chan, dimmno, size >> 20, dimm->nr_pages);
  322. snprintf(dimm->label, sizeof(dimm->label), "CPU_SrcID#%u_MC#%u_Chan#%u_DIMM#%u",
  323. imc->src_id, imc->lmc, chan, dimmno);
  324. return (size == 0 || size == ~0ull) ? 0 : 1;
  325. }
  326. int skx_register_mci(struct skx_imc *imc, struct pci_dev *pdev,
  327. const char *ctl_name, const char *mod_str,
  328. get_dimm_config_f get_dimm_config)
  329. {
  330. struct mem_ctl_info *mci;
  331. struct edac_mc_layer layers[2];
  332. struct skx_pvt *pvt;
  333. int rc;
  334. /* Allocate a new MC control structure */
  335. layers[0].type = EDAC_MC_LAYER_CHANNEL;
  336. layers[0].size = NUM_CHANNELS;
  337. layers[0].is_virt_csrow = false;
  338. layers[1].type = EDAC_MC_LAYER_SLOT;
  339. layers[1].size = NUM_DIMMS;
  340. layers[1].is_virt_csrow = true;
  341. mci = edac_mc_alloc(imc->mc, ARRAY_SIZE(layers), layers,
  342. sizeof(struct skx_pvt));
  343. if (unlikely(!mci))
  344. return -ENOMEM;
  345. edac_dbg(0, "MC#%d: mci = %p\n", imc->mc, mci);
  346. /* Associate skx_dev and mci for future usage */
  347. imc->mci = mci;
  348. pvt = mci->pvt_info;
  349. pvt->imc = imc;
  350. mci->ctl_name = kasprintf(GFP_KERNEL, "%s#%d IMC#%d", ctl_name,
  351. imc->node_id, imc->lmc);
  352. if (!mci->ctl_name) {
  353. rc = -ENOMEM;
  354. goto fail0;
  355. }
  356. mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_NVDIMM;
  357. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  358. mci->edac_cap = EDAC_FLAG_NONE;
  359. mci->mod_name = mod_str;
  360. mci->dev_name = pci_name(pdev);
  361. mci->ctl_page_to_phys = NULL;
  362. rc = get_dimm_config(mci);
  363. if (rc < 0)
  364. goto fail;
  365. /* Record ptr to the generic device */
  366. mci->pdev = &pdev->dev;
  367. /* Add this new MC control structure to EDAC's list of MCs */
  368. if (unlikely(edac_mc_add_mc(mci))) {
  369. edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
  370. rc = -EINVAL;
  371. goto fail;
  372. }
  373. return 0;
  374. fail:
  375. kfree(mci->ctl_name);
  376. fail0:
  377. edac_mc_free(mci);
  378. imc->mci = NULL;
  379. return rc;
  380. }
  381. static void skx_unregister_mci(struct skx_imc *imc)
  382. {
  383. struct mem_ctl_info *mci = imc->mci;
  384. if (!mci)
  385. return;
  386. edac_dbg(0, "MC%d: mci = %p\n", imc->mc, mci);
  387. /* Remove MC sysfs nodes */
  388. edac_mc_del_mc(mci->pdev);
  389. edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
  390. kfree(mci->ctl_name);
  391. edac_mc_free(mci);
  392. }
  393. static void skx_mce_output_error(struct mem_ctl_info *mci,
  394. const struct mce *m,
  395. struct decoded_addr *res)
  396. {
  397. enum hw_event_mc_err_type tp_event;
  398. char *optype;
  399. bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
  400. bool overflow = GET_BITFIELD(m->status, 62, 62);
  401. bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
  402. bool recoverable;
  403. int len;
  404. u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
  405. u32 mscod = GET_BITFIELD(m->status, 16, 31);
  406. u32 errcode = GET_BITFIELD(m->status, 0, 15);
  407. u32 optypenum = GET_BITFIELD(m->status, 4, 6);
  408. recoverable = GET_BITFIELD(m->status, 56, 56);
  409. if (uncorrected_error) {
  410. core_err_cnt = 1;
  411. if (ripv) {
  412. tp_event = HW_EVENT_ERR_UNCORRECTED;
  413. } else {
  414. tp_event = HW_EVENT_ERR_FATAL;
  415. }
  416. } else {
  417. tp_event = HW_EVENT_ERR_CORRECTED;
  418. }
  419. /*
  420. * According to Intel Architecture spec vol 3B,
  421. * Table 15-10 "IA32_MCi_Status [15:0] Compound Error Code Encoding"
  422. * memory errors should fit one of these masks:
  423. * 000f 0000 1mmm cccc (binary)
  424. * 000f 0010 1mmm cccc (binary) [RAM used as cache]
  425. * where:
  426. * f = Correction Report Filtering Bit. If 1, subsequent errors
  427. * won't be shown
  428. * mmm = error type
  429. * cccc = channel
  430. * If the mask doesn't match, report an error to the parsing logic
  431. */
  432. if (!((errcode & 0xef80) == 0x80 || (errcode & 0xef80) == 0x280)) {
  433. optype = "Can't parse: it is not a mem";
  434. } else {
  435. switch (optypenum) {
  436. case 0:
  437. optype = "generic undef request error";
  438. break;
  439. case 1:
  440. optype = "memory read error";
  441. break;
  442. case 2:
  443. optype = "memory write error";
  444. break;
  445. case 3:
  446. optype = "addr/cmd error";
  447. break;
  448. case 4:
  449. optype = "memory scrubbing error";
  450. break;
  451. default:
  452. optype = "reserved";
  453. break;
  454. }
  455. }
  456. if (adxl_component_count) {
  457. len = snprintf(skx_msg, MSG_SIZE, "%s%s err_code:0x%04x:0x%04x %s",
  458. overflow ? " OVERFLOW" : "",
  459. (uncorrected_error && recoverable) ? " recoverable" : "",
  460. mscod, errcode, adxl_msg);
  461. } else {
  462. len = snprintf(skx_msg, MSG_SIZE,
  463. "%s%s err_code:0x%04x:0x%04x socket:%d imc:%d rank:%d bg:%d ba:%d row:0x%x col:0x%x",
  464. overflow ? " OVERFLOW" : "",
  465. (uncorrected_error && recoverable) ? " recoverable" : "",
  466. mscod, errcode,
  467. res->socket, res->imc, res->rank,
  468. res->bank_group, res->bank_address, res->row, res->column);
  469. }
  470. if (skx_show_retry_rd_err_log)
  471. skx_show_retry_rd_err_log(res, skx_msg + len, MSG_SIZE - len);
  472. edac_dbg(0, "%s\n", skx_msg);
  473. /* Call the helper to output message */
  474. edac_mc_handle_error(tp_event, mci, core_err_cnt,
  475. m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0,
  476. res->channel, res->dimm, -1,
  477. optype, skx_msg);
  478. }
  479. int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
  480. void *data)
  481. {
  482. struct mce *mce = (struct mce *)data;
  483. struct decoded_addr res;
  484. struct mem_ctl_info *mci;
  485. char *type;
  486. if (mce->kflags & MCE_HANDLED_CEC)
  487. return NOTIFY_DONE;
  488. /* ignore unless this is memory related with an address */
  489. if ((mce->status & 0xefff) >> 7 != 1 || !(mce->status & MCI_STATUS_ADDRV))
  490. return NOTIFY_DONE;
  491. memset(&res, 0, sizeof(res));
  492. res.addr = mce->addr;
  493. if (adxl_component_count) {
  494. if (!skx_adxl_decode(&res))
  495. return NOTIFY_DONE;
  496. } else if (!skx_decode || !skx_decode(&res)) {
  497. return NOTIFY_DONE;
  498. }
  499. mci = res.dev->imc[res.imc].mci;
  500. if (!mci)
  501. return NOTIFY_DONE;
  502. if (mce->mcgstatus & MCG_STATUS_MCIP)
  503. type = "Exception";
  504. else
  505. type = "Event";
  506. skx_mc_printk(mci, KERN_DEBUG, "HANDLING MCE MEMORY ERROR\n");
  507. skx_mc_printk(mci, KERN_DEBUG, "CPU %d: Machine Check %s: 0x%llx "
  508. "Bank %d: 0x%llx\n", mce->extcpu, type,
  509. mce->mcgstatus, mce->bank, mce->status);
  510. skx_mc_printk(mci, KERN_DEBUG, "TSC 0x%llx ", mce->tsc);
  511. skx_mc_printk(mci, KERN_DEBUG, "ADDR 0x%llx ", mce->addr);
  512. skx_mc_printk(mci, KERN_DEBUG, "MISC 0x%llx ", mce->misc);
  513. skx_mc_printk(mci, KERN_DEBUG, "PROCESSOR %u:0x%x TIME %llu SOCKET "
  514. "%u APIC 0x%x\n", mce->cpuvendor, mce->cpuid,
  515. mce->time, mce->socketid, mce->apicid);
  516. skx_mce_output_error(mci, mce, &res);
  517. mce->kflags |= MCE_HANDLED_EDAC;
  518. return NOTIFY_DONE;
  519. }
  520. void skx_remove(void)
  521. {
  522. int i, j;
  523. struct skx_dev *d, *tmp;
  524. edac_dbg(0, "\n");
  525. list_for_each_entry_safe(d, tmp, &dev_edac_list, list) {
  526. list_del(&d->list);
  527. for (i = 0; i < NUM_IMC; i++) {
  528. if (d->imc[i].mci)
  529. skx_unregister_mci(&d->imc[i]);
  530. if (d->imc[i].mdev)
  531. pci_dev_put(d->imc[i].mdev);
  532. if (d->imc[i].mbase)
  533. iounmap(d->imc[i].mbase);
  534. for (j = 0; j < NUM_CHANNELS; j++) {
  535. if (d->imc[i].chan[j].cdev)
  536. pci_dev_put(d->imc[i].chan[j].cdev);
  537. }
  538. }
  539. if (d->util_all)
  540. pci_dev_put(d->util_all);
  541. if (d->sad_all)
  542. pci_dev_put(d->sad_all);
  543. if (d->uracu)
  544. pci_dev_put(d->uracu);
  545. kfree(d);
  546. }
  547. }