r82600_edac.c 12 KB

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  1. /*
  2. * Radisys 82600 Embedded chipset Memory Controller kernel module
  3. * (C) 2005 EADS Astrium
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License.
  6. *
  7. * Written by Tim Small <tim@buttersideup.com>, based on work by Thayne
  8. * Harbaugh, Dan Hollis <goemon at anime dot net> and others.
  9. *
  10. * $Id: edac_r82600.c,v 1.1.2.6 2005/10/05 00:43:44 dsp_llnl Exp $
  11. *
  12. * Written with reference to 82600 High Integration Dual PCI System
  13. * Controller Data Book:
  14. * www.radisys.com/files/support_downloads/007-01277-0002.82600DataBook.pdf
  15. * references to this document given in []
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/pci.h>
  20. #include <linux/pci_ids.h>
  21. #include <linux/edac.h>
  22. #include "edac_module.h"
  23. #define EDAC_MOD_STR "r82600_edac"
  24. #define r82600_printk(level, fmt, arg...) \
  25. edac_printk(level, "r82600", fmt, ##arg)
  26. #define r82600_mc_printk(mci, level, fmt, arg...) \
  27. edac_mc_chipset_printk(mci, level, "r82600", fmt, ##arg)
  28. /* Radisys say "The 82600 integrates a main memory SDRAM controller that
  29. * supports up to four banks of memory. The four banks can support a mix of
  30. * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
  31. * each of which can be any size from 16MB to 512MB. Both registered (control
  32. * signals buffered) and unbuffered DIMM types are supported. Mixing of
  33. * registered and unbuffered DIMMs as well as mixing of ECC and non-ECC DIMMs
  34. * is not allowed. The 82600 SDRAM interface operates at the same frequency as
  35. * the CPU bus, 66MHz, 100MHz or 133MHz."
  36. */
  37. #define R82600_NR_CSROWS 4
  38. #define R82600_NR_CHANS 1
  39. #define R82600_NR_DIMMS 4
  40. #define R82600_BRIDGE_ID 0x8200
  41. /* Radisys 82600 register addresses - device 0 function 0 - PCI bridge */
  42. #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
  43. * all bits are R/W
  44. *
  45. * 7 SDRAM ISA Hole Enable
  46. * 6 Flash Page Mode Enable
  47. * 5 ECC Enable: 1=ECC 0=noECC
  48. * 4 DRAM DIMM Type: 1=
  49. * 3 BIOS Alias Disable
  50. * 2 SDRAM BIOS Flash Write Enable
  51. * 1:0 SDRAM Refresh Rate: 00=Disabled
  52. * 01=7.8usec (256Mbit SDRAMs)
  53. * 10=15.6us 11=125usec
  54. */
  55. #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
  56. * More SDRAM related control bits
  57. * all bits are R/W
  58. *
  59. * 15:8 Reserved.
  60. *
  61. * 7:5 Special SDRAM Mode Select
  62. *
  63. * 4 Force ECC
  64. *
  65. * 1=Drive ECC bits to 0 during
  66. * write cycles (i.e. ECC test mode)
  67. *
  68. * 0=Normal ECC functioning
  69. *
  70. * 3 Enhanced Paging Enable
  71. *
  72. * 2 CAS# Latency 0=3clks 1=2clks
  73. *
  74. * 1 RAS# to CAS# Delay 0=3 1=2
  75. *
  76. * 0 RAS# Precharge 0=3 1=2
  77. */
  78. #define R82600_EAP 0x80 /* ECC Error Address Pointer Register
  79. *
  80. * 31 Disable Hardware Scrubbing (RW)
  81. * 0=Scrub on corrected read
  82. * 1=Don't scrub on corrected read
  83. *
  84. * 30:12 Error Address Pointer (RO)
  85. * Upper 19 bits of error address
  86. *
  87. * 11:4 Syndrome Bits (RO)
  88. *
  89. * 3 BSERR# on multibit error (RW)
  90. * 1=enable 0=disable
  91. *
  92. * 2 NMI on Single Bit Eror (RW)
  93. * 1=NMI triggered by SBE n.b. other
  94. * prerequeists
  95. * 0=NMI not triggered
  96. *
  97. * 1 MBE (R/WC)
  98. * read 1=MBE at EAP (see above)
  99. * read 0=no MBE, or SBE occurred first
  100. * write 1=Clear MBE status (must also
  101. * clear SBE)
  102. * write 0=NOP
  103. *
  104. * 1 SBE (R/WC)
  105. * read 1=SBE at EAP (see above)
  106. * read 0=no SBE, or MBE occurred first
  107. * write 1=Clear SBE status (must also
  108. * clear MBE)
  109. * write 0=NOP
  110. */
  111. #define R82600_DRBA 0x60 /* + 0x60..0x63 SDRAM Row Boundary Address
  112. * Registers
  113. *
  114. * 7:0 Address lines 30:24 - upper limit of
  115. * each row [p57]
  116. */
  117. struct r82600_error_info {
  118. u32 eapr;
  119. };
  120. static bool disable_hardware_scrub;
  121. static struct edac_pci_ctl_info *r82600_pci;
  122. static void r82600_get_error_info(struct mem_ctl_info *mci,
  123. struct r82600_error_info *info)
  124. {
  125. struct pci_dev *pdev;
  126. pdev = to_pci_dev(mci->pdev);
  127. pci_read_config_dword(pdev, R82600_EAP, &info->eapr);
  128. if (info->eapr & BIT(0))
  129. /* Clear error to allow next error to be reported [p.62] */
  130. pci_write_bits32(pdev, R82600_EAP,
  131. ((u32) BIT(0) & (u32) BIT(1)),
  132. ((u32) BIT(0) & (u32) BIT(1)));
  133. if (info->eapr & BIT(1))
  134. /* Clear error to allow next error to be reported [p.62] */
  135. pci_write_bits32(pdev, R82600_EAP,
  136. ((u32) BIT(0) & (u32) BIT(1)),
  137. ((u32) BIT(0) & (u32) BIT(1)));
  138. }
  139. static int r82600_process_error_info(struct mem_ctl_info *mci,
  140. struct r82600_error_info *info,
  141. int handle_errors)
  142. {
  143. int error_found;
  144. u32 eapaddr, page;
  145. u32 syndrome;
  146. error_found = 0;
  147. /* bits 30:12 store the upper 19 bits of the 32 bit error address */
  148. eapaddr = ((info->eapr >> 12) & 0x7FFF) << 13;
  149. /* Syndrome in bits 11:4 [p.62] */
  150. syndrome = (info->eapr >> 4) & 0xFF;
  151. /* the R82600 reports at less than page *
  152. * granularity (upper 19 bits only) */
  153. page = eapaddr >> PAGE_SHIFT;
  154. if (info->eapr & BIT(0)) { /* CE? */
  155. error_found = 1;
  156. if (handle_errors)
  157. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  158. page, 0, syndrome,
  159. edac_mc_find_csrow_by_page(mci, page),
  160. 0, -1,
  161. mci->ctl_name, "");
  162. }
  163. if (info->eapr & BIT(1)) { /* UE? */
  164. error_found = 1;
  165. if (handle_errors)
  166. /* 82600 doesn't give enough info */
  167. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  168. page, 0, 0,
  169. edac_mc_find_csrow_by_page(mci, page),
  170. 0, -1,
  171. mci->ctl_name, "");
  172. }
  173. return error_found;
  174. }
  175. static void r82600_check(struct mem_ctl_info *mci)
  176. {
  177. struct r82600_error_info info;
  178. edac_dbg(1, "MC%d\n", mci->mc_idx);
  179. r82600_get_error_info(mci, &info);
  180. r82600_process_error_info(mci, &info, 1);
  181. }
  182. static inline int ecc_enabled(u8 dramcr)
  183. {
  184. return dramcr & BIT(5);
  185. }
  186. static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
  187. u8 dramcr)
  188. {
  189. struct csrow_info *csrow;
  190. struct dimm_info *dimm;
  191. int index;
  192. u8 drbar; /* SDRAM Row Boundary Address Register */
  193. u32 row_high_limit, row_high_limit_last;
  194. u32 reg_sdram, ecc_on, row_base;
  195. ecc_on = ecc_enabled(dramcr);
  196. reg_sdram = dramcr & BIT(4);
  197. row_high_limit_last = 0;
  198. for (index = 0; index < mci->nr_csrows; index++) {
  199. csrow = mci->csrows[index];
  200. dimm = csrow->channels[0]->dimm;
  201. /* find the DRAM Chip Select Base address and mask */
  202. pci_read_config_byte(pdev, R82600_DRBA + index, &drbar);
  203. edac_dbg(1, "Row=%d DRBA = %#0x\n", index, drbar);
  204. row_high_limit = ((u32) drbar << 24);
  205. /* row_high_limit = ((u32)drbar << 24) | 0xffffffUL; */
  206. edac_dbg(1, "Row=%d, Boundary Address=%#0x, Last = %#0x\n",
  207. index, row_high_limit, row_high_limit_last);
  208. /* Empty row [p.57] */
  209. if (row_high_limit == row_high_limit_last)
  210. continue;
  211. row_base = row_high_limit_last;
  212. csrow->first_page = row_base >> PAGE_SHIFT;
  213. csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
  214. dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
  215. /* Error address is top 19 bits - so granularity is *
  216. * 14 bits */
  217. dimm->grain = 1 << 14;
  218. dimm->mtype = reg_sdram ? MEM_RDDR : MEM_DDR;
  219. /* FIXME - check that this is unknowable with this chipset */
  220. dimm->dtype = DEV_UNKNOWN;
  221. /* Mode is global on 82600 */
  222. dimm->edac_mode = ecc_on ? EDAC_SECDED : EDAC_NONE;
  223. row_high_limit_last = row_high_limit;
  224. }
  225. }
  226. static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
  227. {
  228. struct mem_ctl_info *mci;
  229. struct edac_mc_layer layers[2];
  230. u8 dramcr;
  231. u32 eapr;
  232. u32 scrub_disabled;
  233. u32 sdram_refresh_rate;
  234. struct r82600_error_info discard;
  235. edac_dbg(0, "\n");
  236. pci_read_config_byte(pdev, R82600_DRAMC, &dramcr);
  237. pci_read_config_dword(pdev, R82600_EAP, &eapr);
  238. scrub_disabled = eapr & BIT(31);
  239. sdram_refresh_rate = dramcr & (BIT(0) | BIT(1));
  240. edac_dbg(2, "sdram refresh rate = %#0x\n", sdram_refresh_rate);
  241. edac_dbg(2, "DRAMC register = %#0x\n", dramcr);
  242. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  243. layers[0].size = R82600_NR_CSROWS;
  244. layers[0].is_virt_csrow = true;
  245. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  246. layers[1].size = R82600_NR_CHANS;
  247. layers[1].is_virt_csrow = false;
  248. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
  249. if (mci == NULL)
  250. return -ENOMEM;
  251. edac_dbg(0, "mci = %p\n", mci);
  252. mci->pdev = &pdev->dev;
  253. mci->mtype_cap = MEM_FLAG_RDDR | MEM_FLAG_DDR;
  254. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  255. /* FIXME try to work out if the chip leads have been used for COM2
  256. * instead on this board? [MA6?] MAYBE:
  257. */
  258. /* On the R82600, the pins for memory bits 72:65 - i.e. the *
  259. * EC bits are shared with the pins for COM2 (!), so if COM2 *
  260. * is enabled, we assume COM2 is wired up, and thus no EDAC *
  261. * is possible. */
  262. mci->edac_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  263. if (ecc_enabled(dramcr)) {
  264. if (scrub_disabled)
  265. edac_dbg(3, "mci = %p - Scrubbing disabled! EAP: %#0x\n",
  266. mci, eapr);
  267. } else
  268. mci->edac_cap = EDAC_FLAG_NONE;
  269. mci->mod_name = EDAC_MOD_STR;
  270. mci->ctl_name = "R82600";
  271. mci->dev_name = pci_name(pdev);
  272. mci->edac_check = r82600_check;
  273. mci->ctl_page_to_phys = NULL;
  274. r82600_init_csrows(mci, pdev, dramcr);
  275. r82600_get_error_info(mci, &discard); /* clear counters */
  276. /* Here we assume that we will never see multiple instances of this
  277. * type of memory controller. The ID is therefore hardcoded to 0.
  278. */
  279. if (edac_mc_add_mc(mci)) {
  280. edac_dbg(3, "failed edac_mc_add_mc()\n");
  281. goto fail;
  282. }
  283. /* get this far and it's successful */
  284. if (disable_hardware_scrub) {
  285. edac_dbg(3, "Disabling Hardware Scrub (scrub on error)\n");
  286. pci_write_bits32(pdev, R82600_EAP, BIT(31), BIT(31));
  287. }
  288. /* allocating generic PCI control info */
  289. r82600_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  290. if (!r82600_pci) {
  291. printk(KERN_WARNING
  292. "%s(): Unable to create PCI control\n",
  293. __func__);
  294. printk(KERN_WARNING
  295. "%s(): PCI error report via EDAC not setup\n",
  296. __func__);
  297. }
  298. edac_dbg(3, "success\n");
  299. return 0;
  300. fail:
  301. edac_mc_free(mci);
  302. return -ENODEV;
  303. }
  304. /* returns count (>= 0), or negative on error */
  305. static int r82600_init_one(struct pci_dev *pdev,
  306. const struct pci_device_id *ent)
  307. {
  308. edac_dbg(0, "\n");
  309. /* don't need to call pci_enable_device() */
  310. return r82600_probe1(pdev, ent->driver_data);
  311. }
  312. static void r82600_remove_one(struct pci_dev *pdev)
  313. {
  314. struct mem_ctl_info *mci;
  315. edac_dbg(0, "\n");
  316. if (r82600_pci)
  317. edac_pci_release_generic_ctl(r82600_pci);
  318. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  319. return;
  320. edac_mc_free(mci);
  321. }
  322. static const struct pci_device_id r82600_pci_tbl[] = {
  323. {
  324. PCI_DEVICE(PCI_VENDOR_ID_RADISYS, R82600_BRIDGE_ID)
  325. },
  326. {
  327. 0,
  328. } /* 0 terminated list. */
  329. };
  330. MODULE_DEVICE_TABLE(pci, r82600_pci_tbl);
  331. static struct pci_driver r82600_driver = {
  332. .name = EDAC_MOD_STR,
  333. .probe = r82600_init_one,
  334. .remove = r82600_remove_one,
  335. .id_table = r82600_pci_tbl,
  336. };
  337. static int __init r82600_init(void)
  338. {
  339. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  340. opstate_init();
  341. return pci_register_driver(&r82600_driver);
  342. }
  343. static void __exit r82600_exit(void)
  344. {
  345. pci_unregister_driver(&r82600_driver);
  346. }
  347. module_init(r82600_init);
  348. module_exit(r82600_exit);
  349. MODULE_LICENSE("GPL");
  350. MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD Ltd. "
  351. "on behalf of EADS Astrium");
  352. MODULE_DESCRIPTION("MC support for Radisys 82600 memory controllers");
  353. module_param(disable_hardware_scrub, bool, 0644);
  354. MODULE_PARM_DESC(disable_hardware_scrub,
  355. "If set, disable the chipset's automatic scrub for CEs");
  356. module_param(edac_op_state, int, 0444);
  357. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");