qcom_edac.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2018, The Linux Foundation. All rights reserved.
  4. */
  5. #include <linux/edac.h>
  6. #include <linux/interrupt.h>
  7. #include <linux/kernel.h>
  8. #include <linux/of.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/regmap.h>
  11. #include <linux/soc/qcom/llcc-qcom.h>
  12. #include "edac_mc.h"
  13. #include "edac_device.h"
  14. #define EDAC_LLCC "qcom_llcc"
  15. #define LLCC_ERP_PANIC_ON_UE 1
  16. #define TRP_SYN_REG_CNT 6
  17. #define DRP_SYN_REG_CNT 8
  18. #define LLCC_COMMON_STATUS0 0x0003000c
  19. #define LLCC_LB_CNT_MASK GENMASK(31, 28)
  20. #define LLCC_LB_CNT_SHIFT 28
  21. /* Single & double bit syndrome register offsets */
  22. #define TRP_ECC_SB_ERR_SYN0 0x0002304c
  23. #define TRP_ECC_DB_ERR_SYN0 0x00020370
  24. #define DRP_ECC_SB_ERR_SYN0 0x0004204c
  25. #define DRP_ECC_DB_ERR_SYN0 0x00042070
  26. /* Error register offsets */
  27. #define TRP_ECC_ERROR_STATUS1 0x00020348
  28. #define TRP_ECC_ERROR_STATUS0 0x00020344
  29. #define DRP_ECC_ERROR_STATUS1 0x00042048
  30. #define DRP_ECC_ERROR_STATUS0 0x00042044
  31. /* TRP, DRP interrupt register offsets */
  32. #define DRP_INTERRUPT_STATUS 0x00041000
  33. #define TRP_INTERRUPT_0_STATUS 0x00020480
  34. #define DRP_INTERRUPT_CLEAR 0x00041008
  35. #define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004
  36. #define TRP_INTERRUPT_0_CLEAR 0x00020484
  37. #define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440
  38. /* Mask and shift macros */
  39. #define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0)
  40. #define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16)
  41. #define ECC_DB_ERR_WAYS_SHIFT BIT(4)
  42. #define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16)
  43. #define ECC_SB_ERR_COUNT_SHIFT BIT(4)
  44. #define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0)
  45. #define SB_ECC_ERROR BIT(0)
  46. #define DB_ECC_ERROR BIT(1)
  47. #define DRP_TRP_INT_CLEAR GENMASK(1, 0)
  48. #define DRP_TRP_CNT_CLEAR GENMASK(1, 0)
  49. /* Config registers offsets*/
  50. #define DRP_ECC_ERROR_CFG 0x00040000
  51. /* Tag RAM, Data RAM interrupt register offsets */
  52. #define CMN_INTERRUPT_0_ENABLE 0x0003001c
  53. #define CMN_INTERRUPT_2_ENABLE 0x0003003c
  54. #define TRP_INTERRUPT_0_ENABLE 0x00020488
  55. #define DRP_INTERRUPT_ENABLE 0x0004100c
  56. #define SB_ERROR_THRESHOLD 0x1
  57. #define SB_ERROR_THRESHOLD_SHIFT 24
  58. #define SB_DB_TRP_INTERRUPT_ENABLE 0x3
  59. #define TRP0_INTERRUPT_ENABLE 0x1
  60. #define DRP0_INTERRUPT_ENABLE BIT(6)
  61. #define SB_DB_DRP_INTERRUPT_ENABLE 0x3
  62. enum {
  63. LLCC_DRAM_CE = 0,
  64. LLCC_DRAM_UE,
  65. LLCC_TRAM_CE,
  66. LLCC_TRAM_UE,
  67. };
  68. static const struct llcc_edac_reg_data edac_reg_data[] = {
  69. [LLCC_DRAM_CE] = {
  70. .name = "DRAM Single-bit",
  71. .synd_reg = DRP_ECC_SB_ERR_SYN0,
  72. .count_status_reg = DRP_ECC_ERROR_STATUS1,
  73. .ways_status_reg = DRP_ECC_ERROR_STATUS0,
  74. .reg_cnt = DRP_SYN_REG_CNT,
  75. .count_mask = ECC_SB_ERR_COUNT_MASK,
  76. .ways_mask = ECC_SB_ERR_WAYS_MASK,
  77. .count_shift = ECC_SB_ERR_COUNT_SHIFT,
  78. },
  79. [LLCC_DRAM_UE] = {
  80. .name = "DRAM Double-bit",
  81. .synd_reg = DRP_ECC_DB_ERR_SYN0,
  82. .count_status_reg = DRP_ECC_ERROR_STATUS1,
  83. .ways_status_reg = DRP_ECC_ERROR_STATUS0,
  84. .reg_cnt = DRP_SYN_REG_CNT,
  85. .count_mask = ECC_DB_ERR_COUNT_MASK,
  86. .ways_mask = ECC_DB_ERR_WAYS_MASK,
  87. .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
  88. },
  89. [LLCC_TRAM_CE] = {
  90. .name = "TRAM Single-bit",
  91. .synd_reg = TRP_ECC_SB_ERR_SYN0,
  92. .count_status_reg = TRP_ECC_ERROR_STATUS1,
  93. .ways_status_reg = TRP_ECC_ERROR_STATUS0,
  94. .reg_cnt = TRP_SYN_REG_CNT,
  95. .count_mask = ECC_SB_ERR_COUNT_MASK,
  96. .ways_mask = ECC_SB_ERR_WAYS_MASK,
  97. .count_shift = ECC_SB_ERR_COUNT_SHIFT,
  98. },
  99. [LLCC_TRAM_UE] = {
  100. .name = "TRAM Double-bit",
  101. .synd_reg = TRP_ECC_DB_ERR_SYN0,
  102. .count_status_reg = TRP_ECC_ERROR_STATUS1,
  103. .ways_status_reg = TRP_ECC_ERROR_STATUS0,
  104. .reg_cnt = TRP_SYN_REG_CNT,
  105. .count_mask = ECC_DB_ERR_COUNT_MASK,
  106. .ways_mask = ECC_DB_ERR_WAYS_MASK,
  107. .ways_shift = ECC_DB_ERR_WAYS_SHIFT,
  108. },
  109. };
  110. static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
  111. {
  112. u32 sb_err_threshold;
  113. int ret;
  114. /*
  115. * Configure interrupt enable registers such that Tag, Data RAM related
  116. * interrupts are propagated to interrupt controller for servicing
  117. */
  118. ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
  119. TRP0_INTERRUPT_ENABLE,
  120. TRP0_INTERRUPT_ENABLE);
  121. if (ret)
  122. return ret;
  123. ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
  124. SB_DB_TRP_INTERRUPT_ENABLE,
  125. SB_DB_TRP_INTERRUPT_ENABLE);
  126. if (ret)
  127. return ret;
  128. sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
  129. ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
  130. sb_err_threshold);
  131. if (ret)
  132. return ret;
  133. ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
  134. DRP0_INTERRUPT_ENABLE,
  135. DRP0_INTERRUPT_ENABLE);
  136. if (ret)
  137. return ret;
  138. ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
  139. SB_DB_DRP_INTERRUPT_ENABLE);
  140. return ret;
  141. }
  142. /* Clear the error interrupt and counter registers */
  143. static int
  144. qcom_llcc_clear_error_status(int err_type, struct llcc_drv_data *drv)
  145. {
  146. int ret = 0;
  147. switch (err_type) {
  148. case LLCC_DRAM_CE:
  149. case LLCC_DRAM_UE:
  150. ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
  151. DRP_TRP_INT_CLEAR);
  152. if (ret)
  153. return ret;
  154. ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
  155. DRP_TRP_CNT_CLEAR);
  156. if (ret)
  157. return ret;
  158. break;
  159. case LLCC_TRAM_CE:
  160. case LLCC_TRAM_UE:
  161. ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
  162. DRP_TRP_INT_CLEAR);
  163. if (ret)
  164. return ret;
  165. ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
  166. DRP_TRP_CNT_CLEAR);
  167. if (ret)
  168. return ret;
  169. break;
  170. default:
  171. ret = -EINVAL;
  172. edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
  173. err_type);
  174. }
  175. return ret;
  176. }
  177. /* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
  178. static int
  179. dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
  180. {
  181. struct llcc_edac_reg_data reg_data = edac_reg_data[err_type];
  182. int err_cnt, err_ways, ret, i;
  183. u32 synd_reg, synd_val;
  184. for (i = 0; i < reg_data.reg_cnt; i++) {
  185. synd_reg = reg_data.synd_reg + (i * 4);
  186. ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
  187. &synd_val);
  188. if (ret)
  189. goto clear;
  190. edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
  191. reg_data.name, i, synd_val);
  192. }
  193. ret = regmap_read(drv->regmap,
  194. drv->offsets[bank] + reg_data.count_status_reg,
  195. &err_cnt);
  196. if (ret)
  197. goto clear;
  198. err_cnt &= reg_data.count_mask;
  199. err_cnt >>= reg_data.count_shift;
  200. edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n",
  201. reg_data.name, err_cnt);
  202. ret = regmap_read(drv->regmap,
  203. drv->offsets[bank] + reg_data.ways_status_reg,
  204. &err_ways);
  205. if (ret)
  206. goto clear;
  207. err_ways &= reg_data.ways_mask;
  208. err_ways >>= reg_data.ways_shift;
  209. edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error ways: 0x%4x\n",
  210. reg_data.name, err_ways);
  211. clear:
  212. return qcom_llcc_clear_error_status(err_type, drv);
  213. }
  214. static int
  215. dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
  216. {
  217. struct llcc_drv_data *drv = edev_ctl->pvt_info;
  218. int ret;
  219. ret = dump_syn_reg_values(drv, bank, err_type);
  220. if (ret)
  221. return ret;
  222. switch (err_type) {
  223. case LLCC_DRAM_CE:
  224. edac_device_handle_ce(edev_ctl, 0, bank,
  225. "LLCC Data RAM correctable Error");
  226. break;
  227. case LLCC_DRAM_UE:
  228. edac_device_handle_ue(edev_ctl, 0, bank,
  229. "LLCC Data RAM uncorrectable Error");
  230. break;
  231. case LLCC_TRAM_CE:
  232. edac_device_handle_ce(edev_ctl, 0, bank,
  233. "LLCC Tag RAM correctable Error");
  234. break;
  235. case LLCC_TRAM_UE:
  236. edac_device_handle_ue(edev_ctl, 0, bank,
  237. "LLCC Tag RAM uncorrectable Error");
  238. break;
  239. default:
  240. ret = -EINVAL;
  241. edac_printk(KERN_CRIT, EDAC_LLCC, "Unexpected error type: %d\n",
  242. err_type);
  243. }
  244. return ret;
  245. }
  246. static irqreturn_t
  247. llcc_ecc_irq_handler(int irq, void *edev_ctl)
  248. {
  249. struct edac_device_ctl_info *edac_dev_ctl = edev_ctl;
  250. struct llcc_drv_data *drv = edac_dev_ctl->pvt_info;
  251. irqreturn_t irq_rc = IRQ_NONE;
  252. u32 drp_error, trp_error, i;
  253. int ret;
  254. /* Iterate over the banks and look for Tag RAM or Data RAM errors */
  255. for (i = 0; i < drv->num_banks; i++) {
  256. ret = regmap_read(drv->regmap,
  257. drv->offsets[i] + DRP_INTERRUPT_STATUS,
  258. &drp_error);
  259. if (!ret && (drp_error & SB_ECC_ERROR)) {
  260. edac_printk(KERN_CRIT, EDAC_LLCC,
  261. "Single Bit Error detected in Data RAM\n");
  262. ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
  263. } else if (!ret && (drp_error & DB_ECC_ERROR)) {
  264. edac_printk(KERN_CRIT, EDAC_LLCC,
  265. "Double Bit Error detected in Data RAM\n");
  266. ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
  267. }
  268. if (!ret)
  269. irq_rc = IRQ_HANDLED;
  270. ret = regmap_read(drv->regmap,
  271. drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
  272. &trp_error);
  273. if (!ret && (trp_error & SB_ECC_ERROR)) {
  274. edac_printk(KERN_CRIT, EDAC_LLCC,
  275. "Single Bit Error detected in Tag RAM\n");
  276. ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
  277. } else if (!ret && (trp_error & DB_ECC_ERROR)) {
  278. edac_printk(KERN_CRIT, EDAC_LLCC,
  279. "Double Bit Error detected in Tag RAM\n");
  280. ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
  281. }
  282. if (!ret)
  283. irq_rc = IRQ_HANDLED;
  284. }
  285. return irq_rc;
  286. }
  287. static int qcom_llcc_edac_probe(struct platform_device *pdev)
  288. {
  289. struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
  290. struct edac_device_ctl_info *edev_ctl;
  291. struct device *dev = &pdev->dev;
  292. int ecc_irq;
  293. int rc;
  294. rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
  295. if (rc)
  296. return rc;
  297. /* Allocate edac control info */
  298. edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
  299. llcc_driv_data->num_banks, 1,
  300. NULL, 0,
  301. edac_device_alloc_index());
  302. if (!edev_ctl)
  303. return -ENOMEM;
  304. edev_ctl->dev = dev;
  305. edev_ctl->mod_name = dev_name(dev);
  306. edev_ctl->dev_name = dev_name(dev);
  307. edev_ctl->ctl_name = "llcc";
  308. edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
  309. edev_ctl->pvt_info = llcc_driv_data;
  310. rc = edac_device_add_device(edev_ctl);
  311. if (rc)
  312. goto out_mem;
  313. platform_set_drvdata(pdev, edev_ctl);
  314. /* Request for ecc irq */
  315. ecc_irq = llcc_driv_data->ecc_irq;
  316. if (ecc_irq < 0) {
  317. rc = -ENODEV;
  318. goto out_dev;
  319. }
  320. rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
  321. IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
  322. if (rc)
  323. goto out_dev;
  324. return rc;
  325. out_dev:
  326. edac_device_del_device(edev_ctl->dev);
  327. out_mem:
  328. edac_device_free_ctl_info(edev_ctl);
  329. return rc;
  330. }
  331. static int qcom_llcc_edac_remove(struct platform_device *pdev)
  332. {
  333. struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
  334. edac_device_del_device(edev_ctl->dev);
  335. edac_device_free_ctl_info(edev_ctl);
  336. return 0;
  337. }
  338. static struct platform_driver qcom_llcc_edac_driver = {
  339. .probe = qcom_llcc_edac_probe,
  340. .remove = qcom_llcc_edac_remove,
  341. .driver = {
  342. .name = "qcom_llcc_edac",
  343. },
  344. };
  345. module_platform_driver(qcom_llcc_edac_driver);
  346. MODULE_DESCRIPTION("QCOM EDAC driver");
  347. MODULE_LICENSE("GPL v2");