ppc4xx_edac.h 7.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2008 Nuovation System Designs, LLC
  4. * Grant Erickson <gerickson@nuovations.com>
  5. *
  6. * This file defines processor mnemonics for accessing and managing
  7. * the IBM DDR1/DDR2 ECC controller found in the 405EX[r], 440SP,
  8. * 440SPe, 460EX, 460GT and 460SX.
  9. */
  10. #ifndef __PPC4XX_EDAC_H
  11. #define __PPC4XX_EDAC_H
  12. #include <linux/types.h>
  13. /*
  14. * Macro for generating register field mnemonics
  15. */
  16. #define PPC_REG_BITS 32
  17. #define PPC_REG_VAL(bit, val) ((val) << ((PPC_REG_BITS - 1) - (bit)))
  18. #define PPC_REG_DECODE(bit, val) ((val) >> ((PPC_REG_BITS - 1) - (bit)))
  19. /*
  20. * IBM 4xx DDR1/DDR2 SDRAM memory controller registers (at least those
  21. * relevant to ECC)
  22. */
  23. #define SDRAM_BESR 0x00 /* Error status (read/clear) */
  24. #define SDRAM_BESRT 0x01 /* Error statuss (test/set) */
  25. #define SDRAM_BEARL 0x02 /* Error address low */
  26. #define SDRAM_BEARH 0x03 /* Error address high */
  27. #define SDRAM_WMIRQ 0x06 /* Write master (read/clear) */
  28. #define SDRAM_WMIRQT 0x07 /* Write master (test/set) */
  29. #define SDRAM_MCOPT1 0x20 /* Controller options 1 */
  30. #define SDRAM_MBXCF_BASE 0x40 /* Bank n configuration base */
  31. #define SDRAM_MBXCF(n) (SDRAM_MBXCF_BASE + (4 * (n)))
  32. #define SDRAM_MB0CF SDRAM_MBXCF(0)
  33. #define SDRAM_MB1CF SDRAM_MBXCF(1)
  34. #define SDRAM_MB2CF SDRAM_MBXCF(2)
  35. #define SDRAM_MB3CF SDRAM_MBXCF(3)
  36. #define SDRAM_ECCCR 0x98 /* ECC error status */
  37. #define SDRAM_ECCES SDRAM_ECCCR
  38. /*
  39. * PLB Master IDs
  40. */
  41. #define SDRAM_PLB_M0ID_FIRST 0
  42. #define SDRAM_PLB_M0ID_ICU SDRAM_PLB_M0ID_FIRST
  43. #define SDRAM_PLB_M0ID_PCIE0 1
  44. #define SDRAM_PLB_M0ID_PCIE1 2
  45. #define SDRAM_PLB_M0ID_DMA 3
  46. #define SDRAM_PLB_M0ID_DCU 4
  47. #define SDRAM_PLB_M0ID_OPB 5
  48. #define SDRAM_PLB_M0ID_MAL 6
  49. #define SDRAM_PLB_M0ID_SEC 7
  50. #define SDRAM_PLB_M0ID_AHB 8
  51. #define SDRAM_PLB_M0ID_LAST SDRAM_PLB_M0ID_AHB
  52. #define SDRAM_PLB_M0ID_COUNT (SDRAM_PLB_M0ID_LAST - \
  53. SDRAM_PLB_M0ID_FIRST + 1)
  54. /*
  55. * Memory Controller Bus Error Status Register
  56. */
  57. #define SDRAM_BESR_MASK PPC_REG_VAL(7, 0xFF)
  58. #define SDRAM_BESR_M0ID_MASK PPC_REG_VAL(3, 0xF)
  59. #define SDRAM_BESR_M0ID_DECODE(n) PPC_REG_DECODE(3, n)
  60. #define SDRAM_BESR_M0ID_ICU PPC_REG_VAL(3, SDRAM_PLB_M0ID_ICU)
  61. #define SDRAM_BESR_M0ID_PCIE0 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE0)
  62. #define SDRAM_BESR_M0ID_PCIE1 PPC_REG_VAL(3, SDRAM_PLB_M0ID_PCIE1)
  63. #define SDRAM_BESR_M0ID_DMA PPC_REG_VAL(3, SDRAM_PLB_M0ID_DMA)
  64. #define SDRAM_BESR_M0ID_DCU PPC_REG_VAL(3, SDRAM_PLB_M0ID_DCU)
  65. #define SDRAM_BESR_M0ID_OPB PPC_REG_VAL(3, SDRAM_PLB_M0ID_OPB)
  66. #define SDRAM_BESR_M0ID_MAL PPC_REG_VAL(3, SDRAM_PLB_M0ID_MAL)
  67. #define SDRAM_BESR_M0ID_SEC PPC_REG_VAL(3, SDRAM_PLB_M0ID_SEC)
  68. #define SDRAM_BESR_M0ID_AHB PPC_REG_VAL(3, SDRAM_PLB_M0ID_AHB)
  69. #define SDRAM_BESR_M0ET_MASK PPC_REG_VAL(6, 0x7)
  70. #define SDRAM_BESR_M0ET_NONE PPC_REG_VAL(6, 0)
  71. #define SDRAM_BESR_M0ET_ECC PPC_REG_VAL(6, 1)
  72. #define SDRAM_BESR_M0RW_MASK PPC_REG_VAL(7, 1)
  73. #define SDRAM_BESR_M0RW_WRITE PPC_REG_VAL(7, 0)
  74. #define SDRAM_BESR_M0RW_READ PPC_REG_VAL(7, 1)
  75. /*
  76. * Memory Controller PLB Write Master Interrupt Register
  77. */
  78. #define SDRAM_WMIRQ_MASK PPC_REG_VAL(8, 0x1FF)
  79. #define SDRAM_WMIRQ_ENCODE(id) PPC_REG_VAL((id % \
  80. SDRAM_PLB_M0ID_COUNT), 1)
  81. #define SDRAM_WMIRQ_ICU PPC_REG_VAL(SDRAM_PLB_M0ID_ICU, 1)
  82. #define SDRAM_WMIRQ_PCIE0 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE0, 1)
  83. #define SDRAM_WMIRQ_PCIE1 PPC_REG_VAL(SDRAM_PLB_M0ID_PCIE1, 1)
  84. #define SDRAM_WMIRQ_DMA PPC_REG_VAL(SDRAM_PLB_M0ID_DMA, 1)
  85. #define SDRAM_WMIRQ_DCU PPC_REG_VAL(SDRAM_PLB_M0ID_DCU, 1)
  86. #define SDRAM_WMIRQ_OPB PPC_REG_VAL(SDRAM_PLB_M0ID_OPB, 1)
  87. #define SDRAM_WMIRQ_MAL PPC_REG_VAL(SDRAM_PLB_M0ID_MAL, 1)
  88. #define SDRAM_WMIRQ_SEC PPC_REG_VAL(SDRAM_PLB_M0ID_SEC, 1)
  89. #define SDRAM_WMIRQ_AHB PPC_REG_VAL(SDRAM_PLB_M0ID_AHB, 1)
  90. /*
  91. * Memory Controller Options 1 Register
  92. */
  93. #define SDRAM_MCOPT1_MCHK_MASK PPC_REG_VAL(3, 0x3) /* ECC mask */
  94. #define SDRAM_MCOPT1_MCHK_NON PPC_REG_VAL(3, 0x0) /* No ECC gen */
  95. #define SDRAM_MCOPT1_MCHK_GEN PPC_REG_VAL(3, 0x2) /* ECC gen */
  96. #define SDRAM_MCOPT1_MCHK_CHK PPC_REG_VAL(3, 0x1) /* ECC gen and chk */
  97. #define SDRAM_MCOPT1_MCHK_CHK_REP PPC_REG_VAL(3, 0x3) /* ECC gen/chk/rpt */
  98. #define SDRAM_MCOPT1_MCHK_DECODE(n) ((((u32)(n)) >> 28) & 0x3)
  99. #define SDRAM_MCOPT1_RDEN_MASK PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM mask */
  100. #define SDRAM_MCOPT1_RDEN PPC_REG_VAL(4, 0x1) /* Rgstrd DIMM enbl */
  101. #define SDRAM_MCOPT1_WDTH_MASK PPC_REG_VAL(7, 0x1) /* Width mask */
  102. #define SDRAM_MCOPT1_WDTH_32 PPC_REG_VAL(7, 0x0) /* 32 bits */
  103. #define SDRAM_MCOPT1_WDTH_16 PPC_REG_VAL(7, 0x1) /* 16 bits */
  104. #define SDRAM_MCOPT1_DDR_TYPE_MASK PPC_REG_VAL(11, 0x1) /* DDR type mask */
  105. #define SDRAM_MCOPT1_DDR1_TYPE PPC_REG_VAL(11, 0x0) /* DDR1 type */
  106. #define SDRAM_MCOPT1_DDR2_TYPE PPC_REG_VAL(11, 0x1) /* DDR2 type */
  107. /*
  108. * Memory Bank 0 - n Configuration Register
  109. */
  110. #define SDRAM_MBCF_BA_MASK PPC_REG_VAL(12, 0x1FFF)
  111. #define SDRAM_MBCF_SZ_MASK PPC_REG_VAL(19, 0xF)
  112. #define SDRAM_MBCF_SZ_DECODE(mbxcf) PPC_REG_DECODE(19, mbxcf)
  113. #define SDRAM_MBCF_SZ_4MB PPC_REG_VAL(19, 0x0)
  114. #define SDRAM_MBCF_SZ_8MB PPC_REG_VAL(19, 0x1)
  115. #define SDRAM_MBCF_SZ_16MB PPC_REG_VAL(19, 0x2)
  116. #define SDRAM_MBCF_SZ_32MB PPC_REG_VAL(19, 0x3)
  117. #define SDRAM_MBCF_SZ_64MB PPC_REG_VAL(19, 0x4)
  118. #define SDRAM_MBCF_SZ_128MB PPC_REG_VAL(19, 0x5)
  119. #define SDRAM_MBCF_SZ_256MB PPC_REG_VAL(19, 0x6)
  120. #define SDRAM_MBCF_SZ_512MB PPC_REG_VAL(19, 0x7)
  121. #define SDRAM_MBCF_SZ_1GB PPC_REG_VAL(19, 0x8)
  122. #define SDRAM_MBCF_SZ_2GB PPC_REG_VAL(19, 0x9)
  123. #define SDRAM_MBCF_SZ_4GB PPC_REG_VAL(19, 0xA)
  124. #define SDRAM_MBCF_SZ_8GB PPC_REG_VAL(19, 0xB)
  125. #define SDRAM_MBCF_AM_MASK PPC_REG_VAL(23, 0xF)
  126. #define SDRAM_MBCF_AM_MODE0 PPC_REG_VAL(23, 0x0)
  127. #define SDRAM_MBCF_AM_MODE1 PPC_REG_VAL(23, 0x1)
  128. #define SDRAM_MBCF_AM_MODE2 PPC_REG_VAL(23, 0x2)
  129. #define SDRAM_MBCF_AM_MODE3 PPC_REG_VAL(23, 0x3)
  130. #define SDRAM_MBCF_AM_MODE4 PPC_REG_VAL(23, 0x4)
  131. #define SDRAM_MBCF_AM_MODE5 PPC_REG_VAL(23, 0x5)
  132. #define SDRAM_MBCF_AM_MODE6 PPC_REG_VAL(23, 0x6)
  133. #define SDRAM_MBCF_AM_MODE7 PPC_REG_VAL(23, 0x7)
  134. #define SDRAM_MBCF_AM_MODE8 PPC_REG_VAL(23, 0x8)
  135. #define SDRAM_MBCF_AM_MODE9 PPC_REG_VAL(23, 0x9)
  136. #define SDRAM_MBCF_BE_MASK PPC_REG_VAL(31, 0x1)
  137. #define SDRAM_MBCF_BE_DISABLE PPC_REG_VAL(31, 0x0)
  138. #define SDRAM_MBCF_BE_ENABLE PPC_REG_VAL(31, 0x1)
  139. /*
  140. * ECC Error Status
  141. */
  142. #define SDRAM_ECCES_MASK PPC_REG_VAL(21, 0x3FFFFF)
  143. #define SDRAM_ECCES_BNCE_MASK PPC_REG_VAL(15, 0xFFFF)
  144. #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
  145. #define SDRAM_ECCES_CKBER_MASK PPC_REG_VAL(17, 0x3)
  146. #define SDRAM_ECCES_CKBER_NONE PPC_REG_VAL(17, 0)
  147. #define SDRAM_ECCES_CKBER_16_ECC_0_3 PPC_REG_VAL(17, 2)
  148. #define SDRAM_ECCES_CKBER_32_ECC_0_3 PPC_REG_VAL(17, 1)
  149. #define SDRAM_ECCES_CKBER_32_ECC_4_8 PPC_REG_VAL(17, 2)
  150. #define SDRAM_ECCES_CKBER_32_ECC_0_8 PPC_REG_VAL(17, 3)
  151. #define SDRAM_ECCES_CE PPC_REG_VAL(18, 1)
  152. #define SDRAM_ECCES_UE PPC_REG_VAL(19, 1)
  153. #define SDRAM_ECCES_BKNER_MASK PPC_REG_VAL(21, 0x3)
  154. #define SDRAM_ECCES_BK0ER PPC_REG_VAL(20, 1)
  155. #define SDRAM_ECCES_BK1ER PPC_REG_VAL(21, 1)
  156. #endif /* __PPC4XX_EDAC_H */