octeon_edac-lmc.c 8.5 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2009 Wind River Systems,
  7. * written by Ralf Baechle <ralf@linux-mips.org>
  8. *
  9. * Copyright (c) 2013 by Cisco Systems, Inc.
  10. * All rights reserved.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/slab.h>
  15. #include <linux/io.h>
  16. #include <linux/edac.h>
  17. #include <linux/ctype.h>
  18. #include <asm/octeon/octeon.h>
  19. #include <asm/octeon/cvmx-lmcx-defs.h>
  20. #include "edac_module.h"
  21. #define OCTEON_MAX_MC 4
  22. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  23. struct octeon_lmc_pvt {
  24. unsigned long inject;
  25. unsigned long error_type;
  26. unsigned long dimm;
  27. unsigned long rank;
  28. unsigned long bank;
  29. unsigned long row;
  30. unsigned long col;
  31. };
  32. static void octeon_lmc_edac_poll(struct mem_ctl_info *mci)
  33. {
  34. union cvmx_lmcx_mem_cfg0 cfg0;
  35. bool do_clear = false;
  36. char msg[64];
  37. cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx));
  38. if (cfg0.s.sec_err || cfg0.s.ded_err) {
  39. union cvmx_lmcx_fadr fadr;
  40. fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
  41. snprintf(msg, sizeof(msg),
  42. "DIMM %d rank %d bank %d row %d col %d",
  43. fadr.cn30xx.fdimm, fadr.cn30xx.fbunk,
  44. fadr.cn30xx.fbank, fadr.cn30xx.frow, fadr.cn30xx.fcol);
  45. }
  46. if (cfg0.s.sec_err) {
  47. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
  48. -1, -1, -1, msg, "");
  49. cfg0.s.sec_err = -1; /* Done, re-arm */
  50. do_clear = true;
  51. }
  52. if (cfg0.s.ded_err) {
  53. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
  54. -1, -1, -1, msg, "");
  55. cfg0.s.ded_err = -1; /* Done, re-arm */
  56. do_clear = true;
  57. }
  58. if (do_clear)
  59. cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mci->mc_idx), cfg0.u64);
  60. }
  61. static void octeon_lmc_edac_poll_o2(struct mem_ctl_info *mci)
  62. {
  63. struct octeon_lmc_pvt *pvt = mci->pvt_info;
  64. union cvmx_lmcx_int int_reg;
  65. bool do_clear = false;
  66. char msg[64];
  67. if (!pvt->inject)
  68. int_reg.u64 = cvmx_read_csr(CVMX_LMCX_INT(mci->mc_idx));
  69. else {
  70. int_reg.u64 = 0;
  71. if (pvt->error_type == 1)
  72. int_reg.s.sec_err = 1;
  73. if (pvt->error_type == 2)
  74. int_reg.s.ded_err = 1;
  75. }
  76. if (int_reg.s.sec_err || int_reg.s.ded_err) {
  77. union cvmx_lmcx_fadr fadr;
  78. if (likely(!pvt->inject))
  79. fadr.u64 = cvmx_read_csr(CVMX_LMCX_FADR(mci->mc_idx));
  80. else {
  81. fadr.cn61xx.fdimm = pvt->dimm;
  82. fadr.cn61xx.fbunk = pvt->rank;
  83. fadr.cn61xx.fbank = pvt->bank;
  84. fadr.cn61xx.frow = pvt->row;
  85. fadr.cn61xx.fcol = pvt->col;
  86. }
  87. snprintf(msg, sizeof(msg),
  88. "DIMM %d rank %d bank %d row %d col %d",
  89. fadr.cn61xx.fdimm, fadr.cn61xx.fbunk,
  90. fadr.cn61xx.fbank, fadr.cn61xx.frow, fadr.cn61xx.fcol);
  91. }
  92. if (int_reg.s.sec_err) {
  93. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
  94. -1, -1, -1, msg, "");
  95. int_reg.s.sec_err = -1; /* Done, re-arm */
  96. do_clear = true;
  97. }
  98. if (int_reg.s.ded_err) {
  99. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
  100. -1, -1, -1, msg, "");
  101. int_reg.s.ded_err = -1; /* Done, re-arm */
  102. do_clear = true;
  103. }
  104. if (do_clear) {
  105. if (likely(!pvt->inject))
  106. cvmx_write_csr(CVMX_LMCX_INT(mci->mc_idx), int_reg.u64);
  107. else
  108. pvt->inject = 0;
  109. }
  110. }
  111. /************************ MC SYSFS parts ***********************************/
  112. /* Only a couple naming differences per template, so very similar */
  113. #define TEMPLATE_SHOW(reg) \
  114. static ssize_t octeon_mc_inject_##reg##_show(struct device *dev, \
  115. struct device_attribute *attr, \
  116. char *data) \
  117. { \
  118. struct mem_ctl_info *mci = to_mci(dev); \
  119. struct octeon_lmc_pvt *pvt = mci->pvt_info; \
  120. return sprintf(data, "%016llu\n", (u64)pvt->reg); \
  121. }
  122. #define TEMPLATE_STORE(reg) \
  123. static ssize_t octeon_mc_inject_##reg##_store(struct device *dev, \
  124. struct device_attribute *attr, \
  125. const char *data, size_t count) \
  126. { \
  127. struct mem_ctl_info *mci = to_mci(dev); \
  128. struct octeon_lmc_pvt *pvt = mci->pvt_info; \
  129. if (isdigit(*data)) { \
  130. if (!kstrtoul(data, 0, &pvt->reg)) \
  131. return count; \
  132. } \
  133. return 0; \
  134. }
  135. TEMPLATE_SHOW(inject);
  136. TEMPLATE_STORE(inject);
  137. TEMPLATE_SHOW(dimm);
  138. TEMPLATE_STORE(dimm);
  139. TEMPLATE_SHOW(bank);
  140. TEMPLATE_STORE(bank);
  141. TEMPLATE_SHOW(rank);
  142. TEMPLATE_STORE(rank);
  143. TEMPLATE_SHOW(row);
  144. TEMPLATE_STORE(row);
  145. TEMPLATE_SHOW(col);
  146. TEMPLATE_STORE(col);
  147. static ssize_t octeon_mc_inject_error_type_store(struct device *dev,
  148. struct device_attribute *attr,
  149. const char *data,
  150. size_t count)
  151. {
  152. struct mem_ctl_info *mci = to_mci(dev);
  153. struct octeon_lmc_pvt *pvt = mci->pvt_info;
  154. if (!strncmp(data, "single", 6))
  155. pvt->error_type = 1;
  156. else if (!strncmp(data, "double", 6))
  157. pvt->error_type = 2;
  158. return count;
  159. }
  160. static ssize_t octeon_mc_inject_error_type_show(struct device *dev,
  161. struct device_attribute *attr,
  162. char *data)
  163. {
  164. struct mem_ctl_info *mci = to_mci(dev);
  165. struct octeon_lmc_pvt *pvt = mci->pvt_info;
  166. if (pvt->error_type == 1)
  167. return sprintf(data, "single");
  168. else if (pvt->error_type == 2)
  169. return sprintf(data, "double");
  170. return 0;
  171. }
  172. static DEVICE_ATTR(inject, S_IRUGO | S_IWUSR,
  173. octeon_mc_inject_inject_show, octeon_mc_inject_inject_store);
  174. static DEVICE_ATTR(error_type, S_IRUGO | S_IWUSR,
  175. octeon_mc_inject_error_type_show, octeon_mc_inject_error_type_store);
  176. static DEVICE_ATTR(dimm, S_IRUGO | S_IWUSR,
  177. octeon_mc_inject_dimm_show, octeon_mc_inject_dimm_store);
  178. static DEVICE_ATTR(rank, S_IRUGO | S_IWUSR,
  179. octeon_mc_inject_rank_show, octeon_mc_inject_rank_store);
  180. static DEVICE_ATTR(bank, S_IRUGO | S_IWUSR,
  181. octeon_mc_inject_bank_show, octeon_mc_inject_bank_store);
  182. static DEVICE_ATTR(row, S_IRUGO | S_IWUSR,
  183. octeon_mc_inject_row_show, octeon_mc_inject_row_store);
  184. static DEVICE_ATTR(col, S_IRUGO | S_IWUSR,
  185. octeon_mc_inject_col_show, octeon_mc_inject_col_store);
  186. static struct attribute *octeon_dev_attrs[] = {
  187. &dev_attr_inject.attr,
  188. &dev_attr_error_type.attr,
  189. &dev_attr_dimm.attr,
  190. &dev_attr_rank.attr,
  191. &dev_attr_bank.attr,
  192. &dev_attr_row.attr,
  193. &dev_attr_col.attr,
  194. NULL
  195. };
  196. ATTRIBUTE_GROUPS(octeon_dev);
  197. static int octeon_lmc_edac_probe(struct platform_device *pdev)
  198. {
  199. struct mem_ctl_info *mci;
  200. struct edac_mc_layer layers[1];
  201. int mc = pdev->id;
  202. opstate_init();
  203. layers[0].type = EDAC_MC_LAYER_CHANNEL;
  204. layers[0].size = 1;
  205. layers[0].is_virt_csrow = false;
  206. if (OCTEON_IS_OCTEON1PLUS()) {
  207. union cvmx_lmcx_mem_cfg0 cfg0;
  208. cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(0));
  209. if (!cfg0.s.ecc_ena) {
  210. dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
  211. return 0;
  212. }
  213. mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
  214. if (!mci)
  215. return -ENXIO;
  216. mci->pdev = &pdev->dev;
  217. mci->dev_name = dev_name(&pdev->dev);
  218. mci->mod_name = "octeon-lmc";
  219. mci->ctl_name = "octeon-lmc-err";
  220. mci->edac_check = octeon_lmc_edac_poll;
  221. if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
  222. dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
  223. edac_mc_free(mci);
  224. return -ENXIO;
  225. }
  226. cfg0.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
  227. cfg0.s.intr_ded_ena = 0; /* We poll */
  228. cfg0.s.intr_sec_ena = 0;
  229. cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), cfg0.u64);
  230. } else {
  231. /* OCTEON II */
  232. union cvmx_lmcx_int_en en;
  233. union cvmx_lmcx_config config;
  234. config.u64 = cvmx_read_csr(CVMX_LMCX_CONFIG(0));
  235. if (!config.s.ecc_ena) {
  236. dev_info(&pdev->dev, "Disabled (ECC not enabled)\n");
  237. return 0;
  238. }
  239. mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
  240. if (!mci)
  241. return -ENXIO;
  242. mci->pdev = &pdev->dev;
  243. mci->dev_name = dev_name(&pdev->dev);
  244. mci->mod_name = "octeon-lmc";
  245. mci->ctl_name = "co_lmc_err";
  246. mci->edac_check = octeon_lmc_edac_poll_o2;
  247. if (edac_mc_add_mc_with_groups(mci, octeon_dev_groups)) {
  248. dev_err(&pdev->dev, "edac_mc_add_mc() failed\n");
  249. edac_mc_free(mci);
  250. return -ENXIO;
  251. }
  252. en.u64 = cvmx_read_csr(CVMX_LMCX_MEM_CFG0(mc));
  253. en.s.intr_ded_ena = 0; /* We poll */
  254. en.s.intr_sec_ena = 0;
  255. cvmx_write_csr(CVMX_LMCX_MEM_CFG0(mc), en.u64);
  256. }
  257. platform_set_drvdata(pdev, mci);
  258. return 0;
  259. }
  260. static int octeon_lmc_edac_remove(struct platform_device *pdev)
  261. {
  262. struct mem_ctl_info *mci = platform_get_drvdata(pdev);
  263. edac_mc_del_mc(&pdev->dev);
  264. edac_mc_free(mci);
  265. return 0;
  266. }
  267. static struct platform_driver octeon_lmc_edac_driver = {
  268. .probe = octeon_lmc_edac_probe,
  269. .remove = octeon_lmc_edac_remove,
  270. .driver = {
  271. .name = "octeon_lmc_edac",
  272. }
  273. };
  274. module_platform_driver(octeon_lmc_edac_driver);
  275. MODULE_LICENSE("GPL");
  276. MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");