mv64x60_edac.h 3.2 KB

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  1. /*
  2. * EDAC defs for Marvell MV64x60 bridge chip
  3. *
  4. * Author: Dave Jiang <djiang@mvista.com>
  5. *
  6. * 2007 (c) MontaVista Software, Inc. This file is licensed under
  7. * the terms of the GNU General Public License version 2. This program
  8. * is licensed "as is" without any warranty of any kind, whether express
  9. * or implied.
  10. *
  11. */
  12. #ifndef _MV64X60_EDAC_H_
  13. #define _MV64X60_EDAC_H_
  14. #define MV64x60_REVISION " Ver: 2.0.0"
  15. #define EDAC_MOD_STR "MV64x60_edac"
  16. #define mv64x60_printk(level, fmt, arg...) \
  17. edac_printk(level, "MV64x60", fmt, ##arg)
  18. #define mv64x60_mc_printk(mci, level, fmt, arg...) \
  19. edac_mc_chipset_printk(mci, level, "MV64x60", fmt, ##arg)
  20. /* CPU Error Report Registers */
  21. #define MV64x60_CPU_ERR_ADDR_LO 0x00 /* 0x0070 */
  22. #define MV64x60_CPU_ERR_ADDR_HI 0x08 /* 0x0078 */
  23. #define MV64x60_CPU_ERR_DATA_LO 0x00 /* 0x0128 */
  24. #define MV64x60_CPU_ERR_DATA_HI 0x08 /* 0x0130 */
  25. #define MV64x60_CPU_ERR_PARITY 0x10 /* 0x0138 */
  26. #define MV64x60_CPU_ERR_CAUSE 0x18 /* 0x0140 */
  27. #define MV64x60_CPU_ERR_MASK 0x20 /* 0x0148 */
  28. #define MV64x60_CPU_CAUSE_MASK 0x07ffffff
  29. /* SRAM Error Report Registers */
  30. #define MV64X60_SRAM_ERR_CAUSE 0x08 /* 0x0388 */
  31. #define MV64X60_SRAM_ERR_ADDR_LO 0x10 /* 0x0390 */
  32. #define MV64X60_SRAM_ERR_ADDR_HI 0x78 /* 0x03f8 */
  33. #define MV64X60_SRAM_ERR_DATA_LO 0x18 /* 0x0398 */
  34. #define MV64X60_SRAM_ERR_DATA_HI 0x20 /* 0x03a0 */
  35. #define MV64X60_SRAM_ERR_PARITY 0x28 /* 0x03a8 */
  36. /* SDRAM Controller Registers */
  37. #define MV64X60_SDRAM_CONFIG 0x00 /* 0x1400 */
  38. #define MV64X60_SDRAM_ERR_DATA_HI 0x40 /* 0x1440 */
  39. #define MV64X60_SDRAM_ERR_DATA_LO 0x44 /* 0x1444 */
  40. #define MV64X60_SDRAM_ERR_ECC_RCVD 0x48 /* 0x1448 */
  41. #define MV64X60_SDRAM_ERR_ECC_CALC 0x4c /* 0x144c */
  42. #define MV64X60_SDRAM_ERR_ADDR 0x50 /* 0x1450 */
  43. #define MV64X60_SDRAM_ERR_ECC_CNTL 0x54 /* 0x1454 */
  44. #define MV64X60_SDRAM_ERR_ECC_ERR_CNT 0x58 /* 0x1458 */
  45. #define MV64X60_SDRAM_REGISTERED 0x20000
  46. #define MV64X60_SDRAM_ECC 0x40000
  47. #ifdef CONFIG_PCI
  48. /*
  49. * Bit 0 of MV64x60_PCIx_ERR_MASK does not exist on the 64360 and because of
  50. * errata FEr-#11 and FEr-##16 for the 64460, it should be 0 on that chip as
  51. * well. IOW, don't set bit 0.
  52. */
  53. #define MV64X60_PCIx_ERR_MASK_VAL 0x00a50c24
  54. /* Register offsets from PCIx error address low register */
  55. #define MV64X60_PCI_ERROR_ADDR_LO 0x00
  56. #define MV64X60_PCI_ERROR_ADDR_HI 0x04
  57. #define MV64X60_PCI_ERROR_ATTR 0x08
  58. #define MV64X60_PCI_ERROR_CMD 0x10
  59. #define MV64X60_PCI_ERROR_CAUSE 0x18
  60. #define MV64X60_PCI_ERROR_MASK 0x1c
  61. #define MV64X60_PCI_ERR_SWrPerr 0x0002
  62. #define MV64X60_PCI_ERR_SRdPerr 0x0004
  63. #define MV64X60_PCI_ERR_MWrPerr 0x0020
  64. #define MV64X60_PCI_ERR_MRdPerr 0x0040
  65. #define MV64X60_PCI_PE_MASK (MV64X60_PCI_ERR_SWrPerr | \
  66. MV64X60_PCI_ERR_SRdPerr | \
  67. MV64X60_PCI_ERR_MWrPerr | \
  68. MV64X60_PCI_ERR_MRdPerr)
  69. struct mv64x60_pci_pdata {
  70. int pci_hose;
  71. void __iomem *pci_vbase;
  72. char *name;
  73. int irq;
  74. int edac_idx;
  75. };
  76. #endif /* CONFIG_PCI */
  77. struct mv64x60_mc_pdata {
  78. void __iomem *mc_vbase;
  79. int total_mem;
  80. char *name;
  81. int irq;
  82. int edac_idx;
  83. };
  84. struct mv64x60_cpu_pdata {
  85. void __iomem *cpu_vbase[2];
  86. char *name;
  87. int irq;
  88. int edac_idx;
  89. };
  90. struct mv64x60_sram_pdata {
  91. void __iomem *sram_vbase;
  92. char *name;
  93. int irq;
  94. int edac_idx;
  95. };
  96. #endif