layerscape_edac.c 1.6 KB

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  1. /*
  2. * Freescale Memory Controller kernel module
  3. *
  4. * Author: York Sun <york.sun@nxp.com>
  5. *
  6. * Copyright 2016 NXP Semiconductor
  7. *
  8. * Derived from mpc85xx_edac.c
  9. * Author: Dave Jiang <djiang@mvista.com>
  10. *
  11. * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
  12. * the terms of the GNU General Public License version 2. This program
  13. * is licensed "as is" without any warranty of any kind, whether express
  14. * or implied.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include "edac_module.h"
  18. #include "fsl_ddr_edac.h"
  19. static const struct of_device_id fsl_ddr_mc_err_of_match[] = {
  20. { .compatible = "fsl,qoriq-memory-controller", },
  21. {},
  22. };
  23. MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match);
  24. static struct platform_driver fsl_ddr_mc_err_driver = {
  25. .probe = fsl_mc_err_probe,
  26. .remove = fsl_mc_err_remove,
  27. .driver = {
  28. .name = "fsl_ddr_mc_err",
  29. .of_match_table = fsl_ddr_mc_err_of_match,
  30. },
  31. };
  32. static int __init fsl_ddr_mc_init(void)
  33. {
  34. int res;
  35. /* make sure error reporting method is sane */
  36. switch (edac_op_state) {
  37. case EDAC_OPSTATE_POLL:
  38. case EDAC_OPSTATE_INT:
  39. break;
  40. default:
  41. edac_op_state = EDAC_OPSTATE_INT;
  42. break;
  43. }
  44. res = platform_driver_register(&fsl_ddr_mc_err_driver);
  45. if (res) {
  46. pr_err("MC fails to register\n");
  47. return res;
  48. }
  49. return 0;
  50. }
  51. module_init(fsl_ddr_mc_init);
  52. static void __exit fsl_ddr_mc_exit(void)
  53. {
  54. platform_driver_unregister(&fsl_ddr_mc_err_driver);
  55. }
  56. module_exit(fsl_ddr_mc_exit);
  57. MODULE_LICENSE("GPL");
  58. MODULE_AUTHOR("NXP Semiconductor");
  59. module_param(edac_op_state, int, 0444);
  60. MODULE_PARM_DESC(edac_op_state,
  61. "EDAC Error Reporting state: 0=Poll, 2=Interrupt");