ie31200_edac.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Intel E3-1200
  4. * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
  5. *
  6. * Support for the E3-1200 processor family. Heavily based on previous
  7. * Intel EDAC drivers.
  8. *
  9. * Since the DRAM controller is on the cpu chip, we can use its PCI device
  10. * id to identify these processors.
  11. *
  12. * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
  13. *
  14. * 0108: Xeon E3-1200 Processor Family DRAM Controller
  15. * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
  16. * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
  17. * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
  18. * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
  19. * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
  20. * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
  21. * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
  22. * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
  23. * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
  24. *
  25. * Based on Intel specification:
  26. * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
  27. * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
  28. * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
  29. * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
  30. *
  31. * According to the above datasheet (p.16):
  32. * "
  33. * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
  34. * requests that cross a DW boundary.
  35. * "
  36. *
  37. * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
  38. * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
  39. * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
  40. */
  41. #include <linux/module.h>
  42. #include <linux/init.h>
  43. #include <linux/pci.h>
  44. #include <linux/pci_ids.h>
  45. #include <linux/edac.h>
  46. #include <linux/io-64-nonatomic-lo-hi.h>
  47. #include "edac_module.h"
  48. #define EDAC_MOD_STR "ie31200_edac"
  49. #define ie31200_printk(level, fmt, arg...) \
  50. edac_printk(level, "ie31200", fmt, ##arg)
  51. #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
  52. #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
  53. #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
  54. #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
  55. #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
  56. #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
  57. #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
  58. #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
  59. #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
  60. /* Coffee Lake-S */
  61. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
  62. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f
  63. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18
  64. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f
  65. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30
  66. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31
  67. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32
  68. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33
  69. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2
  70. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6
  71. #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca
  72. /* Test if HB is for Skylake or later. */
  73. #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
  74. (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
  75. ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
  76. (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
  77. PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
  78. #define IE31200_DIMMS 4
  79. #define IE31200_RANKS 8
  80. #define IE31200_RANKS_PER_CHANNEL 4
  81. #define IE31200_DIMMS_PER_CHANNEL 2
  82. #define IE31200_CHANNELS 2
  83. /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
  84. #define IE31200_MCHBAR_LOW 0x48
  85. #define IE31200_MCHBAR_HIGH 0x4c
  86. #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
  87. #define IE31200_MMR_WINDOW_SIZE BIT(15)
  88. /*
  89. * Error Status Register (16b)
  90. *
  91. * 15 reserved
  92. * 14 Isochronous TBWRR Run Behind FIFO Full
  93. * (ITCV)
  94. * 13 Isochronous TBWRR Run Behind FIFO Put
  95. * (ITSTV)
  96. * 12 reserved
  97. * 11 MCH Thermal Sensor Event
  98. * for SMI/SCI/SERR (GTSE)
  99. * 10 reserved
  100. * 9 LOCK to non-DRAM Memory Flag (LCKF)
  101. * 8 reserved
  102. * 7 DRAM Throttle Flag (DTF)
  103. * 6:2 reserved
  104. * 1 Multi-bit DRAM ECC Error Flag (DMERR)
  105. * 0 Single-bit DRAM ECC Error Flag (DSERR)
  106. */
  107. #define IE31200_ERRSTS 0xc8
  108. #define IE31200_ERRSTS_UE BIT(1)
  109. #define IE31200_ERRSTS_CE BIT(0)
  110. #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
  111. /*
  112. * Channel 0 ECC Error Log (64b)
  113. *
  114. * 63:48 Error Column Address (ERRCOL)
  115. * 47:32 Error Row Address (ERRROW)
  116. * 31:29 Error Bank Address (ERRBANK)
  117. * 28:27 Error Rank Address (ERRRANK)
  118. * 26:24 reserved
  119. * 23:16 Error Syndrome (ERRSYND)
  120. * 15: 2 reserved
  121. * 1 Multiple Bit Error Status (MERRSTS)
  122. * 0 Correctable Error Status (CERRSTS)
  123. */
  124. #define IE31200_C0ECCERRLOG 0x40c8
  125. #define IE31200_C1ECCERRLOG 0x44c8
  126. #define IE31200_C0ECCERRLOG_SKL 0x4048
  127. #define IE31200_C1ECCERRLOG_SKL 0x4448
  128. #define IE31200_ECCERRLOG_CE BIT(0)
  129. #define IE31200_ECCERRLOG_UE BIT(1)
  130. #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
  131. #define IE31200_ECCERRLOG_RANK_SHIFT 27
  132. #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
  133. #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
  134. #define IE31200_ECCERRLOG_SYNDROME(log) \
  135. ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
  136. IE31200_ECCERRLOG_SYNDROME_SHIFT)
  137. #define IE31200_CAPID0 0xe4
  138. #define IE31200_CAPID0_PDCD BIT(4)
  139. #define IE31200_CAPID0_DDPCD BIT(6)
  140. #define IE31200_CAPID0_ECC BIT(1)
  141. #define IE31200_MAD_DIMM_0_OFFSET 0x5004
  142. #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
  143. #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
  144. #define IE31200_MAD_DIMM_A_RANK BIT(17)
  145. #define IE31200_MAD_DIMM_A_RANK_SHIFT 17
  146. #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
  147. #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
  148. #define IE31200_MAD_DIMM_A_WIDTH BIT(19)
  149. #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
  150. #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
  151. #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
  152. /* Skylake reports 1GB increments, everything else is 256MB */
  153. #define IE31200_PAGES(n, skl) \
  154. (n << (28 + (2 * skl) - PAGE_SHIFT))
  155. static int nr_channels;
  156. static struct pci_dev *mci_pdev;
  157. static int ie31200_registered = 1;
  158. struct ie31200_priv {
  159. void __iomem *window;
  160. void __iomem *c0errlog;
  161. void __iomem *c1errlog;
  162. };
  163. enum ie31200_chips {
  164. IE31200 = 0,
  165. };
  166. struct ie31200_dev_info {
  167. const char *ctl_name;
  168. };
  169. struct ie31200_error_info {
  170. u16 errsts;
  171. u16 errsts2;
  172. u64 eccerrlog[IE31200_CHANNELS];
  173. };
  174. static const struct ie31200_dev_info ie31200_devs[] = {
  175. [IE31200] = {
  176. .ctl_name = "IE31200"
  177. },
  178. };
  179. struct dimm_data {
  180. u8 size; /* in multiples of 256MB, except Skylake is 1GB */
  181. u8 dual_rank : 1,
  182. x16_width : 2; /* 0 means x8 width */
  183. };
  184. static int how_many_channels(struct pci_dev *pdev)
  185. {
  186. int n_channels;
  187. unsigned char capid0_2b; /* 2nd byte of CAPID0 */
  188. pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
  189. /* check PDCD: Dual Channel Disable */
  190. if (capid0_2b & IE31200_CAPID0_PDCD) {
  191. edac_dbg(0, "In single channel mode\n");
  192. n_channels = 1;
  193. } else {
  194. edac_dbg(0, "In dual channel mode\n");
  195. n_channels = 2;
  196. }
  197. /* check DDPCD - check if both channels are filled */
  198. if (capid0_2b & IE31200_CAPID0_DDPCD)
  199. edac_dbg(0, "2 DIMMS per channel disabled\n");
  200. else
  201. edac_dbg(0, "2 DIMMS per channel enabled\n");
  202. return n_channels;
  203. }
  204. static bool ecc_capable(struct pci_dev *pdev)
  205. {
  206. unsigned char capid0_4b; /* 4th byte of CAPID0 */
  207. pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
  208. if (capid0_4b & IE31200_CAPID0_ECC)
  209. return false;
  210. return true;
  211. }
  212. static int eccerrlog_row(u64 log)
  213. {
  214. return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
  215. IE31200_ECCERRLOG_RANK_SHIFT);
  216. }
  217. static void ie31200_clear_error_info(struct mem_ctl_info *mci)
  218. {
  219. /*
  220. * Clear any error bits.
  221. * (Yes, we really clear bits by writing 1 to them.)
  222. */
  223. pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
  224. IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
  225. }
  226. static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
  227. struct ie31200_error_info *info)
  228. {
  229. struct pci_dev *pdev;
  230. struct ie31200_priv *priv = mci->pvt_info;
  231. pdev = to_pci_dev(mci->pdev);
  232. /*
  233. * This is a mess because there is no atomic way to read all the
  234. * registers at once and the registers can transition from CE being
  235. * overwritten by UE.
  236. */
  237. pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
  238. if (!(info->errsts & IE31200_ERRSTS_BITS))
  239. return;
  240. info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
  241. if (nr_channels == 2)
  242. info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
  243. pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
  244. /*
  245. * If the error is the same for both reads then the first set
  246. * of reads is valid. If there is a change then there is a CE
  247. * with no info and the second set of reads is valid and
  248. * should be UE info.
  249. */
  250. if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
  251. info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
  252. if (nr_channels == 2)
  253. info->eccerrlog[1] =
  254. lo_hi_readq(priv->c1errlog);
  255. }
  256. ie31200_clear_error_info(mci);
  257. }
  258. static void ie31200_process_error_info(struct mem_ctl_info *mci,
  259. struct ie31200_error_info *info)
  260. {
  261. int channel;
  262. u64 log;
  263. if (!(info->errsts & IE31200_ERRSTS_BITS))
  264. return;
  265. if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
  266. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
  267. -1, -1, -1, "UE overwrote CE", "");
  268. info->errsts = info->errsts2;
  269. }
  270. for (channel = 0; channel < nr_channels; channel++) {
  271. log = info->eccerrlog[channel];
  272. if (log & IE31200_ECCERRLOG_UE) {
  273. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  274. 0, 0, 0,
  275. eccerrlog_row(log),
  276. channel, -1,
  277. "ie31200 UE", "");
  278. } else if (log & IE31200_ECCERRLOG_CE) {
  279. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  280. 0, 0,
  281. IE31200_ECCERRLOG_SYNDROME(log),
  282. eccerrlog_row(log),
  283. channel, -1,
  284. "ie31200 CE", "");
  285. }
  286. }
  287. }
  288. static void ie31200_check(struct mem_ctl_info *mci)
  289. {
  290. struct ie31200_error_info info;
  291. edac_dbg(1, "MC%d\n", mci->mc_idx);
  292. ie31200_get_and_clear_error_info(mci, &info);
  293. ie31200_process_error_info(mci, &info);
  294. }
  295. static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
  296. {
  297. union {
  298. u64 mchbar;
  299. struct {
  300. u32 mchbar_low;
  301. u32 mchbar_high;
  302. };
  303. } u;
  304. void __iomem *window;
  305. pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
  306. pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
  307. u.mchbar &= IE31200_MCHBAR_MASK;
  308. if (u.mchbar != (resource_size_t)u.mchbar) {
  309. ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
  310. (unsigned long long)u.mchbar);
  311. return NULL;
  312. }
  313. window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE);
  314. if (!window)
  315. ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
  316. (unsigned long long)u.mchbar);
  317. return window;
  318. }
  319. static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
  320. int chan)
  321. {
  322. dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE;
  323. dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
  324. dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
  325. (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
  326. }
  327. static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
  328. int chan)
  329. {
  330. dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
  331. dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
  332. dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
  333. }
  334. static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
  335. bool skl)
  336. {
  337. if (skl)
  338. __skl_populate_dimm_info(dd, addr_decode, chan);
  339. else
  340. __populate_dimm_info(dd, addr_decode, chan);
  341. }
  342. static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
  343. {
  344. int i, j, ret;
  345. struct mem_ctl_info *mci = NULL;
  346. struct edac_mc_layer layers[2];
  347. struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
  348. void __iomem *window;
  349. struct ie31200_priv *priv;
  350. u32 addr_decode, mad_offset;
  351. /*
  352. * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit
  353. * this logic when adding new CPU support.
  354. */
  355. bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);
  356. edac_dbg(0, "MC:\n");
  357. if (!ecc_capable(pdev)) {
  358. ie31200_printk(KERN_INFO, "No ECC support\n");
  359. return -ENODEV;
  360. }
  361. nr_channels = how_many_channels(pdev);
  362. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  363. layers[0].size = IE31200_DIMMS;
  364. layers[0].is_virt_csrow = true;
  365. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  366. layers[1].size = nr_channels;
  367. layers[1].is_virt_csrow = false;
  368. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
  369. sizeof(struct ie31200_priv));
  370. if (!mci)
  371. return -ENOMEM;
  372. window = ie31200_map_mchbar(pdev);
  373. if (!window) {
  374. ret = -ENODEV;
  375. goto fail_free;
  376. }
  377. edac_dbg(3, "MC: init mci\n");
  378. mci->pdev = &pdev->dev;
  379. if (skl)
  380. mci->mtype_cap = MEM_FLAG_DDR4;
  381. else
  382. mci->mtype_cap = MEM_FLAG_DDR3;
  383. mci->edac_ctl_cap = EDAC_FLAG_SECDED;
  384. mci->edac_cap = EDAC_FLAG_SECDED;
  385. mci->mod_name = EDAC_MOD_STR;
  386. mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
  387. mci->dev_name = pci_name(pdev);
  388. mci->edac_check = ie31200_check;
  389. mci->ctl_page_to_phys = NULL;
  390. priv = mci->pvt_info;
  391. priv->window = window;
  392. if (skl) {
  393. priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
  394. priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
  395. mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
  396. } else {
  397. priv->c0errlog = window + IE31200_C0ECCERRLOG;
  398. priv->c1errlog = window + IE31200_C1ECCERRLOG;
  399. mad_offset = IE31200_MAD_DIMM_0_OFFSET;
  400. }
  401. /* populate DIMM info */
  402. for (i = 0; i < IE31200_CHANNELS; i++) {
  403. addr_decode = readl(window + mad_offset +
  404. (i * 4));
  405. edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
  406. for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
  407. populate_dimm_info(&dimm_info[i][j], addr_decode, j,
  408. skl);
  409. edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
  410. dimm_info[i][j].size,
  411. dimm_info[i][j].dual_rank,
  412. dimm_info[i][j].x16_width);
  413. }
  414. }
  415. /*
  416. * The dram rank boundary (DRB) reg values are boundary addresses
  417. * for each DRAM rank with a granularity of 64MB. DRB regs are
  418. * cumulative; the last one will contain the total memory
  419. * contained in all ranks.
  420. */
  421. for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
  422. for (j = 0; j < IE31200_CHANNELS; j++) {
  423. struct dimm_info *dimm;
  424. unsigned long nr_pages;
  425. nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
  426. if (nr_pages == 0)
  427. continue;
  428. if (dimm_info[j][i].dual_rank) {
  429. nr_pages = nr_pages / 2;
  430. dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);
  431. dimm->nr_pages = nr_pages;
  432. edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
  433. dimm->grain = 8; /* just a guess */
  434. if (skl)
  435. dimm->mtype = MEM_DDR4;
  436. else
  437. dimm->mtype = MEM_DDR3;
  438. dimm->dtype = DEV_UNKNOWN;
  439. dimm->edac_mode = EDAC_UNKNOWN;
  440. }
  441. dimm = edac_get_dimm(mci, i * 2, j, 0);
  442. dimm->nr_pages = nr_pages;
  443. edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
  444. dimm->grain = 8; /* same guess */
  445. if (skl)
  446. dimm->mtype = MEM_DDR4;
  447. else
  448. dimm->mtype = MEM_DDR3;
  449. dimm->dtype = DEV_UNKNOWN;
  450. dimm->edac_mode = EDAC_UNKNOWN;
  451. }
  452. }
  453. ie31200_clear_error_info(mci);
  454. if (edac_mc_add_mc(mci)) {
  455. edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
  456. ret = -ENODEV;
  457. goto fail_unmap;
  458. }
  459. /* get this far and it's successful */
  460. edac_dbg(3, "MC: success\n");
  461. return 0;
  462. fail_unmap:
  463. iounmap(window);
  464. fail_free:
  465. edac_mc_free(mci);
  466. return ret;
  467. }
  468. static int ie31200_init_one(struct pci_dev *pdev,
  469. const struct pci_device_id *ent)
  470. {
  471. int rc;
  472. edac_dbg(0, "MC:\n");
  473. if (pci_enable_device(pdev) < 0)
  474. return -EIO;
  475. rc = ie31200_probe1(pdev, ent->driver_data);
  476. if (rc == 0 && !mci_pdev)
  477. mci_pdev = pci_dev_get(pdev);
  478. return rc;
  479. }
  480. static void ie31200_remove_one(struct pci_dev *pdev)
  481. {
  482. struct mem_ctl_info *mci;
  483. struct ie31200_priv *priv;
  484. edac_dbg(0, "\n");
  485. pci_dev_put(mci_pdev);
  486. mci_pdev = NULL;
  487. mci = edac_mc_del_mc(&pdev->dev);
  488. if (!mci)
  489. return;
  490. priv = mci->pvt_info;
  491. iounmap(priv->window);
  492. edac_mc_free(mci);
  493. }
  494. static const struct pci_device_id ie31200_pci_tbl[] = {
  495. { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  496. { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  497. { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  498. { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  499. { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  500. { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  501. { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  502. { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  503. { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  504. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  505. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  506. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  507. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  508. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  509. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  510. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  511. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  512. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  513. { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
  514. { 0, } /* 0 terminated list. */
  515. };
  516. MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
  517. static struct pci_driver ie31200_driver = {
  518. .name = EDAC_MOD_STR,
  519. .probe = ie31200_init_one,
  520. .remove = ie31200_remove_one,
  521. .id_table = ie31200_pci_tbl,
  522. };
  523. static int __init ie31200_init(void)
  524. {
  525. int pci_rc, i;
  526. edac_dbg(3, "MC:\n");
  527. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  528. opstate_init();
  529. pci_rc = pci_register_driver(&ie31200_driver);
  530. if (pci_rc < 0)
  531. goto fail0;
  532. if (!mci_pdev) {
  533. ie31200_registered = 0;
  534. for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
  535. mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
  536. ie31200_pci_tbl[i].device,
  537. NULL);
  538. if (mci_pdev)
  539. break;
  540. }
  541. if (!mci_pdev) {
  542. edac_dbg(0, "ie31200 pci_get_device fail\n");
  543. pci_rc = -ENODEV;
  544. goto fail1;
  545. }
  546. pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
  547. if (pci_rc < 0) {
  548. edac_dbg(0, "ie31200 init fail\n");
  549. pci_rc = -ENODEV;
  550. goto fail1;
  551. }
  552. }
  553. return 0;
  554. fail1:
  555. pci_unregister_driver(&ie31200_driver);
  556. fail0:
  557. pci_dev_put(mci_pdev);
  558. return pci_rc;
  559. }
  560. static void __exit ie31200_exit(void)
  561. {
  562. edac_dbg(3, "MC:\n");
  563. pci_unregister_driver(&ie31200_driver);
  564. if (!ie31200_registered)
  565. ie31200_remove_one(mci_pdev);
  566. }
  567. module_init(ie31200_init);
  568. module_exit(ie31200_exit);
  569. MODULE_LICENSE("GPL");
  570. MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
  571. MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");