i82875p_edac.c 15 KB

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  1. /*
  2. * Intel D82875P Memory Controller kernel module
  3. * (C) 2003 Linux Networx (http://lnxi.com)
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License.
  6. *
  7. * Written by Thayne Harbaugh
  8. * Contributors:
  9. * Wang Zhenyu at intel.com
  10. *
  11. * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
  12. *
  13. * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
  14. */
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/pci.h>
  18. #include <linux/pci_ids.h>
  19. #include <linux/edac.h>
  20. #include "edac_module.h"
  21. #define EDAC_MOD_STR "i82875p_edac"
  22. #define i82875p_printk(level, fmt, arg...) \
  23. edac_printk(level, "i82875p", fmt, ##arg)
  24. #define i82875p_mc_printk(mci, level, fmt, arg...) \
  25. edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
  26. #ifndef PCI_DEVICE_ID_INTEL_82875_0
  27. #define PCI_DEVICE_ID_INTEL_82875_0 0x2578
  28. #endif /* PCI_DEVICE_ID_INTEL_82875_0 */
  29. #ifndef PCI_DEVICE_ID_INTEL_82875_6
  30. #define PCI_DEVICE_ID_INTEL_82875_6 0x257e
  31. #endif /* PCI_DEVICE_ID_INTEL_82875_6 */
  32. /* four csrows in dual channel, eight in single channel */
  33. #define I82875P_NR_DIMMS 8
  34. #define I82875P_NR_CSROWS(nr_chans) (I82875P_NR_DIMMS / (nr_chans))
  35. /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
  36. #define I82875P_EAP 0x58 /* Error Address Pointer (32b)
  37. *
  38. * 31:12 block address
  39. * 11:0 reserved
  40. */
  41. #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
  42. *
  43. * 7:0 DRAM ECC Syndrome
  44. */
  45. #define I82875P_DES 0x5d /* DRAM Error Status (8b)
  46. *
  47. * 7:1 reserved
  48. * 0 Error channel 0/1
  49. */
  50. #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
  51. *
  52. * 15:10 reserved
  53. * 9 non-DRAM lock error (ndlock)
  54. * 8 Sftwr Generated SMI
  55. * 7 ECC UE
  56. * 6 reserved
  57. * 5 MCH detects unimplemented cycle
  58. * 4 AGP access outside GA
  59. * 3 Invalid AGP access
  60. * 2 Invalid GA translation table
  61. * 1 Unsupported AGP command
  62. * 0 ECC CE
  63. */
  64. #define I82875P_ERRCMD 0xca /* Error Command (16b)
  65. *
  66. * 15:10 reserved
  67. * 9 SERR on non-DRAM lock
  68. * 8 SERR on ECC UE
  69. * 7 SERR on ECC CE
  70. * 6 target abort on high exception
  71. * 5 detect unimplemented cyc
  72. * 4 AGP access outside of GA
  73. * 3 SERR on invalid AGP access
  74. * 2 invalid translation table
  75. * 1 SERR on unsupported AGP command
  76. * 0 reserved
  77. */
  78. /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
  79. #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
  80. *
  81. * 15:10 reserved
  82. * 9 fast back-to-back - ro 0
  83. * 8 SERR enable - ro 0
  84. * 7 addr/data stepping - ro 0
  85. * 6 parity err enable - ro 0
  86. * 5 VGA palette snoop - ro 0
  87. * 4 mem wr & invalidate - ro 0
  88. * 3 special cycle - ro 0
  89. * 2 bus master - ro 0
  90. * 1 mem access dev6 - 0(dis),1(en)
  91. * 0 IO access dev3 - 0(dis),1(en)
  92. */
  93. #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
  94. *
  95. * 31:12 mem base addr [31:12]
  96. * 11:4 address mask - ro 0
  97. * 3 prefetchable - ro 0(non),1(pre)
  98. * 2:1 mem type - ro 0
  99. * 0 mem space - ro 0
  100. */
  101. /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
  102. #define I82875P_DRB_SHIFT 26 /* 64MiB grain */
  103. #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
  104. *
  105. * 7 reserved
  106. * 6:0 64MiB row boundary addr
  107. */
  108. #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
  109. *
  110. * 7 reserved
  111. * 6:4 row attr row 1
  112. * 3 reserved
  113. * 2:0 row attr row 0
  114. *
  115. * 000 = 4KiB
  116. * 001 = 8KiB
  117. * 010 = 16KiB
  118. * 011 = 32KiB
  119. */
  120. #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
  121. *
  122. * 31:30 reserved
  123. * 29 init complete
  124. * 28:23 reserved
  125. * 22:21 nr chan 00=1,01=2
  126. * 20 reserved
  127. * 19:18 Data Integ Mode 00=none,01=ecc
  128. * 17:11 reserved
  129. * 10:8 refresh mode
  130. * 7 reserved
  131. * 6:4 mode select
  132. * 3:2 reserved
  133. * 1:0 DRAM type 01=DDR
  134. */
  135. enum i82875p_chips {
  136. I82875P = 0,
  137. };
  138. struct i82875p_pvt {
  139. struct pci_dev *ovrfl_pdev;
  140. void __iomem *ovrfl_window;
  141. };
  142. struct i82875p_dev_info {
  143. const char *ctl_name;
  144. };
  145. struct i82875p_error_info {
  146. u16 errsts;
  147. u32 eap;
  148. u8 des;
  149. u8 derrsyn;
  150. u16 errsts2;
  151. };
  152. static const struct i82875p_dev_info i82875p_devs[] = {
  153. [I82875P] = {
  154. .ctl_name = "i82875p"},
  155. };
  156. static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
  157. * already registered driver
  158. */
  159. static struct edac_pci_ctl_info *i82875p_pci;
  160. static void i82875p_get_error_info(struct mem_ctl_info *mci,
  161. struct i82875p_error_info *info)
  162. {
  163. struct pci_dev *pdev;
  164. pdev = to_pci_dev(mci->pdev);
  165. /*
  166. * This is a mess because there is no atomic way to read all the
  167. * registers at once and the registers can transition from CE being
  168. * overwritten by UE.
  169. */
  170. pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
  171. if (!(info->errsts & 0x0081))
  172. return;
  173. pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
  174. pci_read_config_byte(pdev, I82875P_DES, &info->des);
  175. pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
  176. pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
  177. /*
  178. * If the error is the same then we can for both reads then
  179. * the first set of reads is valid. If there is a change then
  180. * there is a CE no info and the second set of reads is valid
  181. * and should be UE info.
  182. */
  183. if ((info->errsts ^ info->errsts2) & 0x0081) {
  184. pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
  185. pci_read_config_byte(pdev, I82875P_DES, &info->des);
  186. pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
  187. }
  188. pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
  189. }
  190. static int i82875p_process_error_info(struct mem_ctl_info *mci,
  191. struct i82875p_error_info *info,
  192. int handle_errors)
  193. {
  194. int row, multi_chan;
  195. multi_chan = mci->csrows[0]->nr_channels - 1;
  196. if (!(info->errsts & 0x0081))
  197. return 0;
  198. if (!handle_errors)
  199. return 1;
  200. if ((info->errsts ^ info->errsts2) & 0x0081) {
  201. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
  202. -1, -1, -1,
  203. "UE overwrote CE", "");
  204. info->errsts = info->errsts2;
  205. }
  206. info->eap >>= PAGE_SHIFT;
  207. row = edac_mc_find_csrow_by_page(mci, info->eap);
  208. if (info->errsts & 0x0080)
  209. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  210. info->eap, 0, 0,
  211. row, -1, -1,
  212. "i82875p UE", "");
  213. else
  214. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  215. info->eap, 0, info->derrsyn,
  216. row, multi_chan ? (info->des & 0x1) : 0,
  217. -1, "i82875p CE", "");
  218. return 1;
  219. }
  220. static void i82875p_check(struct mem_ctl_info *mci)
  221. {
  222. struct i82875p_error_info info;
  223. edac_dbg(1, "MC%d\n", mci->mc_idx);
  224. i82875p_get_error_info(mci, &info);
  225. i82875p_process_error_info(mci, &info, 1);
  226. }
  227. /* Return 0 on success or 1 on failure. */
  228. static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
  229. struct pci_dev **ovrfl_pdev,
  230. void __iomem **ovrfl_window)
  231. {
  232. struct pci_dev *dev;
  233. void __iomem *window;
  234. *ovrfl_pdev = NULL;
  235. *ovrfl_window = NULL;
  236. dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
  237. if (dev == NULL) {
  238. /* Intel tells BIOS developers to hide device 6 which
  239. * configures the overflow device access containing
  240. * the DRBs - this is where we expose device 6.
  241. * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
  242. */
  243. pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
  244. dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
  245. if (dev == NULL)
  246. return 1;
  247. pci_bus_assign_resources(dev->bus);
  248. pci_bus_add_device(dev);
  249. }
  250. *ovrfl_pdev = dev;
  251. if (pci_enable_device(dev)) {
  252. i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
  253. "device\n", __func__);
  254. return 1;
  255. }
  256. if (pci_request_regions(dev, pci_name(dev))) {
  257. #ifdef CORRECT_BIOS
  258. goto fail0;
  259. #endif
  260. }
  261. /* cache is irrelevant for PCI bus reads/writes */
  262. window = pci_ioremap_bar(dev, 0);
  263. if (window == NULL) {
  264. i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
  265. __func__);
  266. goto fail1;
  267. }
  268. *ovrfl_window = window;
  269. return 0;
  270. fail1:
  271. pci_release_regions(dev);
  272. #ifdef CORRECT_BIOS
  273. fail0:
  274. pci_disable_device(dev);
  275. #endif
  276. /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
  277. return 1;
  278. }
  279. /* Return 1 if dual channel mode is active. Else return 0. */
  280. static inline int dual_channel_active(u32 drc)
  281. {
  282. return (drc >> 21) & 0x1;
  283. }
  284. static void i82875p_init_csrows(struct mem_ctl_info *mci,
  285. struct pci_dev *pdev,
  286. void __iomem * ovrfl_window, u32 drc)
  287. {
  288. struct csrow_info *csrow;
  289. struct dimm_info *dimm;
  290. unsigned nr_chans = dual_channel_active(drc) + 1;
  291. unsigned long last_cumul_size;
  292. u8 value;
  293. u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
  294. u32 cumul_size, nr_pages;
  295. int index, j;
  296. drc_ddim = (drc >> 18) & 0x1;
  297. last_cumul_size = 0;
  298. /* The dram row boundary (DRB) reg values are boundary address
  299. * for each DRAM row with a granularity of 32 or 64MB (single/dual
  300. * channel operation). DRB regs are cumulative; therefore DRB7 will
  301. * contain the total memory contained in all eight rows.
  302. */
  303. for (index = 0; index < mci->nr_csrows; index++) {
  304. csrow = mci->csrows[index];
  305. value = readb(ovrfl_window + I82875P_DRB + index);
  306. cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
  307. edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
  308. if (cumul_size == last_cumul_size)
  309. continue; /* not populated */
  310. csrow->first_page = last_cumul_size;
  311. csrow->last_page = cumul_size - 1;
  312. nr_pages = cumul_size - last_cumul_size;
  313. last_cumul_size = cumul_size;
  314. for (j = 0; j < nr_chans; j++) {
  315. dimm = csrow->channels[j]->dimm;
  316. dimm->nr_pages = nr_pages / nr_chans;
  317. dimm->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
  318. dimm->mtype = MEM_DDR;
  319. dimm->dtype = DEV_UNKNOWN;
  320. dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
  321. }
  322. }
  323. }
  324. static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
  325. {
  326. int rc = -ENODEV;
  327. struct mem_ctl_info *mci;
  328. struct edac_mc_layer layers[2];
  329. struct i82875p_pvt *pvt;
  330. struct pci_dev *ovrfl_pdev;
  331. void __iomem *ovrfl_window;
  332. u32 drc;
  333. u32 nr_chans;
  334. struct i82875p_error_info discard;
  335. edac_dbg(0, "\n");
  336. if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
  337. return -ENODEV;
  338. drc = readl(ovrfl_window + I82875P_DRC);
  339. nr_chans = dual_channel_active(drc) + 1;
  340. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  341. layers[0].size = I82875P_NR_CSROWS(nr_chans);
  342. layers[0].is_virt_csrow = true;
  343. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  344. layers[1].size = nr_chans;
  345. layers[1].is_virt_csrow = false;
  346. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
  347. if (!mci) {
  348. rc = -ENOMEM;
  349. goto fail0;
  350. }
  351. edac_dbg(3, "init mci\n");
  352. mci->pdev = &pdev->dev;
  353. mci->mtype_cap = MEM_FLAG_DDR;
  354. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
  355. mci->edac_cap = EDAC_FLAG_UNKNOWN;
  356. mci->mod_name = EDAC_MOD_STR;
  357. mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
  358. mci->dev_name = pci_name(pdev);
  359. mci->edac_check = i82875p_check;
  360. mci->ctl_page_to_phys = NULL;
  361. edac_dbg(3, "init pvt\n");
  362. pvt = (struct i82875p_pvt *)mci->pvt_info;
  363. pvt->ovrfl_pdev = ovrfl_pdev;
  364. pvt->ovrfl_window = ovrfl_window;
  365. i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
  366. i82875p_get_error_info(mci, &discard); /* clear counters */
  367. /* Here we assume that we will never see multiple instances of this
  368. * type of memory controller. The ID is therefore hardcoded to 0.
  369. */
  370. if (edac_mc_add_mc(mci)) {
  371. edac_dbg(3, "failed edac_mc_add_mc()\n");
  372. goto fail1;
  373. }
  374. /* allocating generic PCI control info */
  375. i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  376. if (!i82875p_pci) {
  377. printk(KERN_WARNING
  378. "%s(): Unable to create PCI control\n",
  379. __func__);
  380. printk(KERN_WARNING
  381. "%s(): PCI error report via EDAC not setup\n",
  382. __func__);
  383. }
  384. /* get this far and it's successful */
  385. edac_dbg(3, "success\n");
  386. return 0;
  387. fail1:
  388. edac_mc_free(mci);
  389. fail0:
  390. iounmap(ovrfl_window);
  391. pci_release_regions(ovrfl_pdev);
  392. pci_disable_device(ovrfl_pdev);
  393. /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
  394. return rc;
  395. }
  396. /* returns count (>= 0), or negative on error */
  397. static int i82875p_init_one(struct pci_dev *pdev,
  398. const struct pci_device_id *ent)
  399. {
  400. int rc;
  401. edac_dbg(0, "\n");
  402. i82875p_printk(KERN_INFO, "i82875p init one\n");
  403. if (pci_enable_device(pdev) < 0)
  404. return -EIO;
  405. rc = i82875p_probe1(pdev, ent->driver_data);
  406. if (mci_pdev == NULL)
  407. mci_pdev = pci_dev_get(pdev);
  408. return rc;
  409. }
  410. static void i82875p_remove_one(struct pci_dev *pdev)
  411. {
  412. struct mem_ctl_info *mci;
  413. struct i82875p_pvt *pvt = NULL;
  414. edac_dbg(0, "\n");
  415. if (i82875p_pci)
  416. edac_pci_release_generic_ctl(i82875p_pci);
  417. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  418. return;
  419. pvt = (struct i82875p_pvt *)mci->pvt_info;
  420. if (pvt->ovrfl_window)
  421. iounmap(pvt->ovrfl_window);
  422. if (pvt->ovrfl_pdev) {
  423. #ifdef CORRECT_BIOS
  424. pci_release_regions(pvt->ovrfl_pdev);
  425. #endif /*CORRECT_BIOS */
  426. pci_disable_device(pvt->ovrfl_pdev);
  427. pci_dev_put(pvt->ovrfl_pdev);
  428. }
  429. edac_mc_free(mci);
  430. }
  431. static const struct pci_device_id i82875p_pci_tbl[] = {
  432. {
  433. PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  434. I82875P},
  435. {
  436. 0,
  437. } /* 0 terminated list. */
  438. };
  439. MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
  440. static struct pci_driver i82875p_driver = {
  441. .name = EDAC_MOD_STR,
  442. .probe = i82875p_init_one,
  443. .remove = i82875p_remove_one,
  444. .id_table = i82875p_pci_tbl,
  445. };
  446. static int __init i82875p_init(void)
  447. {
  448. int pci_rc;
  449. edac_dbg(3, "\n");
  450. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  451. opstate_init();
  452. pci_rc = pci_register_driver(&i82875p_driver);
  453. if (pci_rc < 0)
  454. goto fail0;
  455. if (mci_pdev == NULL) {
  456. mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  457. PCI_DEVICE_ID_INTEL_82875_0, NULL);
  458. if (!mci_pdev) {
  459. edac_dbg(0, "875p pci_get_device fail\n");
  460. pci_rc = -ENODEV;
  461. goto fail1;
  462. }
  463. pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
  464. if (pci_rc < 0) {
  465. edac_dbg(0, "875p init fail\n");
  466. pci_rc = -ENODEV;
  467. goto fail1;
  468. }
  469. }
  470. return 0;
  471. fail1:
  472. pci_unregister_driver(&i82875p_driver);
  473. fail0:
  474. pci_dev_put(mci_pdev);
  475. return pci_rc;
  476. }
  477. static void __exit i82875p_exit(void)
  478. {
  479. edac_dbg(3, "\n");
  480. i82875p_remove_one(mci_pdev);
  481. pci_dev_put(mci_pdev);
  482. pci_unregister_driver(&i82875p_driver);
  483. }
  484. module_init(i82875p_init);
  485. module_exit(i82875p_exit);
  486. MODULE_LICENSE("GPL");
  487. MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
  488. MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
  489. module_param(edac_op_state, int, 0444);
  490. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");