i82860_edac.c 9.1 KB

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  1. /*
  2. * Intel 82860 Memory Controller kernel module
  3. * (C) 2005 Red Hat (http://www.redhat.com)
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License.
  6. *
  7. * Written by Ben Woodard <woodard@redhat.com>
  8. * shamelessly copied from and based upon the edac_i82875 driver
  9. * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/pci.h>
  14. #include <linux/pci_ids.h>
  15. #include <linux/edac.h>
  16. #include "edac_module.h"
  17. #define EDAC_MOD_STR "i82860_edac"
  18. #define i82860_printk(level, fmt, arg...) \
  19. edac_printk(level, "i82860", fmt, ##arg)
  20. #define i82860_mc_printk(mci, level, fmt, arg...) \
  21. edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
  22. #ifndef PCI_DEVICE_ID_INTEL_82860_0
  23. #define PCI_DEVICE_ID_INTEL_82860_0 0x2531
  24. #endif /* PCI_DEVICE_ID_INTEL_82860_0 */
  25. #define I82860_MCHCFG 0x50
  26. #define I82860_GBA 0x60
  27. #define I82860_GBA_MASK 0x7FF
  28. #define I82860_GBA_SHIFT 24
  29. #define I82860_ERRSTS 0xC8
  30. #define I82860_EAP 0xE4
  31. #define I82860_DERRCTL_STS 0xE2
  32. enum i82860_chips {
  33. I82860 = 0,
  34. };
  35. struct i82860_dev_info {
  36. const char *ctl_name;
  37. };
  38. struct i82860_error_info {
  39. u16 errsts;
  40. u32 eap;
  41. u16 derrsyn;
  42. u16 errsts2;
  43. };
  44. static const struct i82860_dev_info i82860_devs[] = {
  45. [I82860] = {
  46. .ctl_name = "i82860"},
  47. };
  48. static struct pci_dev *mci_pdev; /* init dev: in case that AGP code
  49. * has already registered driver
  50. */
  51. static struct edac_pci_ctl_info *i82860_pci;
  52. static void i82860_get_error_info(struct mem_ctl_info *mci,
  53. struct i82860_error_info *info)
  54. {
  55. struct pci_dev *pdev;
  56. pdev = to_pci_dev(mci->pdev);
  57. /*
  58. * This is a mess because there is no atomic way to read all the
  59. * registers at once and the registers can transition from CE being
  60. * overwritten by UE.
  61. */
  62. pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
  63. pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  64. pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
  65. pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
  66. pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
  67. /*
  68. * If the error is the same for both reads then the first set of reads
  69. * is valid. If there is a change then there is a CE no info and the
  70. * second set of reads is valid and should be UE info.
  71. */
  72. if (!(info->errsts2 & 0x0003))
  73. return;
  74. if ((info->errsts ^ info->errsts2) & 0x0003) {
  75. pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  76. pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
  77. }
  78. }
  79. static int i82860_process_error_info(struct mem_ctl_info *mci,
  80. struct i82860_error_info *info,
  81. int handle_errors)
  82. {
  83. struct dimm_info *dimm;
  84. int row;
  85. if (!(info->errsts2 & 0x0003))
  86. return 0;
  87. if (!handle_errors)
  88. return 1;
  89. if ((info->errsts ^ info->errsts2) & 0x0003) {
  90. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
  91. -1, -1, -1, "UE overwrote CE", "");
  92. info->errsts = info->errsts2;
  93. }
  94. info->eap >>= PAGE_SHIFT;
  95. row = edac_mc_find_csrow_by_page(mci, info->eap);
  96. dimm = mci->csrows[row]->channels[0]->dimm;
  97. if (info->errsts & 0x0002)
  98. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  99. info->eap, 0, 0,
  100. dimm->location[0], dimm->location[1], -1,
  101. "i82860 UE", "");
  102. else
  103. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  104. info->eap, 0, info->derrsyn,
  105. dimm->location[0], dimm->location[1], -1,
  106. "i82860 CE", "");
  107. return 1;
  108. }
  109. static void i82860_check(struct mem_ctl_info *mci)
  110. {
  111. struct i82860_error_info info;
  112. edac_dbg(1, "MC%d\n", mci->mc_idx);
  113. i82860_get_error_info(mci, &info);
  114. i82860_process_error_info(mci, &info, 1);
  115. }
  116. static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
  117. {
  118. unsigned long last_cumul_size;
  119. u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
  120. u16 value;
  121. u32 cumul_size;
  122. struct csrow_info *csrow;
  123. struct dimm_info *dimm;
  124. int index;
  125. pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
  126. mchcfg_ddim = mchcfg_ddim & 0x180;
  127. last_cumul_size = 0;
  128. /* The group row boundary (GRA) reg values are boundary address
  129. * for each DRAM row with a granularity of 16MB. GRA regs are
  130. * cumulative; therefore GRA15 will contain the total memory contained
  131. * in all eight rows.
  132. */
  133. for (index = 0; index < mci->nr_csrows; index++) {
  134. csrow = mci->csrows[index];
  135. dimm = csrow->channels[0]->dimm;
  136. pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
  137. cumul_size = (value & I82860_GBA_MASK) <<
  138. (I82860_GBA_SHIFT - PAGE_SHIFT);
  139. edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
  140. if (cumul_size == last_cumul_size)
  141. continue; /* not populated */
  142. csrow->first_page = last_cumul_size;
  143. csrow->last_page = cumul_size - 1;
  144. dimm->nr_pages = cumul_size - last_cumul_size;
  145. last_cumul_size = cumul_size;
  146. dimm->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
  147. dimm->mtype = MEM_RMBS;
  148. dimm->dtype = DEV_UNKNOWN;
  149. dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
  150. }
  151. }
  152. static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
  153. {
  154. struct mem_ctl_info *mci;
  155. struct edac_mc_layer layers[2];
  156. struct i82860_error_info discard;
  157. /*
  158. * RDRAM has channels but these don't map onto the csrow abstraction.
  159. * According with the datasheet, there are 2 Rambus channels, supporting
  160. * up to 16 direct RDRAM devices.
  161. * The device groups from the GRA registers seem to map reasonably
  162. * well onto the notion of a chip select row.
  163. * There are 16 GRA registers and since the name is associated with
  164. * the channel and the GRA registers map to physical devices so we are
  165. * going to make 1 channel for group.
  166. */
  167. layers[0].type = EDAC_MC_LAYER_CHANNEL;
  168. layers[0].size = 2;
  169. layers[0].is_virt_csrow = true;
  170. layers[1].type = EDAC_MC_LAYER_SLOT;
  171. layers[1].size = 8;
  172. layers[1].is_virt_csrow = true;
  173. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
  174. if (!mci)
  175. return -ENOMEM;
  176. edac_dbg(3, "init mci\n");
  177. mci->pdev = &pdev->dev;
  178. mci->mtype_cap = MEM_FLAG_DDR;
  179. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
  180. /* I"m not sure about this but I think that all RDRAM is SECDED */
  181. mci->edac_cap = EDAC_FLAG_SECDED;
  182. mci->mod_name = EDAC_MOD_STR;
  183. mci->ctl_name = i82860_devs[dev_idx].ctl_name;
  184. mci->dev_name = pci_name(pdev);
  185. mci->edac_check = i82860_check;
  186. mci->ctl_page_to_phys = NULL;
  187. i82860_init_csrows(mci, pdev);
  188. i82860_get_error_info(mci, &discard); /* clear counters */
  189. /* Here we assume that we will never see multiple instances of this
  190. * type of memory controller. The ID is therefore hardcoded to 0.
  191. */
  192. if (edac_mc_add_mc(mci)) {
  193. edac_dbg(3, "failed edac_mc_add_mc()\n");
  194. goto fail;
  195. }
  196. /* allocating generic PCI control info */
  197. i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  198. if (!i82860_pci) {
  199. printk(KERN_WARNING
  200. "%s(): Unable to create PCI control\n",
  201. __func__);
  202. printk(KERN_WARNING
  203. "%s(): PCI error report via EDAC not setup\n",
  204. __func__);
  205. }
  206. /* get this far and it's successful */
  207. edac_dbg(3, "success\n");
  208. return 0;
  209. fail:
  210. edac_mc_free(mci);
  211. return -ENODEV;
  212. }
  213. /* returns count (>= 0), or negative on error */
  214. static int i82860_init_one(struct pci_dev *pdev,
  215. const struct pci_device_id *ent)
  216. {
  217. int rc;
  218. edac_dbg(0, "\n");
  219. i82860_printk(KERN_INFO, "i82860 init one\n");
  220. if (pci_enable_device(pdev) < 0)
  221. return -EIO;
  222. rc = i82860_probe1(pdev, ent->driver_data);
  223. if (rc == 0)
  224. mci_pdev = pci_dev_get(pdev);
  225. return rc;
  226. }
  227. static void i82860_remove_one(struct pci_dev *pdev)
  228. {
  229. struct mem_ctl_info *mci;
  230. edac_dbg(0, "\n");
  231. if (i82860_pci)
  232. edac_pci_release_generic_ctl(i82860_pci);
  233. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  234. return;
  235. edac_mc_free(mci);
  236. }
  237. static const struct pci_device_id i82860_pci_tbl[] = {
  238. {
  239. PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  240. I82860},
  241. {
  242. 0,
  243. } /* 0 terminated list. */
  244. };
  245. MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
  246. static struct pci_driver i82860_driver = {
  247. .name = EDAC_MOD_STR,
  248. .probe = i82860_init_one,
  249. .remove = i82860_remove_one,
  250. .id_table = i82860_pci_tbl,
  251. };
  252. static int __init i82860_init(void)
  253. {
  254. int pci_rc;
  255. edac_dbg(3, "\n");
  256. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  257. opstate_init();
  258. if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
  259. goto fail0;
  260. if (!mci_pdev) {
  261. mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  262. PCI_DEVICE_ID_INTEL_82860_0, NULL);
  263. if (mci_pdev == NULL) {
  264. edac_dbg(0, "860 pci_get_device fail\n");
  265. pci_rc = -ENODEV;
  266. goto fail1;
  267. }
  268. pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
  269. if (pci_rc < 0) {
  270. edac_dbg(0, "860 init fail\n");
  271. pci_rc = -ENODEV;
  272. goto fail1;
  273. }
  274. }
  275. return 0;
  276. fail1:
  277. pci_unregister_driver(&i82860_driver);
  278. fail0:
  279. pci_dev_put(mci_pdev);
  280. return pci_rc;
  281. }
  282. static void __exit i82860_exit(void)
  283. {
  284. edac_dbg(3, "\n");
  285. pci_unregister_driver(&i82860_driver);
  286. pci_dev_put(mci_pdev);
  287. }
  288. module_init(i82860_init);
  289. module_exit(i82860_exit);
  290. MODULE_LICENSE("GPL");
  291. MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
  292. "Ben Woodard <woodard@redhat.com>");
  293. MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
  294. module_param(edac_op_state, int, 0444);
  295. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");