i82443bxgx_edac.c 14 KB

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  1. /*
  2. * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
  3. * module (C) 2006 Tim Small
  4. *
  5. * This file may be distributed under the terms of the GNU General
  6. * Public License.
  7. *
  8. * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
  9. * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
  10. * others.
  11. *
  12. * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
  13. *
  14. * Written with reference to 82443BX Host Bridge Datasheet:
  15. * http://download.intel.com/design/chipsets/datashts/29063301.pdf
  16. * references to this document given in [].
  17. *
  18. * This module doesn't support the 440LX, but it may be possible to
  19. * make it do so (the 440LX's register definitions are different, but
  20. * not completely so - I haven't studied them in enough detail to know
  21. * how easy this would be).
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/pci_ids.h>
  27. #include <linux/edac.h>
  28. #include "edac_module.h"
  29. #define EDAC_MOD_STR "i82443bxgx_edac"
  30. /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
  31. * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
  32. * rows" "The 82443BX supports multiple-bit error detection and
  33. * single-bit error correction when ECC mode is enabled and
  34. * single/multi-bit error detection when correction is disabled.
  35. * During writes to the DRAM, the 82443BX generates ECC for the data
  36. * on a QWord basis. Partial QWord writes require a read-modify-write
  37. * cycle when ECC is enabled."
  38. */
  39. /* "Additionally, the 82443BX ensures that the data is corrected in
  40. * main memory so that accumulation of errors is prevented. Another
  41. * error within the same QWord would result in a double-bit error
  42. * which is unrecoverable. This is known as hardware scrubbing since
  43. * it requires no software intervention to correct the data in memory."
  44. */
  45. /* [Also see page 100 (section 4.3), "DRAM Interface"]
  46. * [Also see page 112 (section 4.6.1.4), ECC]
  47. */
  48. #define I82443BXGX_NR_CSROWS 8
  49. #define I82443BXGX_NR_CHANS 1
  50. #define I82443BXGX_NR_DIMMS 4
  51. /* 82443 PCI Device 0 */
  52. #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
  53. * config space offset */
  54. #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
  55. * row is non-ECC */
  56. #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
  57. #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
  58. #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
  59. #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
  60. #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
  61. #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
  62. #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
  63. /* 82443 PCI Device 0 */
  64. #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
  65. * config space offset, Error Address
  66. * Pointer Register */
  67. #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
  68. #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
  69. #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
  70. #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
  71. * config space offset. */
  72. #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
  73. #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
  74. #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
  75. * config space offset. */
  76. #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
  77. #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
  78. #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
  79. #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
  80. #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
  81. * config space offset. */
  82. #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
  83. #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
  84. #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
  85. #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
  86. #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
  87. * config space offset. */
  88. /* FIXME - don't poll when ECC disabled? */
  89. struct i82443bxgx_edacmc_error_info {
  90. u32 eap;
  91. };
  92. static struct edac_pci_ctl_info *i82443bxgx_pci;
  93. static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
  94. * already registered driver
  95. */
  96. static int i82443bxgx_registered = 1;
  97. static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
  98. struct i82443bxgx_edacmc_error_info
  99. *info)
  100. {
  101. struct pci_dev *pdev;
  102. pdev = to_pci_dev(mci->pdev);
  103. pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
  104. if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
  105. /* Clear error to allow next error to be reported [p.61] */
  106. pci_write_bits32(pdev, I82443BXGX_EAP,
  107. I82443BXGX_EAP_OFFSET_SBE,
  108. I82443BXGX_EAP_OFFSET_SBE);
  109. if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
  110. /* Clear error to allow next error to be reported [p.61] */
  111. pci_write_bits32(pdev, I82443BXGX_EAP,
  112. I82443BXGX_EAP_OFFSET_MBE,
  113. I82443BXGX_EAP_OFFSET_MBE);
  114. }
  115. static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
  116. struct
  117. i82443bxgx_edacmc_error_info
  118. *info, int handle_errors)
  119. {
  120. int error_found = 0;
  121. u32 eapaddr, page, pageoffset;
  122. /* bits 30:12 hold the 4kb block in which the error occurred
  123. * [p.61] */
  124. eapaddr = (info->eap & 0xfffff000);
  125. page = eapaddr >> PAGE_SHIFT;
  126. pageoffset = eapaddr - (page << PAGE_SHIFT);
  127. if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
  128. error_found = 1;
  129. if (handle_errors)
  130. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  131. page, pageoffset, 0,
  132. edac_mc_find_csrow_by_page(mci, page),
  133. 0, -1, mci->ctl_name, "");
  134. }
  135. if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
  136. error_found = 1;
  137. if (handle_errors)
  138. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  139. page, pageoffset, 0,
  140. edac_mc_find_csrow_by_page(mci, page),
  141. 0, -1, mci->ctl_name, "");
  142. }
  143. return error_found;
  144. }
  145. static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
  146. {
  147. struct i82443bxgx_edacmc_error_info info;
  148. edac_dbg(1, "MC%d\n", mci->mc_idx);
  149. i82443bxgx_edacmc_get_error_info(mci, &info);
  150. i82443bxgx_edacmc_process_error_info(mci, &info, 1);
  151. }
  152. static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
  153. struct pci_dev *pdev,
  154. enum edac_type edac_mode,
  155. enum mem_type mtype)
  156. {
  157. struct csrow_info *csrow;
  158. struct dimm_info *dimm;
  159. int index;
  160. u8 drbar, dramc;
  161. u32 row_base, row_high_limit, row_high_limit_last;
  162. pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
  163. row_high_limit_last = 0;
  164. for (index = 0; index < mci->nr_csrows; index++) {
  165. csrow = mci->csrows[index];
  166. dimm = csrow->channels[0]->dimm;
  167. pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
  168. edac_dbg(1, "MC%d: Row=%d DRB = %#0x\n",
  169. mci->mc_idx, index, drbar);
  170. row_high_limit = ((u32) drbar << 23);
  171. /* find the DRAM Chip Select Base address and mask */
  172. edac_dbg(1, "MC%d: Row=%d, Boundary Address=%#0x, Last = %#0x\n",
  173. mci->mc_idx, index, row_high_limit,
  174. row_high_limit_last);
  175. /* 440GX goes to 2GB, represented with a DRB of 0. */
  176. if (row_high_limit_last && !row_high_limit)
  177. row_high_limit = 1UL << 31;
  178. /* This row is empty [p.49] */
  179. if (row_high_limit == row_high_limit_last)
  180. continue;
  181. row_base = row_high_limit_last;
  182. csrow->first_page = row_base >> PAGE_SHIFT;
  183. csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
  184. dimm->nr_pages = csrow->last_page - csrow->first_page + 1;
  185. /* EAP reports in 4kilobyte granularity [61] */
  186. dimm->grain = 1 << 12;
  187. dimm->mtype = mtype;
  188. /* I don't think 440BX can tell you device type? FIXME? */
  189. dimm->dtype = DEV_UNKNOWN;
  190. /* Mode is global to all rows on 440BX */
  191. dimm->edac_mode = edac_mode;
  192. row_high_limit_last = row_high_limit;
  193. }
  194. }
  195. static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
  196. {
  197. struct mem_ctl_info *mci;
  198. struct edac_mc_layer layers[2];
  199. u8 dramc;
  200. u32 nbxcfg, ecc_mode;
  201. enum mem_type mtype;
  202. enum edac_type edac_mode;
  203. edac_dbg(0, "MC:\n");
  204. /* Something is really hosed if PCI config space reads from
  205. * the MC aren't working.
  206. */
  207. if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
  208. return -EIO;
  209. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  210. layers[0].size = I82443BXGX_NR_CSROWS;
  211. layers[0].is_virt_csrow = true;
  212. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  213. layers[1].size = I82443BXGX_NR_CHANS;
  214. layers[1].is_virt_csrow = false;
  215. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
  216. if (mci == NULL)
  217. return -ENOMEM;
  218. edac_dbg(0, "MC: mci = %p\n", mci);
  219. mci->pdev = &pdev->dev;
  220. mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
  221. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  222. pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
  223. switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
  224. case I82443BXGX_DRAMC_DRAM_IS_EDO:
  225. mtype = MEM_EDO;
  226. break;
  227. case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
  228. mtype = MEM_SDR;
  229. break;
  230. case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
  231. mtype = MEM_RDR;
  232. break;
  233. default:
  234. edac_dbg(0, "Unknown/reserved DRAM type value in DRAMC register!\n");
  235. mtype = -MEM_UNKNOWN;
  236. }
  237. if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
  238. mci->edac_cap = mci->edac_ctl_cap;
  239. else
  240. mci->edac_cap = EDAC_FLAG_NONE;
  241. mci->scrub_cap = SCRUB_FLAG_HW_SRC;
  242. pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
  243. ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
  244. (BIT(0) | BIT(1)));
  245. mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
  246. ? SCRUB_HW_SRC : SCRUB_NONE;
  247. switch (ecc_mode) {
  248. case I82443BXGX_NBXCFG_INTEGRITY_NONE:
  249. edac_mode = EDAC_NONE;
  250. break;
  251. case I82443BXGX_NBXCFG_INTEGRITY_EC:
  252. edac_mode = EDAC_EC;
  253. break;
  254. case I82443BXGX_NBXCFG_INTEGRITY_ECC:
  255. case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
  256. edac_mode = EDAC_SECDED;
  257. break;
  258. default:
  259. edac_dbg(0, "Unknown/reserved ECC state in NBXCFG register!\n");
  260. edac_mode = EDAC_UNKNOWN;
  261. break;
  262. }
  263. i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
  264. /* Many BIOSes don't clear error flags on boot, so do this
  265. * here, or we get "phantom" errors occurring at module-load
  266. * time. */
  267. pci_write_bits32(pdev, I82443BXGX_EAP,
  268. (I82443BXGX_EAP_OFFSET_SBE |
  269. I82443BXGX_EAP_OFFSET_MBE),
  270. (I82443BXGX_EAP_OFFSET_SBE |
  271. I82443BXGX_EAP_OFFSET_MBE));
  272. mci->mod_name = EDAC_MOD_STR;
  273. mci->ctl_name = "I82443BXGX";
  274. mci->dev_name = pci_name(pdev);
  275. mci->edac_check = i82443bxgx_edacmc_check;
  276. mci->ctl_page_to_phys = NULL;
  277. if (edac_mc_add_mc(mci)) {
  278. edac_dbg(3, "failed edac_mc_add_mc()\n");
  279. goto fail;
  280. }
  281. /* allocating generic PCI control info */
  282. i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  283. if (!i82443bxgx_pci) {
  284. printk(KERN_WARNING
  285. "%s(): Unable to create PCI control\n",
  286. __func__);
  287. printk(KERN_WARNING
  288. "%s(): PCI error report via EDAC not setup\n",
  289. __func__);
  290. }
  291. edac_dbg(3, "MC: success\n");
  292. return 0;
  293. fail:
  294. edac_mc_free(mci);
  295. return -ENODEV;
  296. }
  297. /* returns count (>= 0), or negative on error */
  298. static int i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
  299. const struct pci_device_id *ent)
  300. {
  301. int rc;
  302. edac_dbg(0, "MC:\n");
  303. /* don't need to call pci_enable_device() */
  304. rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
  305. if (mci_pdev == NULL)
  306. mci_pdev = pci_dev_get(pdev);
  307. return rc;
  308. }
  309. static void i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
  310. {
  311. struct mem_ctl_info *mci;
  312. edac_dbg(0, "\n");
  313. if (i82443bxgx_pci)
  314. edac_pci_release_generic_ctl(i82443bxgx_pci);
  315. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  316. return;
  317. edac_mc_free(mci);
  318. }
  319. static const struct pci_device_id i82443bxgx_pci_tbl[] = {
  320. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
  321. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
  322. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
  323. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
  324. {0,} /* 0 terminated list. */
  325. };
  326. MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
  327. static struct pci_driver i82443bxgx_edacmc_driver = {
  328. .name = EDAC_MOD_STR,
  329. .probe = i82443bxgx_edacmc_init_one,
  330. .remove = i82443bxgx_edacmc_remove_one,
  331. .id_table = i82443bxgx_pci_tbl,
  332. };
  333. static int __init i82443bxgx_edacmc_init(void)
  334. {
  335. int pci_rc;
  336. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  337. opstate_init();
  338. pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
  339. if (pci_rc < 0)
  340. goto fail0;
  341. if (mci_pdev == NULL) {
  342. const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
  343. int i = 0;
  344. i82443bxgx_registered = 0;
  345. while (mci_pdev == NULL && id->vendor != 0) {
  346. mci_pdev = pci_get_device(id->vendor,
  347. id->device, NULL);
  348. i++;
  349. id = &i82443bxgx_pci_tbl[i];
  350. }
  351. if (!mci_pdev) {
  352. edac_dbg(0, "i82443bxgx pci_get_device fail\n");
  353. pci_rc = -ENODEV;
  354. goto fail1;
  355. }
  356. pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
  357. if (pci_rc < 0) {
  358. edac_dbg(0, "i82443bxgx init fail\n");
  359. pci_rc = -ENODEV;
  360. goto fail1;
  361. }
  362. }
  363. return 0;
  364. fail1:
  365. pci_unregister_driver(&i82443bxgx_edacmc_driver);
  366. fail0:
  367. pci_dev_put(mci_pdev);
  368. return pci_rc;
  369. }
  370. static void __exit i82443bxgx_edacmc_exit(void)
  371. {
  372. pci_unregister_driver(&i82443bxgx_edacmc_driver);
  373. if (!i82443bxgx_registered)
  374. i82443bxgx_edacmc_remove_one(mci_pdev);
  375. pci_dev_put(mci_pdev);
  376. }
  377. module_init(i82443bxgx_edacmc_init);
  378. module_exit(i82443bxgx_edacmc_exit);
  379. MODULE_LICENSE("GPL");
  380. MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
  381. MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
  382. module_param(edac_op_state, int, 0444);
  383. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");