i7core_edac.c 61 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* Intel i7 core/Nehalem Memory Controller kernel module
  3. *
  4. * This driver supports the memory controllers found on the Intel
  5. * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
  6. * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
  7. * and Westmere-EP.
  8. *
  9. * Copyright (c) 2009-2010 by:
  10. * Mauro Carvalho Chehab
  11. *
  12. * Red Hat Inc. https://www.redhat.com
  13. *
  14. * Forked and adapted from the i5400_edac driver
  15. *
  16. * Based on the following public Intel datasheets:
  17. * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
  18. * Datasheet, Volume 2:
  19. * http://download.intel.com/design/processor/datashts/320835.pdf
  20. * Intel Xeon Processor 5500 Series Datasheet Volume 2
  21. * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
  22. * also available at:
  23. * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  24. */
  25. #include <linux/module.h>
  26. #include <linux/init.h>
  27. #include <linux/pci.h>
  28. #include <linux/pci_ids.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/dmi.h>
  32. #include <linux/edac.h>
  33. #include <linux/mmzone.h>
  34. #include <linux/smp.h>
  35. #include <asm/mce.h>
  36. #include <asm/processor.h>
  37. #include <asm/div64.h>
  38. #include "edac_module.h"
  39. /* Static vars */
  40. static LIST_HEAD(i7core_edac_list);
  41. static DEFINE_MUTEX(i7core_edac_lock);
  42. static int probed;
  43. static int use_pci_fixup;
  44. module_param(use_pci_fixup, int, 0444);
  45. MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
  46. /*
  47. * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
  48. * registers start at bus 255, and are not reported by BIOS.
  49. * We currently find devices with only 2 sockets. In order to support more QPI
  50. * Quick Path Interconnect, just increment this number.
  51. */
  52. #define MAX_SOCKET_BUSES 2
  53. /*
  54. * Alter this version for the module when modifications are made
  55. */
  56. #define I7CORE_REVISION " Ver: 1.0.0"
  57. #define EDAC_MOD_STR "i7core_edac"
  58. /*
  59. * Debug macros
  60. */
  61. #define i7core_printk(level, fmt, arg...) \
  62. edac_printk(level, "i7core", fmt, ##arg)
  63. #define i7core_mc_printk(mci, level, fmt, arg...) \
  64. edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
  65. /*
  66. * i7core Memory Controller Registers
  67. */
  68. /* OFFSETS for Device 0 Function 0 */
  69. #define MC_CFG_CONTROL 0x90
  70. #define MC_CFG_UNLOCK 0x02
  71. #define MC_CFG_LOCK 0x00
  72. /* OFFSETS for Device 3 Function 0 */
  73. #define MC_CONTROL 0x48
  74. #define MC_STATUS 0x4c
  75. #define MC_MAX_DOD 0x64
  76. /*
  77. * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet:
  78. * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  79. */
  80. #define MC_TEST_ERR_RCV1 0x60
  81. #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
  82. #define MC_TEST_ERR_RCV0 0x64
  83. #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
  84. #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
  85. /* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */
  86. #define MC_SSRCONTROL 0x48
  87. #define SSR_MODE_DISABLE 0x00
  88. #define SSR_MODE_ENABLE 0x01
  89. #define SSR_MODE_MASK 0x03
  90. #define MC_SCRUB_CONTROL 0x4c
  91. #define STARTSCRUB (1 << 24)
  92. #define SCRUBINTERVAL_MASK 0xffffff
  93. #define MC_COR_ECC_CNT_0 0x80
  94. #define MC_COR_ECC_CNT_1 0x84
  95. #define MC_COR_ECC_CNT_2 0x88
  96. #define MC_COR_ECC_CNT_3 0x8c
  97. #define MC_COR_ECC_CNT_4 0x90
  98. #define MC_COR_ECC_CNT_5 0x94
  99. #define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
  100. #define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
  101. /* OFFSETS for Devices 4,5 and 6 Function 0 */
  102. #define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
  103. #define THREE_DIMMS_PRESENT (1 << 24)
  104. #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
  105. #define QUAD_RANK_PRESENT (1 << 22)
  106. #define REGISTERED_DIMM (1 << 15)
  107. #define MC_CHANNEL_MAPPER 0x60
  108. #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
  109. #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
  110. #define MC_CHANNEL_RANK_PRESENT 0x7c
  111. #define RANK_PRESENT_MASK 0xffff
  112. #define MC_CHANNEL_ADDR_MATCH 0xf0
  113. #define MC_CHANNEL_ERROR_MASK 0xf8
  114. #define MC_CHANNEL_ERROR_INJECT 0xfc
  115. #define INJECT_ADDR_PARITY 0x10
  116. #define INJECT_ECC 0x08
  117. #define MASK_CACHELINE 0x06
  118. #define MASK_FULL_CACHELINE 0x06
  119. #define MASK_MSB32_CACHELINE 0x04
  120. #define MASK_LSB32_CACHELINE 0x02
  121. #define NO_MASK_CACHELINE 0x00
  122. #define REPEAT_EN 0x01
  123. /* OFFSETS for Devices 4,5 and 6 Function 1 */
  124. #define MC_DOD_CH_DIMM0 0x48
  125. #define MC_DOD_CH_DIMM1 0x4c
  126. #define MC_DOD_CH_DIMM2 0x50
  127. #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
  128. #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
  129. #define DIMM_PRESENT_MASK (1 << 9)
  130. #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
  131. #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
  132. #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
  133. #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
  134. #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
  135. #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
  136. #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
  137. #define MC_DOD_NUMCOL_MASK 3
  138. #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
  139. #define MC_RANK_PRESENT 0x7c
  140. #define MC_SAG_CH_0 0x80
  141. #define MC_SAG_CH_1 0x84
  142. #define MC_SAG_CH_2 0x88
  143. #define MC_SAG_CH_3 0x8c
  144. #define MC_SAG_CH_4 0x90
  145. #define MC_SAG_CH_5 0x94
  146. #define MC_SAG_CH_6 0x98
  147. #define MC_SAG_CH_7 0x9c
  148. #define MC_RIR_LIMIT_CH_0 0x40
  149. #define MC_RIR_LIMIT_CH_1 0x44
  150. #define MC_RIR_LIMIT_CH_2 0x48
  151. #define MC_RIR_LIMIT_CH_3 0x4C
  152. #define MC_RIR_LIMIT_CH_4 0x50
  153. #define MC_RIR_LIMIT_CH_5 0x54
  154. #define MC_RIR_LIMIT_CH_6 0x58
  155. #define MC_RIR_LIMIT_CH_7 0x5C
  156. #define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
  157. #define MC_RIR_WAY_CH 0x80
  158. #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
  159. #define MC_RIR_WAY_RANK_MASK 0x7
  160. /*
  161. * i7core structs
  162. */
  163. #define NUM_CHANS 3
  164. #define MAX_DIMMS 3 /* Max DIMMS per channel */
  165. #define MAX_MCR_FUNC 4
  166. #define MAX_CHAN_FUNC 3
  167. struct i7core_info {
  168. u32 mc_control;
  169. u32 mc_status;
  170. u32 max_dod;
  171. u32 ch_map;
  172. };
  173. struct i7core_inject {
  174. int enable;
  175. u32 section;
  176. u32 type;
  177. u32 eccmask;
  178. /* Error address mask */
  179. int channel, dimm, rank, bank, page, col;
  180. };
  181. struct i7core_channel {
  182. bool is_3dimms_present;
  183. bool is_single_4rank;
  184. bool has_4rank;
  185. u32 dimms;
  186. };
  187. struct pci_id_descr {
  188. int dev;
  189. int func;
  190. int dev_id;
  191. int optional;
  192. };
  193. struct pci_id_table {
  194. const struct pci_id_descr *descr;
  195. int n_devs;
  196. };
  197. struct i7core_dev {
  198. struct list_head list;
  199. u8 socket;
  200. struct pci_dev **pdev;
  201. int n_devs;
  202. struct mem_ctl_info *mci;
  203. };
  204. struct i7core_pvt {
  205. struct device *addrmatch_dev, *chancounts_dev;
  206. struct pci_dev *pci_noncore;
  207. struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
  208. struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
  209. struct i7core_dev *i7core_dev;
  210. struct i7core_info info;
  211. struct i7core_inject inject;
  212. struct i7core_channel channel[NUM_CHANS];
  213. int ce_count_available;
  214. /* ECC corrected errors counts per udimm */
  215. unsigned long udimm_ce_count[MAX_DIMMS];
  216. int udimm_last_ce_count[MAX_DIMMS];
  217. /* ECC corrected errors counts per rdimm */
  218. unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
  219. int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
  220. bool is_registered, enable_scrub;
  221. /* DCLK Frequency used for computing scrub rate */
  222. int dclk_freq;
  223. /* Struct to control EDAC polling */
  224. struct edac_pci_ctl_info *i7core_pci;
  225. };
  226. #define PCI_DESCR(device, function, device_id) \
  227. .dev = (device), \
  228. .func = (function), \
  229. .dev_id = (device_id)
  230. static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
  231. /* Memory controller */
  232. { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
  233. { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
  234. /* Exists only for RDIMM */
  235. { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
  236. { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
  237. /* Channel 0 */
  238. { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
  239. { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
  240. { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
  241. { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
  242. /* Channel 1 */
  243. { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
  244. { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
  245. { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
  246. { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
  247. /* Channel 2 */
  248. { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
  249. { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
  250. { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
  251. { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
  252. /* Generic Non-core registers */
  253. /*
  254. * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
  255. * On Xeon 55xx, however, it has a different id (8086:2c40). So,
  256. * the probing code needs to test for the other address in case of
  257. * failure of this one
  258. */
  259. { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
  260. };
  261. static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
  262. { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
  263. { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
  264. { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
  265. { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
  266. { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
  267. { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
  268. { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
  269. { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
  270. { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
  271. { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
  272. { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
  273. /*
  274. * This is the PCI device has an alternate address on some
  275. * processors like Core i7 860
  276. */
  277. { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
  278. };
  279. static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
  280. /* Memory controller */
  281. { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
  282. { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
  283. /* Exists only for RDIMM */
  284. { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
  285. { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
  286. /* Channel 0 */
  287. { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
  288. { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
  289. { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
  290. { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
  291. /* Channel 1 */
  292. { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
  293. { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
  294. { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
  295. { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
  296. /* Channel 2 */
  297. { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
  298. { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
  299. { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
  300. { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
  301. /* Generic Non-core registers */
  302. { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
  303. };
  304. #define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
  305. static const struct pci_id_table pci_dev_table[] = {
  306. PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
  307. PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
  308. PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
  309. {0,} /* 0 terminated list. */
  310. };
  311. /*
  312. * pci_device_id table for which devices we are looking for
  313. */
  314. static const struct pci_device_id i7core_pci_tbl[] = {
  315. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
  316. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
  317. {0,} /* 0 terminated list. */
  318. };
  319. /****************************************************************************
  320. Ancillary status routines
  321. ****************************************************************************/
  322. /* MC_CONTROL bits */
  323. #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
  324. #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
  325. /* MC_STATUS bits */
  326. #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
  327. #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
  328. /* MC_MAX_DOD read functions */
  329. static inline int numdimms(u32 dimms)
  330. {
  331. return (dimms & 0x3) + 1;
  332. }
  333. static inline int numrank(u32 rank)
  334. {
  335. static const int ranks[] = { 1, 2, 4, -EINVAL };
  336. return ranks[rank & 0x3];
  337. }
  338. static inline int numbank(u32 bank)
  339. {
  340. static const int banks[] = { 4, 8, 16, -EINVAL };
  341. return banks[bank & 0x3];
  342. }
  343. static inline int numrow(u32 row)
  344. {
  345. static const int rows[] = {
  346. 1 << 12, 1 << 13, 1 << 14, 1 << 15,
  347. 1 << 16, -EINVAL, -EINVAL, -EINVAL,
  348. };
  349. return rows[row & 0x7];
  350. }
  351. static inline int numcol(u32 col)
  352. {
  353. static const int cols[] = {
  354. 1 << 10, 1 << 11, 1 << 12, -EINVAL,
  355. };
  356. return cols[col & 0x3];
  357. }
  358. static struct i7core_dev *get_i7core_dev(u8 socket)
  359. {
  360. struct i7core_dev *i7core_dev;
  361. list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
  362. if (i7core_dev->socket == socket)
  363. return i7core_dev;
  364. }
  365. return NULL;
  366. }
  367. static struct i7core_dev *alloc_i7core_dev(u8 socket,
  368. const struct pci_id_table *table)
  369. {
  370. struct i7core_dev *i7core_dev;
  371. i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
  372. if (!i7core_dev)
  373. return NULL;
  374. i7core_dev->pdev = kcalloc(table->n_devs, sizeof(*i7core_dev->pdev),
  375. GFP_KERNEL);
  376. if (!i7core_dev->pdev) {
  377. kfree(i7core_dev);
  378. return NULL;
  379. }
  380. i7core_dev->socket = socket;
  381. i7core_dev->n_devs = table->n_devs;
  382. list_add_tail(&i7core_dev->list, &i7core_edac_list);
  383. return i7core_dev;
  384. }
  385. static void free_i7core_dev(struct i7core_dev *i7core_dev)
  386. {
  387. list_del(&i7core_dev->list);
  388. kfree(i7core_dev->pdev);
  389. kfree(i7core_dev);
  390. }
  391. /****************************************************************************
  392. Memory check routines
  393. ****************************************************************************/
  394. static int get_dimm_config(struct mem_ctl_info *mci)
  395. {
  396. struct i7core_pvt *pvt = mci->pvt_info;
  397. struct pci_dev *pdev;
  398. int i, j;
  399. enum edac_type mode;
  400. enum mem_type mtype;
  401. struct dimm_info *dimm;
  402. /* Get data from the MC register, function 0 */
  403. pdev = pvt->pci_mcr[0];
  404. if (!pdev)
  405. return -ENODEV;
  406. /* Device 3 function 0 reads */
  407. pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
  408. pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
  409. pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
  410. pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
  411. edac_dbg(0, "QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
  412. pvt->i7core_dev->socket, pvt->info.mc_control,
  413. pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map);
  414. if (ECC_ENABLED(pvt)) {
  415. edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
  416. if (ECCx8(pvt))
  417. mode = EDAC_S8ECD8ED;
  418. else
  419. mode = EDAC_S4ECD4ED;
  420. } else {
  421. edac_dbg(0, "ECC disabled\n");
  422. mode = EDAC_NONE;
  423. }
  424. /* FIXME: need to handle the error codes */
  425. edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n",
  426. numdimms(pvt->info.max_dod),
  427. numrank(pvt->info.max_dod >> 2),
  428. numbank(pvt->info.max_dod >> 4),
  429. numrow(pvt->info.max_dod >> 6),
  430. numcol(pvt->info.max_dod >> 9));
  431. for (i = 0; i < NUM_CHANS; i++) {
  432. u32 data, dimm_dod[3], value[8];
  433. if (!pvt->pci_ch[i][0])
  434. continue;
  435. if (!CH_ACTIVE(pvt, i)) {
  436. edac_dbg(0, "Channel %i is not active\n", i);
  437. continue;
  438. }
  439. if (CH_DISABLED(pvt, i)) {
  440. edac_dbg(0, "Channel %i is disabled\n", i);
  441. continue;
  442. }
  443. /* Devices 4-6 function 0 */
  444. pci_read_config_dword(pvt->pci_ch[i][0],
  445. MC_CHANNEL_DIMM_INIT_PARAMS, &data);
  446. if (data & THREE_DIMMS_PRESENT)
  447. pvt->channel[i].is_3dimms_present = true;
  448. if (data & SINGLE_QUAD_RANK_PRESENT)
  449. pvt->channel[i].is_single_4rank = true;
  450. if (data & QUAD_RANK_PRESENT)
  451. pvt->channel[i].has_4rank = true;
  452. if (data & REGISTERED_DIMM)
  453. mtype = MEM_RDDR3;
  454. else
  455. mtype = MEM_DDR3;
  456. /* Devices 4-6 function 1 */
  457. pci_read_config_dword(pvt->pci_ch[i][1],
  458. MC_DOD_CH_DIMM0, &dimm_dod[0]);
  459. pci_read_config_dword(pvt->pci_ch[i][1],
  460. MC_DOD_CH_DIMM1, &dimm_dod[1]);
  461. pci_read_config_dword(pvt->pci_ch[i][1],
  462. MC_DOD_CH_DIMM2, &dimm_dod[2]);
  463. edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n",
  464. i,
  465. RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
  466. data,
  467. pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
  468. pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
  469. pvt->channel[i].has_4rank ? "HAS_4R " : "",
  470. (data & REGISTERED_DIMM) ? 'R' : 'U');
  471. for (j = 0; j < 3; j++) {
  472. u32 banks, ranks, rows, cols;
  473. u32 size, npages;
  474. if (!DIMM_PRESENT(dimm_dod[j]))
  475. continue;
  476. dimm = edac_get_dimm(mci, i, j, 0);
  477. banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
  478. ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
  479. rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
  480. cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
  481. /* DDR3 has 8 I/O banks */
  482. size = (rows * cols * banks * ranks) >> (20 - 3);
  483. edac_dbg(0, "\tdimm %d %d MiB offset: %x, bank: %d, rank: %d, row: %#x, col: %#x\n",
  484. j, size,
  485. RANKOFFSET(dimm_dod[j]),
  486. banks, ranks, rows, cols);
  487. npages = MiB_TO_PAGES(size);
  488. dimm->nr_pages = npages;
  489. switch (banks) {
  490. case 4:
  491. dimm->dtype = DEV_X4;
  492. break;
  493. case 8:
  494. dimm->dtype = DEV_X8;
  495. break;
  496. case 16:
  497. dimm->dtype = DEV_X16;
  498. break;
  499. default:
  500. dimm->dtype = DEV_UNKNOWN;
  501. }
  502. snprintf(dimm->label, sizeof(dimm->label),
  503. "CPU#%uChannel#%u_DIMM#%u",
  504. pvt->i7core_dev->socket, i, j);
  505. dimm->grain = 8;
  506. dimm->edac_mode = mode;
  507. dimm->mtype = mtype;
  508. }
  509. pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
  510. pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
  511. pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
  512. pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
  513. pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
  514. pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
  515. pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
  516. pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
  517. edac_dbg(1, "\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
  518. for (j = 0; j < 8; j++)
  519. edac_dbg(1, "\t\t%#x\t%#x\t%#x\n",
  520. (value[j] >> 27) & 0x1,
  521. (value[j] >> 24) & 0x7,
  522. (value[j] & ((1 << 24) - 1)));
  523. }
  524. return 0;
  525. }
  526. /****************************************************************************
  527. Error insertion routines
  528. ****************************************************************************/
  529. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  530. /* The i7core has independent error injection features per channel.
  531. However, to have a simpler code, we don't allow enabling error injection
  532. on more than one channel.
  533. Also, since a change at an inject parameter will be applied only at enable,
  534. we're disabling error injection on all write calls to the sysfs nodes that
  535. controls the error code injection.
  536. */
  537. static int disable_inject(const struct mem_ctl_info *mci)
  538. {
  539. struct i7core_pvt *pvt = mci->pvt_info;
  540. pvt->inject.enable = 0;
  541. if (!pvt->pci_ch[pvt->inject.channel][0])
  542. return -ENODEV;
  543. pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
  544. MC_CHANNEL_ERROR_INJECT, 0);
  545. return 0;
  546. }
  547. /*
  548. * i7core inject inject.section
  549. *
  550. * accept and store error injection inject.section value
  551. * bit 0 - refers to the lower 32-byte half cacheline
  552. * bit 1 - refers to the upper 32-byte half cacheline
  553. */
  554. static ssize_t i7core_inject_section_store(struct device *dev,
  555. struct device_attribute *mattr,
  556. const char *data, size_t count)
  557. {
  558. struct mem_ctl_info *mci = to_mci(dev);
  559. struct i7core_pvt *pvt = mci->pvt_info;
  560. unsigned long value;
  561. int rc;
  562. if (pvt->inject.enable)
  563. disable_inject(mci);
  564. rc = kstrtoul(data, 10, &value);
  565. if ((rc < 0) || (value > 3))
  566. return -EIO;
  567. pvt->inject.section = (u32) value;
  568. return count;
  569. }
  570. static ssize_t i7core_inject_section_show(struct device *dev,
  571. struct device_attribute *mattr,
  572. char *data)
  573. {
  574. struct mem_ctl_info *mci = to_mci(dev);
  575. struct i7core_pvt *pvt = mci->pvt_info;
  576. return sprintf(data, "0x%08x\n", pvt->inject.section);
  577. }
  578. /*
  579. * i7core inject.type
  580. *
  581. * accept and store error injection inject.section value
  582. * bit 0 - repeat enable - Enable error repetition
  583. * bit 1 - inject ECC error
  584. * bit 2 - inject parity error
  585. */
  586. static ssize_t i7core_inject_type_store(struct device *dev,
  587. struct device_attribute *mattr,
  588. const char *data, size_t count)
  589. {
  590. struct mem_ctl_info *mci = to_mci(dev);
  591. struct i7core_pvt *pvt = mci->pvt_info;
  592. unsigned long value;
  593. int rc;
  594. if (pvt->inject.enable)
  595. disable_inject(mci);
  596. rc = kstrtoul(data, 10, &value);
  597. if ((rc < 0) || (value > 7))
  598. return -EIO;
  599. pvt->inject.type = (u32) value;
  600. return count;
  601. }
  602. static ssize_t i7core_inject_type_show(struct device *dev,
  603. struct device_attribute *mattr,
  604. char *data)
  605. {
  606. struct mem_ctl_info *mci = to_mci(dev);
  607. struct i7core_pvt *pvt = mci->pvt_info;
  608. return sprintf(data, "0x%08x\n", pvt->inject.type);
  609. }
  610. /*
  611. * i7core_inject_inject.eccmask_store
  612. *
  613. * The type of error (UE/CE) will depend on the inject.eccmask value:
  614. * Any bits set to a 1 will flip the corresponding ECC bit
  615. * Correctable errors can be injected by flipping 1 bit or the bits within
  616. * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
  617. * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
  618. * uncorrectable error to be injected.
  619. */
  620. static ssize_t i7core_inject_eccmask_store(struct device *dev,
  621. struct device_attribute *mattr,
  622. const char *data, size_t count)
  623. {
  624. struct mem_ctl_info *mci = to_mci(dev);
  625. struct i7core_pvt *pvt = mci->pvt_info;
  626. unsigned long value;
  627. int rc;
  628. if (pvt->inject.enable)
  629. disable_inject(mci);
  630. rc = kstrtoul(data, 10, &value);
  631. if (rc < 0)
  632. return -EIO;
  633. pvt->inject.eccmask = (u32) value;
  634. return count;
  635. }
  636. static ssize_t i7core_inject_eccmask_show(struct device *dev,
  637. struct device_attribute *mattr,
  638. char *data)
  639. {
  640. struct mem_ctl_info *mci = to_mci(dev);
  641. struct i7core_pvt *pvt = mci->pvt_info;
  642. return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
  643. }
  644. /*
  645. * i7core_addrmatch
  646. *
  647. * The type of error (UE/CE) will depend on the inject.eccmask value:
  648. * Any bits set to a 1 will flip the corresponding ECC bit
  649. * Correctable errors can be injected by flipping 1 bit or the bits within
  650. * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
  651. * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
  652. * uncorrectable error to be injected.
  653. */
  654. #define DECLARE_ADDR_MATCH(param, limit) \
  655. static ssize_t i7core_inject_store_##param( \
  656. struct device *dev, \
  657. struct device_attribute *mattr, \
  658. const char *data, size_t count) \
  659. { \
  660. struct mem_ctl_info *mci = dev_get_drvdata(dev); \
  661. struct i7core_pvt *pvt; \
  662. long value; \
  663. int rc; \
  664. \
  665. edac_dbg(1, "\n"); \
  666. pvt = mci->pvt_info; \
  667. \
  668. if (pvt->inject.enable) \
  669. disable_inject(mci); \
  670. \
  671. if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
  672. value = -1; \
  673. else { \
  674. rc = kstrtoul(data, 10, &value); \
  675. if ((rc < 0) || (value >= limit)) \
  676. return -EIO; \
  677. } \
  678. \
  679. pvt->inject.param = value; \
  680. \
  681. return count; \
  682. } \
  683. \
  684. static ssize_t i7core_inject_show_##param( \
  685. struct device *dev, \
  686. struct device_attribute *mattr, \
  687. char *data) \
  688. { \
  689. struct mem_ctl_info *mci = dev_get_drvdata(dev); \
  690. struct i7core_pvt *pvt; \
  691. \
  692. pvt = mci->pvt_info; \
  693. edac_dbg(1, "pvt=%p\n", pvt); \
  694. if (pvt->inject.param < 0) \
  695. return sprintf(data, "any\n"); \
  696. else \
  697. return sprintf(data, "%d\n", pvt->inject.param);\
  698. }
  699. #define ATTR_ADDR_MATCH(param) \
  700. static DEVICE_ATTR(param, S_IRUGO | S_IWUSR, \
  701. i7core_inject_show_##param, \
  702. i7core_inject_store_##param)
  703. DECLARE_ADDR_MATCH(channel, 3);
  704. DECLARE_ADDR_MATCH(dimm, 3);
  705. DECLARE_ADDR_MATCH(rank, 4);
  706. DECLARE_ADDR_MATCH(bank, 32);
  707. DECLARE_ADDR_MATCH(page, 0x10000);
  708. DECLARE_ADDR_MATCH(col, 0x4000);
  709. ATTR_ADDR_MATCH(channel);
  710. ATTR_ADDR_MATCH(dimm);
  711. ATTR_ADDR_MATCH(rank);
  712. ATTR_ADDR_MATCH(bank);
  713. ATTR_ADDR_MATCH(page);
  714. ATTR_ADDR_MATCH(col);
  715. static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
  716. {
  717. u32 read;
  718. int count;
  719. edac_dbg(0, "setting pci %02x:%02x.%x reg=%02x value=%08x\n",
  720. dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
  721. where, val);
  722. for (count = 0; count < 10; count++) {
  723. if (count)
  724. msleep(100);
  725. pci_write_config_dword(dev, where, val);
  726. pci_read_config_dword(dev, where, &read);
  727. if (read == val)
  728. return 0;
  729. }
  730. i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
  731. "write=%08x. Read=%08x\n",
  732. dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
  733. where, val, read);
  734. return -EINVAL;
  735. }
  736. /*
  737. * This routine prepares the Memory Controller for error injection.
  738. * The error will be injected when some process tries to write to the
  739. * memory that matches the given criteria.
  740. * The criteria can be set in terms of a mask where dimm, rank, bank, page
  741. * and col can be specified.
  742. * A -1 value for any of the mask items will make the MCU to ignore
  743. * that matching criteria for error injection.
  744. *
  745. * It should be noticed that the error will only happen after a write operation
  746. * on a memory that matches the condition. if REPEAT_EN is not enabled at
  747. * inject mask, then it will produce just one error. Otherwise, it will repeat
  748. * until the injectmask would be cleaned.
  749. *
  750. * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
  751. * is reliable enough to check if the MC is using the
  752. * three channels. However, this is not clear at the datasheet.
  753. */
  754. static ssize_t i7core_inject_enable_store(struct device *dev,
  755. struct device_attribute *mattr,
  756. const char *data, size_t count)
  757. {
  758. struct mem_ctl_info *mci = to_mci(dev);
  759. struct i7core_pvt *pvt = mci->pvt_info;
  760. u32 injectmask;
  761. u64 mask = 0;
  762. int rc;
  763. long enable;
  764. if (!pvt->pci_ch[pvt->inject.channel][0])
  765. return 0;
  766. rc = kstrtoul(data, 10, &enable);
  767. if ((rc < 0))
  768. return 0;
  769. if (enable) {
  770. pvt->inject.enable = 1;
  771. } else {
  772. disable_inject(mci);
  773. return count;
  774. }
  775. /* Sets pvt->inject.dimm mask */
  776. if (pvt->inject.dimm < 0)
  777. mask |= 1LL << 41;
  778. else {
  779. if (pvt->channel[pvt->inject.channel].dimms > 2)
  780. mask |= (pvt->inject.dimm & 0x3LL) << 35;
  781. else
  782. mask |= (pvt->inject.dimm & 0x1LL) << 36;
  783. }
  784. /* Sets pvt->inject.rank mask */
  785. if (pvt->inject.rank < 0)
  786. mask |= 1LL << 40;
  787. else {
  788. if (pvt->channel[pvt->inject.channel].dimms > 2)
  789. mask |= (pvt->inject.rank & 0x1LL) << 34;
  790. else
  791. mask |= (pvt->inject.rank & 0x3LL) << 34;
  792. }
  793. /* Sets pvt->inject.bank mask */
  794. if (pvt->inject.bank < 0)
  795. mask |= 1LL << 39;
  796. else
  797. mask |= (pvt->inject.bank & 0x15LL) << 30;
  798. /* Sets pvt->inject.page mask */
  799. if (pvt->inject.page < 0)
  800. mask |= 1LL << 38;
  801. else
  802. mask |= (pvt->inject.page & 0xffff) << 14;
  803. /* Sets pvt->inject.column mask */
  804. if (pvt->inject.col < 0)
  805. mask |= 1LL << 37;
  806. else
  807. mask |= (pvt->inject.col & 0x3fff);
  808. /*
  809. * bit 0: REPEAT_EN
  810. * bits 1-2: MASK_HALF_CACHELINE
  811. * bit 3: INJECT_ECC
  812. * bit 4: INJECT_ADDR_PARITY
  813. */
  814. injectmask = (pvt->inject.type & 1) |
  815. (pvt->inject.section & 0x3) << 1 |
  816. (pvt->inject.type & 0x6) << (3 - 1);
  817. /* Unlock writes to registers - this register is write only */
  818. pci_write_config_dword(pvt->pci_noncore,
  819. MC_CFG_CONTROL, 0x2);
  820. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  821. MC_CHANNEL_ADDR_MATCH, mask);
  822. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  823. MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
  824. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  825. MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
  826. write_and_test(pvt->pci_ch[pvt->inject.channel][0],
  827. MC_CHANNEL_ERROR_INJECT, injectmask);
  828. /*
  829. * This is something undocumented, based on my tests
  830. * Without writing 8 to this register, errors aren't injected. Not sure
  831. * why.
  832. */
  833. pci_write_config_dword(pvt->pci_noncore,
  834. MC_CFG_CONTROL, 8);
  835. edac_dbg(0, "Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
  836. mask, pvt->inject.eccmask, injectmask);
  837. return count;
  838. }
  839. static ssize_t i7core_inject_enable_show(struct device *dev,
  840. struct device_attribute *mattr,
  841. char *data)
  842. {
  843. struct mem_ctl_info *mci = to_mci(dev);
  844. struct i7core_pvt *pvt = mci->pvt_info;
  845. u32 injectmask;
  846. if (!pvt->pci_ch[pvt->inject.channel][0])
  847. return 0;
  848. pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
  849. MC_CHANNEL_ERROR_INJECT, &injectmask);
  850. edac_dbg(0, "Inject error read: 0x%018x\n", injectmask);
  851. if (injectmask & 0x0c)
  852. pvt->inject.enable = 1;
  853. return sprintf(data, "%d\n", pvt->inject.enable);
  854. }
  855. #define DECLARE_COUNTER(param) \
  856. static ssize_t i7core_show_counter_##param( \
  857. struct device *dev, \
  858. struct device_attribute *mattr, \
  859. char *data) \
  860. { \
  861. struct mem_ctl_info *mci = dev_get_drvdata(dev); \
  862. struct i7core_pvt *pvt = mci->pvt_info; \
  863. \
  864. edac_dbg(1, "\n"); \
  865. if (!pvt->ce_count_available || (pvt->is_registered)) \
  866. return sprintf(data, "data unavailable\n"); \
  867. return sprintf(data, "%lu\n", \
  868. pvt->udimm_ce_count[param]); \
  869. }
  870. #define ATTR_COUNTER(param) \
  871. static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR, \
  872. i7core_show_counter_##param, \
  873. NULL)
  874. DECLARE_COUNTER(0);
  875. DECLARE_COUNTER(1);
  876. DECLARE_COUNTER(2);
  877. ATTR_COUNTER(0);
  878. ATTR_COUNTER(1);
  879. ATTR_COUNTER(2);
  880. /*
  881. * inject_addrmatch device sysfs struct
  882. */
  883. static struct attribute *i7core_addrmatch_attrs[] = {
  884. &dev_attr_channel.attr,
  885. &dev_attr_dimm.attr,
  886. &dev_attr_rank.attr,
  887. &dev_attr_bank.attr,
  888. &dev_attr_page.attr,
  889. &dev_attr_col.attr,
  890. NULL
  891. };
  892. static const struct attribute_group addrmatch_grp = {
  893. .attrs = i7core_addrmatch_attrs,
  894. };
  895. static const struct attribute_group *addrmatch_groups[] = {
  896. &addrmatch_grp,
  897. NULL
  898. };
  899. static void addrmatch_release(struct device *device)
  900. {
  901. edac_dbg(1, "Releasing device %s\n", dev_name(device));
  902. kfree(device);
  903. }
  904. static const struct device_type addrmatch_type = {
  905. .groups = addrmatch_groups,
  906. .release = addrmatch_release,
  907. };
  908. /*
  909. * all_channel_counts sysfs struct
  910. */
  911. static struct attribute *i7core_udimm_counters_attrs[] = {
  912. &dev_attr_udimm0.attr,
  913. &dev_attr_udimm1.attr,
  914. &dev_attr_udimm2.attr,
  915. NULL
  916. };
  917. static const struct attribute_group all_channel_counts_grp = {
  918. .attrs = i7core_udimm_counters_attrs,
  919. };
  920. static const struct attribute_group *all_channel_counts_groups[] = {
  921. &all_channel_counts_grp,
  922. NULL
  923. };
  924. static void all_channel_counts_release(struct device *device)
  925. {
  926. edac_dbg(1, "Releasing device %s\n", dev_name(device));
  927. kfree(device);
  928. }
  929. static const struct device_type all_channel_counts_type = {
  930. .groups = all_channel_counts_groups,
  931. .release = all_channel_counts_release,
  932. };
  933. /*
  934. * inject sysfs attributes
  935. */
  936. static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
  937. i7core_inject_section_show, i7core_inject_section_store);
  938. static DEVICE_ATTR(inject_type, S_IRUGO | S_IWUSR,
  939. i7core_inject_type_show, i7core_inject_type_store);
  940. static DEVICE_ATTR(inject_eccmask, S_IRUGO | S_IWUSR,
  941. i7core_inject_eccmask_show, i7core_inject_eccmask_store);
  942. static DEVICE_ATTR(inject_enable, S_IRUGO | S_IWUSR,
  943. i7core_inject_enable_show, i7core_inject_enable_store);
  944. static struct attribute *i7core_dev_attrs[] = {
  945. &dev_attr_inject_section.attr,
  946. &dev_attr_inject_type.attr,
  947. &dev_attr_inject_eccmask.attr,
  948. &dev_attr_inject_enable.attr,
  949. NULL
  950. };
  951. ATTRIBUTE_GROUPS(i7core_dev);
  952. static int i7core_create_sysfs_devices(struct mem_ctl_info *mci)
  953. {
  954. struct i7core_pvt *pvt = mci->pvt_info;
  955. int rc;
  956. pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL);
  957. if (!pvt->addrmatch_dev)
  958. return -ENOMEM;
  959. pvt->addrmatch_dev->type = &addrmatch_type;
  960. pvt->addrmatch_dev->bus = mci->dev.bus;
  961. device_initialize(pvt->addrmatch_dev);
  962. pvt->addrmatch_dev->parent = &mci->dev;
  963. dev_set_name(pvt->addrmatch_dev, "inject_addrmatch");
  964. dev_set_drvdata(pvt->addrmatch_dev, mci);
  965. edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev));
  966. rc = device_add(pvt->addrmatch_dev);
  967. if (rc < 0)
  968. goto err_put_addrmatch;
  969. if (!pvt->is_registered) {
  970. pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev),
  971. GFP_KERNEL);
  972. if (!pvt->chancounts_dev) {
  973. rc = -ENOMEM;
  974. goto err_del_addrmatch;
  975. }
  976. pvt->chancounts_dev->type = &all_channel_counts_type;
  977. pvt->chancounts_dev->bus = mci->dev.bus;
  978. device_initialize(pvt->chancounts_dev);
  979. pvt->chancounts_dev->parent = &mci->dev;
  980. dev_set_name(pvt->chancounts_dev, "all_channel_counts");
  981. dev_set_drvdata(pvt->chancounts_dev, mci);
  982. edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev));
  983. rc = device_add(pvt->chancounts_dev);
  984. if (rc < 0)
  985. goto err_put_chancounts;
  986. }
  987. return 0;
  988. err_put_chancounts:
  989. put_device(pvt->chancounts_dev);
  990. err_del_addrmatch:
  991. device_del(pvt->addrmatch_dev);
  992. err_put_addrmatch:
  993. put_device(pvt->addrmatch_dev);
  994. return rc;
  995. }
  996. static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci)
  997. {
  998. struct i7core_pvt *pvt = mci->pvt_info;
  999. edac_dbg(1, "\n");
  1000. if (!pvt->is_registered) {
  1001. device_del(pvt->chancounts_dev);
  1002. put_device(pvt->chancounts_dev);
  1003. }
  1004. device_del(pvt->addrmatch_dev);
  1005. put_device(pvt->addrmatch_dev);
  1006. }
  1007. /****************************************************************************
  1008. Device initialization routines: put/get, init/exit
  1009. ****************************************************************************/
  1010. /*
  1011. * i7core_put_all_devices 'put' all the devices that we have
  1012. * reserved via 'get'
  1013. */
  1014. static void i7core_put_devices(struct i7core_dev *i7core_dev)
  1015. {
  1016. int i;
  1017. edac_dbg(0, "\n");
  1018. for (i = 0; i < i7core_dev->n_devs; i++) {
  1019. struct pci_dev *pdev = i7core_dev->pdev[i];
  1020. if (!pdev)
  1021. continue;
  1022. edac_dbg(0, "Removing dev %02x:%02x.%d\n",
  1023. pdev->bus->number,
  1024. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
  1025. pci_dev_put(pdev);
  1026. }
  1027. }
  1028. static void i7core_put_all_devices(void)
  1029. {
  1030. struct i7core_dev *i7core_dev, *tmp;
  1031. list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
  1032. i7core_put_devices(i7core_dev);
  1033. free_i7core_dev(i7core_dev);
  1034. }
  1035. }
  1036. static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
  1037. {
  1038. struct pci_dev *pdev = NULL;
  1039. int i;
  1040. /*
  1041. * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
  1042. * aren't announced by acpi. So, we need to use a legacy scan probing
  1043. * to detect them
  1044. */
  1045. while (table && table->descr) {
  1046. pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
  1047. if (unlikely(!pdev)) {
  1048. for (i = 0; i < MAX_SOCKET_BUSES; i++)
  1049. pcibios_scan_specific_bus(255-i);
  1050. }
  1051. pci_dev_put(pdev);
  1052. table++;
  1053. }
  1054. }
  1055. static unsigned i7core_pci_lastbus(void)
  1056. {
  1057. int last_bus = 0, bus;
  1058. struct pci_bus *b = NULL;
  1059. while ((b = pci_find_next_bus(b)) != NULL) {
  1060. bus = b->number;
  1061. edac_dbg(0, "Found bus %d\n", bus);
  1062. if (bus > last_bus)
  1063. last_bus = bus;
  1064. }
  1065. edac_dbg(0, "Last bus %d\n", last_bus);
  1066. return last_bus;
  1067. }
  1068. /*
  1069. * i7core_get_all_devices Find and perform 'get' operation on the MCH's
  1070. * device/functions we want to reference for this driver
  1071. *
  1072. * Need to 'get' device 16 func 1 and func 2
  1073. */
  1074. static int i7core_get_onedevice(struct pci_dev **prev,
  1075. const struct pci_id_table *table,
  1076. const unsigned devno,
  1077. const unsigned last_bus)
  1078. {
  1079. struct i7core_dev *i7core_dev;
  1080. const struct pci_id_descr *dev_descr = &table->descr[devno];
  1081. struct pci_dev *pdev = NULL;
  1082. u8 bus = 0;
  1083. u8 socket = 0;
  1084. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  1085. dev_descr->dev_id, *prev);
  1086. /*
  1087. * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs
  1088. * is at addr 8086:2c40, instead of 8086:2c41. So, we need
  1089. * to probe for the alternate address in case of failure
  1090. */
  1091. if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev) {
  1092. pci_dev_get(*prev); /* pci_get_device will put it */
  1093. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  1094. PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
  1095. }
  1096. if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE &&
  1097. !pdev) {
  1098. pci_dev_get(*prev); /* pci_get_device will put it */
  1099. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  1100. PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
  1101. *prev);
  1102. }
  1103. if (!pdev) {
  1104. if (*prev) {
  1105. *prev = pdev;
  1106. return 0;
  1107. }
  1108. if (dev_descr->optional)
  1109. return 0;
  1110. if (devno == 0)
  1111. return -ENODEV;
  1112. i7core_printk(KERN_INFO,
  1113. "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
  1114. dev_descr->dev, dev_descr->func,
  1115. PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
  1116. /* End of list, leave */
  1117. return -ENODEV;
  1118. }
  1119. bus = pdev->bus->number;
  1120. socket = last_bus - bus;
  1121. i7core_dev = get_i7core_dev(socket);
  1122. if (!i7core_dev) {
  1123. i7core_dev = alloc_i7core_dev(socket, table);
  1124. if (!i7core_dev) {
  1125. pci_dev_put(pdev);
  1126. return -ENOMEM;
  1127. }
  1128. }
  1129. if (i7core_dev->pdev[devno]) {
  1130. i7core_printk(KERN_ERR,
  1131. "Duplicated device for "
  1132. "dev %02x:%02x.%d PCI ID %04x:%04x\n",
  1133. bus, dev_descr->dev, dev_descr->func,
  1134. PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
  1135. pci_dev_put(pdev);
  1136. return -ENODEV;
  1137. }
  1138. i7core_dev->pdev[devno] = pdev;
  1139. /* Sanity check */
  1140. if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
  1141. PCI_FUNC(pdev->devfn) != dev_descr->func)) {
  1142. i7core_printk(KERN_ERR,
  1143. "Device PCI ID %04x:%04x "
  1144. "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
  1145. PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
  1146. bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
  1147. bus, dev_descr->dev, dev_descr->func);
  1148. return -ENODEV;
  1149. }
  1150. /* Be sure that the device is enabled */
  1151. if (unlikely(pci_enable_device(pdev) < 0)) {
  1152. i7core_printk(KERN_ERR,
  1153. "Couldn't enable "
  1154. "dev %02x:%02x.%d PCI ID %04x:%04x\n",
  1155. bus, dev_descr->dev, dev_descr->func,
  1156. PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
  1157. return -ENODEV;
  1158. }
  1159. edac_dbg(0, "Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
  1160. socket, bus, dev_descr->dev,
  1161. dev_descr->func,
  1162. PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
  1163. /*
  1164. * As stated on drivers/pci/search.c, the reference count for
  1165. * @from is always decremented if it is not %NULL. So, as we need
  1166. * to get all devices up to null, we need to do a get for the device
  1167. */
  1168. pci_dev_get(pdev);
  1169. *prev = pdev;
  1170. return 0;
  1171. }
  1172. static int i7core_get_all_devices(void)
  1173. {
  1174. int i, rc, last_bus;
  1175. struct pci_dev *pdev = NULL;
  1176. const struct pci_id_table *table = pci_dev_table;
  1177. last_bus = i7core_pci_lastbus();
  1178. while (table && table->descr) {
  1179. for (i = 0; i < table->n_devs; i++) {
  1180. pdev = NULL;
  1181. do {
  1182. rc = i7core_get_onedevice(&pdev, table, i,
  1183. last_bus);
  1184. if (rc < 0) {
  1185. if (i == 0) {
  1186. i = table->n_devs;
  1187. break;
  1188. }
  1189. i7core_put_all_devices();
  1190. return -ENODEV;
  1191. }
  1192. } while (pdev);
  1193. }
  1194. table++;
  1195. }
  1196. return 0;
  1197. }
  1198. static int mci_bind_devs(struct mem_ctl_info *mci,
  1199. struct i7core_dev *i7core_dev)
  1200. {
  1201. struct i7core_pvt *pvt = mci->pvt_info;
  1202. struct pci_dev *pdev;
  1203. int i, func, slot;
  1204. char *family;
  1205. pvt->is_registered = false;
  1206. pvt->enable_scrub = false;
  1207. for (i = 0; i < i7core_dev->n_devs; i++) {
  1208. pdev = i7core_dev->pdev[i];
  1209. if (!pdev)
  1210. continue;
  1211. func = PCI_FUNC(pdev->devfn);
  1212. slot = PCI_SLOT(pdev->devfn);
  1213. if (slot == 3) {
  1214. if (unlikely(func > MAX_MCR_FUNC))
  1215. goto error;
  1216. pvt->pci_mcr[func] = pdev;
  1217. } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
  1218. if (unlikely(func > MAX_CHAN_FUNC))
  1219. goto error;
  1220. pvt->pci_ch[slot - 4][func] = pdev;
  1221. } else if (!slot && !func) {
  1222. pvt->pci_noncore = pdev;
  1223. /* Detect the processor family */
  1224. switch (pdev->device) {
  1225. case PCI_DEVICE_ID_INTEL_I7_NONCORE:
  1226. family = "Xeon 35xx/ i7core";
  1227. pvt->enable_scrub = false;
  1228. break;
  1229. case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
  1230. family = "i7-800/i5-700";
  1231. pvt->enable_scrub = false;
  1232. break;
  1233. case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
  1234. family = "Xeon 34xx";
  1235. pvt->enable_scrub = false;
  1236. break;
  1237. case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
  1238. family = "Xeon 55xx";
  1239. pvt->enable_scrub = true;
  1240. break;
  1241. case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
  1242. family = "Xeon 56xx / i7-900";
  1243. pvt->enable_scrub = true;
  1244. break;
  1245. default:
  1246. family = "unknown";
  1247. pvt->enable_scrub = false;
  1248. }
  1249. edac_dbg(0, "Detected a processor type %s\n", family);
  1250. } else
  1251. goto error;
  1252. edac_dbg(0, "Associated fn %d.%d, dev = %p, socket %d\n",
  1253. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
  1254. pdev, i7core_dev->socket);
  1255. if (PCI_SLOT(pdev->devfn) == 3 &&
  1256. PCI_FUNC(pdev->devfn) == 2)
  1257. pvt->is_registered = true;
  1258. }
  1259. return 0;
  1260. error:
  1261. i7core_printk(KERN_ERR, "Device %d, function %d "
  1262. "is out of the expected range\n",
  1263. slot, func);
  1264. return -EINVAL;
  1265. }
  1266. /****************************************************************************
  1267. Error check routines
  1268. ****************************************************************************/
  1269. static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
  1270. const int chan,
  1271. const int new0,
  1272. const int new1,
  1273. const int new2)
  1274. {
  1275. struct i7core_pvt *pvt = mci->pvt_info;
  1276. int add0 = 0, add1 = 0, add2 = 0;
  1277. /* Updates CE counters if it is not the first time here */
  1278. if (pvt->ce_count_available) {
  1279. /* Updates CE counters */
  1280. add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
  1281. add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
  1282. add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
  1283. if (add2 < 0)
  1284. add2 += 0x7fff;
  1285. pvt->rdimm_ce_count[chan][2] += add2;
  1286. if (add1 < 0)
  1287. add1 += 0x7fff;
  1288. pvt->rdimm_ce_count[chan][1] += add1;
  1289. if (add0 < 0)
  1290. add0 += 0x7fff;
  1291. pvt->rdimm_ce_count[chan][0] += add0;
  1292. } else
  1293. pvt->ce_count_available = 1;
  1294. /* Store the new values */
  1295. pvt->rdimm_last_ce_count[chan][2] = new2;
  1296. pvt->rdimm_last_ce_count[chan][1] = new1;
  1297. pvt->rdimm_last_ce_count[chan][0] = new0;
  1298. /*updated the edac core */
  1299. if (add0 != 0)
  1300. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add0,
  1301. 0, 0, 0,
  1302. chan, 0, -1, "error", "");
  1303. if (add1 != 0)
  1304. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add1,
  1305. 0, 0, 0,
  1306. chan, 1, -1, "error", "");
  1307. if (add2 != 0)
  1308. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add2,
  1309. 0, 0, 0,
  1310. chan, 2, -1, "error", "");
  1311. }
  1312. static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
  1313. {
  1314. struct i7core_pvt *pvt = mci->pvt_info;
  1315. u32 rcv[3][2];
  1316. int i, new0, new1, new2;
  1317. /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
  1318. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
  1319. &rcv[0][0]);
  1320. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
  1321. &rcv[0][1]);
  1322. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
  1323. &rcv[1][0]);
  1324. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
  1325. &rcv[1][1]);
  1326. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
  1327. &rcv[2][0]);
  1328. pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
  1329. &rcv[2][1]);
  1330. for (i = 0 ; i < 3; i++) {
  1331. edac_dbg(3, "MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
  1332. (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
  1333. /*if the channel has 3 dimms*/
  1334. if (pvt->channel[i].dimms > 2) {
  1335. new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
  1336. new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
  1337. new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
  1338. } else {
  1339. new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
  1340. DIMM_BOT_COR_ERR(rcv[i][0]);
  1341. new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
  1342. DIMM_BOT_COR_ERR(rcv[i][1]);
  1343. new2 = 0;
  1344. }
  1345. i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
  1346. }
  1347. }
  1348. /* This function is based on the device 3 function 4 registers as described on:
  1349. * Intel Xeon Processor 5500 Series Datasheet Volume 2
  1350. * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
  1351. * also available at:
  1352. * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
  1353. */
  1354. static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
  1355. {
  1356. struct i7core_pvt *pvt = mci->pvt_info;
  1357. u32 rcv1, rcv0;
  1358. int new0, new1, new2;
  1359. if (!pvt->pci_mcr[4]) {
  1360. edac_dbg(0, "MCR registers not found\n");
  1361. return;
  1362. }
  1363. /* Corrected test errors */
  1364. pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
  1365. pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
  1366. /* Store the new values */
  1367. new2 = DIMM2_COR_ERR(rcv1);
  1368. new1 = DIMM1_COR_ERR(rcv0);
  1369. new0 = DIMM0_COR_ERR(rcv0);
  1370. /* Updates CE counters if it is not the first time here */
  1371. if (pvt->ce_count_available) {
  1372. /* Updates CE counters */
  1373. int add0, add1, add2;
  1374. add2 = new2 - pvt->udimm_last_ce_count[2];
  1375. add1 = new1 - pvt->udimm_last_ce_count[1];
  1376. add0 = new0 - pvt->udimm_last_ce_count[0];
  1377. if (add2 < 0)
  1378. add2 += 0x7fff;
  1379. pvt->udimm_ce_count[2] += add2;
  1380. if (add1 < 0)
  1381. add1 += 0x7fff;
  1382. pvt->udimm_ce_count[1] += add1;
  1383. if (add0 < 0)
  1384. add0 += 0x7fff;
  1385. pvt->udimm_ce_count[0] += add0;
  1386. if (add0 | add1 | add2)
  1387. i7core_printk(KERN_ERR, "New Corrected error(s): "
  1388. "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
  1389. add0, add1, add2);
  1390. } else
  1391. pvt->ce_count_available = 1;
  1392. /* Store the new values */
  1393. pvt->udimm_last_ce_count[2] = new2;
  1394. pvt->udimm_last_ce_count[1] = new1;
  1395. pvt->udimm_last_ce_count[0] = new0;
  1396. }
  1397. /*
  1398. * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
  1399. * Architectures Software Developer’s Manual Volume 3B.
  1400. * Nehalem are defined as family 0x06, model 0x1a
  1401. *
  1402. * The MCA registers used here are the following ones:
  1403. * struct mce field MCA Register
  1404. * m->status MSR_IA32_MC8_STATUS
  1405. * m->addr MSR_IA32_MC8_ADDR
  1406. * m->misc MSR_IA32_MC8_MISC
  1407. * In the case of Nehalem, the error information is masked at .status and .misc
  1408. * fields
  1409. */
  1410. static void i7core_mce_output_error(struct mem_ctl_info *mci,
  1411. const struct mce *m)
  1412. {
  1413. struct i7core_pvt *pvt = mci->pvt_info;
  1414. char *optype, *err;
  1415. enum hw_event_mc_err_type tp_event;
  1416. unsigned long error = m->status & 0x1ff0000l;
  1417. bool uncorrected_error = m->mcgstatus & 1ll << 61;
  1418. bool ripv = m->mcgstatus & 1;
  1419. u32 optypenum = (m->status >> 4) & 0x07;
  1420. u32 core_err_cnt = (m->status >> 38) & 0x7fff;
  1421. u32 dimm = (m->misc >> 16) & 0x3;
  1422. u32 channel = (m->misc >> 18) & 0x3;
  1423. u32 syndrome = m->misc >> 32;
  1424. u32 errnum = find_first_bit(&error, 32);
  1425. if (uncorrected_error) {
  1426. core_err_cnt = 1;
  1427. if (ripv)
  1428. tp_event = HW_EVENT_ERR_UNCORRECTED;
  1429. else
  1430. tp_event = HW_EVENT_ERR_FATAL;
  1431. } else {
  1432. tp_event = HW_EVENT_ERR_CORRECTED;
  1433. }
  1434. switch (optypenum) {
  1435. case 0:
  1436. optype = "generic undef request";
  1437. break;
  1438. case 1:
  1439. optype = "read error";
  1440. break;
  1441. case 2:
  1442. optype = "write error";
  1443. break;
  1444. case 3:
  1445. optype = "addr/cmd error";
  1446. break;
  1447. case 4:
  1448. optype = "scrubbing error";
  1449. break;
  1450. default:
  1451. optype = "reserved";
  1452. break;
  1453. }
  1454. switch (errnum) {
  1455. case 16:
  1456. err = "read ECC error";
  1457. break;
  1458. case 17:
  1459. err = "RAS ECC error";
  1460. break;
  1461. case 18:
  1462. err = "write parity error";
  1463. break;
  1464. case 19:
  1465. err = "redundancy loss";
  1466. break;
  1467. case 20:
  1468. err = "reserved";
  1469. break;
  1470. case 21:
  1471. err = "memory range error";
  1472. break;
  1473. case 22:
  1474. err = "RTID out of range";
  1475. break;
  1476. case 23:
  1477. err = "address parity error";
  1478. break;
  1479. case 24:
  1480. err = "byte enable parity error";
  1481. break;
  1482. default:
  1483. err = "unknown";
  1484. }
  1485. /*
  1486. * Call the helper to output message
  1487. * FIXME: what to do if core_err_cnt > 1? Currently, it generates
  1488. * only one event
  1489. */
  1490. if (uncorrected_error || !pvt->is_registered)
  1491. edac_mc_handle_error(tp_event, mci, core_err_cnt,
  1492. m->addr >> PAGE_SHIFT,
  1493. m->addr & ~PAGE_MASK,
  1494. syndrome,
  1495. channel, dimm, -1,
  1496. err, optype);
  1497. }
  1498. /*
  1499. * i7core_check_error Retrieve and process errors reported by the
  1500. * hardware. Called by the Core module.
  1501. */
  1502. static void i7core_check_error(struct mem_ctl_info *mci, struct mce *m)
  1503. {
  1504. struct i7core_pvt *pvt = mci->pvt_info;
  1505. i7core_mce_output_error(mci, m);
  1506. /*
  1507. * Now, let's increment CE error counts
  1508. */
  1509. if (!pvt->is_registered)
  1510. i7core_udimm_check_mc_ecc_err(mci);
  1511. else
  1512. i7core_rdimm_check_mc_ecc_err(mci);
  1513. }
  1514. /*
  1515. * Check that logging is enabled and that this is the right type
  1516. * of error for us to handle.
  1517. */
  1518. static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
  1519. void *data)
  1520. {
  1521. struct mce *mce = (struct mce *)data;
  1522. struct i7core_dev *i7_dev;
  1523. struct mem_ctl_info *mci;
  1524. i7_dev = get_i7core_dev(mce->socketid);
  1525. if (!i7_dev || (mce->kflags & MCE_HANDLED_CEC))
  1526. return NOTIFY_DONE;
  1527. mci = i7_dev->mci;
  1528. /*
  1529. * Just let mcelog handle it if the error is
  1530. * outside the memory controller
  1531. */
  1532. if (((mce->status & 0xffff) >> 7) != 1)
  1533. return NOTIFY_DONE;
  1534. /* Bank 8 registers are the only ones that we know how to handle */
  1535. if (mce->bank != 8)
  1536. return NOTIFY_DONE;
  1537. i7core_check_error(mci, mce);
  1538. /* Advise mcelog that the errors were handled */
  1539. mce->kflags |= MCE_HANDLED_EDAC;
  1540. return NOTIFY_OK;
  1541. }
  1542. static struct notifier_block i7_mce_dec = {
  1543. .notifier_call = i7core_mce_check_error,
  1544. .priority = MCE_PRIO_EDAC,
  1545. };
  1546. struct memdev_dmi_entry {
  1547. u8 type;
  1548. u8 length;
  1549. u16 handle;
  1550. u16 phys_mem_array_handle;
  1551. u16 mem_err_info_handle;
  1552. u16 total_width;
  1553. u16 data_width;
  1554. u16 size;
  1555. u8 form;
  1556. u8 device_set;
  1557. u8 device_locator;
  1558. u8 bank_locator;
  1559. u8 memory_type;
  1560. u16 type_detail;
  1561. u16 speed;
  1562. u8 manufacturer;
  1563. u8 serial_number;
  1564. u8 asset_tag;
  1565. u8 part_number;
  1566. u8 attributes;
  1567. u32 extended_size;
  1568. u16 conf_mem_clk_speed;
  1569. } __attribute__((__packed__));
  1570. /*
  1571. * Decode the DRAM Clock Frequency, be paranoid, make sure that all
  1572. * memory devices show the same speed, and if they don't then consider
  1573. * all speeds to be invalid.
  1574. */
  1575. static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
  1576. {
  1577. int *dclk_freq = _dclk_freq;
  1578. u16 dmi_mem_clk_speed;
  1579. if (*dclk_freq == -1)
  1580. return;
  1581. if (dh->type == DMI_ENTRY_MEM_DEVICE) {
  1582. struct memdev_dmi_entry *memdev_dmi_entry =
  1583. (struct memdev_dmi_entry *)dh;
  1584. unsigned long conf_mem_clk_speed_offset =
  1585. (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
  1586. (unsigned long)&memdev_dmi_entry->type;
  1587. unsigned long speed_offset =
  1588. (unsigned long)&memdev_dmi_entry->speed -
  1589. (unsigned long)&memdev_dmi_entry->type;
  1590. /* Check that a DIMM is present */
  1591. if (memdev_dmi_entry->size == 0)
  1592. return;
  1593. /*
  1594. * Pick the configured speed if it's available, otherwise
  1595. * pick the DIMM speed, or we don't have a speed.
  1596. */
  1597. if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
  1598. dmi_mem_clk_speed =
  1599. memdev_dmi_entry->conf_mem_clk_speed;
  1600. } else if (memdev_dmi_entry->length > speed_offset) {
  1601. dmi_mem_clk_speed = memdev_dmi_entry->speed;
  1602. } else {
  1603. *dclk_freq = -1;
  1604. return;
  1605. }
  1606. if (*dclk_freq == 0) {
  1607. /* First pass, speed was 0 */
  1608. if (dmi_mem_clk_speed > 0) {
  1609. /* Set speed if a valid speed is read */
  1610. *dclk_freq = dmi_mem_clk_speed;
  1611. } else {
  1612. /* Otherwise we don't have a valid speed */
  1613. *dclk_freq = -1;
  1614. }
  1615. } else if (*dclk_freq > 0 &&
  1616. *dclk_freq != dmi_mem_clk_speed) {
  1617. /*
  1618. * If we have a speed, check that all DIMMS are the same
  1619. * speed, otherwise set the speed as invalid.
  1620. */
  1621. *dclk_freq = -1;
  1622. }
  1623. }
  1624. }
  1625. /*
  1626. * The default DCLK frequency is used as a fallback if we
  1627. * fail to find anything reliable in the DMI. The value
  1628. * is taken straight from the datasheet.
  1629. */
  1630. #define DEFAULT_DCLK_FREQ 800
  1631. static int get_dclk_freq(void)
  1632. {
  1633. int dclk_freq = 0;
  1634. dmi_walk(decode_dclk, (void *)&dclk_freq);
  1635. if (dclk_freq < 1)
  1636. return DEFAULT_DCLK_FREQ;
  1637. return dclk_freq;
  1638. }
  1639. /*
  1640. * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
  1641. * to hardware according to SCRUBINTERVAL formula
  1642. * found in datasheet.
  1643. */
  1644. static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
  1645. {
  1646. struct i7core_pvt *pvt = mci->pvt_info;
  1647. struct pci_dev *pdev;
  1648. u32 dw_scrub;
  1649. u32 dw_ssr;
  1650. /* Get data from the MC register, function 2 */
  1651. pdev = pvt->pci_mcr[2];
  1652. if (!pdev)
  1653. return -ENODEV;
  1654. pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
  1655. if (new_bw == 0) {
  1656. /* Prepare to disable petrol scrub */
  1657. dw_scrub &= ~STARTSCRUB;
  1658. /* Stop the patrol scrub engine */
  1659. write_and_test(pdev, MC_SCRUB_CONTROL,
  1660. dw_scrub & ~SCRUBINTERVAL_MASK);
  1661. /* Get current status of scrub rate and set bit to disable */
  1662. pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
  1663. dw_ssr &= ~SSR_MODE_MASK;
  1664. dw_ssr |= SSR_MODE_DISABLE;
  1665. } else {
  1666. const int cache_line_size = 64;
  1667. const u32 freq_dclk_mhz = pvt->dclk_freq;
  1668. unsigned long long scrub_interval;
  1669. /*
  1670. * Translate the desired scrub rate to a register value and
  1671. * program the corresponding register value.
  1672. */
  1673. scrub_interval = (unsigned long long)freq_dclk_mhz *
  1674. cache_line_size * 1000000;
  1675. do_div(scrub_interval, new_bw);
  1676. if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
  1677. return -EINVAL;
  1678. dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
  1679. /* Start the patrol scrub engine */
  1680. pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
  1681. STARTSCRUB | dw_scrub);
  1682. /* Get current status of scrub rate and set bit to enable */
  1683. pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
  1684. dw_ssr &= ~SSR_MODE_MASK;
  1685. dw_ssr |= SSR_MODE_ENABLE;
  1686. }
  1687. /* Disable or enable scrubbing */
  1688. pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
  1689. return new_bw;
  1690. }
  1691. /*
  1692. * get_sdram_scrub_rate This routine convert current scrub rate value
  1693. * into byte/sec bandwidth according to
  1694. * SCRUBINTERVAL formula found in datasheet.
  1695. */
  1696. static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
  1697. {
  1698. struct i7core_pvt *pvt = mci->pvt_info;
  1699. struct pci_dev *pdev;
  1700. const u32 cache_line_size = 64;
  1701. const u32 freq_dclk_mhz = pvt->dclk_freq;
  1702. unsigned long long scrub_rate;
  1703. u32 scrubval;
  1704. /* Get data from the MC register, function 2 */
  1705. pdev = pvt->pci_mcr[2];
  1706. if (!pdev)
  1707. return -ENODEV;
  1708. /* Get current scrub control data */
  1709. pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
  1710. /* Mask highest 8-bits to 0 */
  1711. scrubval &= SCRUBINTERVAL_MASK;
  1712. if (!scrubval)
  1713. return 0;
  1714. /* Calculate scrub rate value into byte/sec bandwidth */
  1715. scrub_rate = (unsigned long long)freq_dclk_mhz *
  1716. 1000000 * cache_line_size;
  1717. do_div(scrub_rate, scrubval);
  1718. return (int)scrub_rate;
  1719. }
  1720. static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
  1721. {
  1722. struct i7core_pvt *pvt = mci->pvt_info;
  1723. u32 pci_lock;
  1724. /* Unlock writes to pci registers */
  1725. pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
  1726. pci_lock &= ~0x3;
  1727. pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
  1728. pci_lock | MC_CFG_UNLOCK);
  1729. mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
  1730. mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
  1731. }
  1732. static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
  1733. {
  1734. struct i7core_pvt *pvt = mci->pvt_info;
  1735. u32 pci_lock;
  1736. /* Lock writes to pci registers */
  1737. pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
  1738. pci_lock &= ~0x3;
  1739. pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
  1740. pci_lock | MC_CFG_LOCK);
  1741. }
  1742. static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
  1743. {
  1744. pvt->i7core_pci = edac_pci_create_generic_ctl(
  1745. &pvt->i7core_dev->pdev[0]->dev,
  1746. EDAC_MOD_STR);
  1747. if (unlikely(!pvt->i7core_pci))
  1748. i7core_printk(KERN_WARNING,
  1749. "Unable to setup PCI error report via EDAC\n");
  1750. }
  1751. static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
  1752. {
  1753. if (likely(pvt->i7core_pci))
  1754. edac_pci_release_generic_ctl(pvt->i7core_pci);
  1755. else
  1756. i7core_printk(KERN_ERR,
  1757. "Couldn't find mem_ctl_info for socket %d\n",
  1758. pvt->i7core_dev->socket);
  1759. pvt->i7core_pci = NULL;
  1760. }
  1761. static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
  1762. {
  1763. struct mem_ctl_info *mci = i7core_dev->mci;
  1764. struct i7core_pvt *pvt;
  1765. if (unlikely(!mci || !mci->pvt_info)) {
  1766. edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev);
  1767. i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
  1768. return;
  1769. }
  1770. pvt = mci->pvt_info;
  1771. edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
  1772. /* Disable scrubrate setting */
  1773. if (pvt->enable_scrub)
  1774. disable_sdram_scrub_setting(mci);
  1775. /* Disable EDAC polling */
  1776. i7core_pci_ctl_release(pvt);
  1777. /* Remove MC sysfs nodes */
  1778. i7core_delete_sysfs_devices(mci);
  1779. edac_mc_del_mc(mci->pdev);
  1780. edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
  1781. kfree(mci->ctl_name);
  1782. edac_mc_free(mci);
  1783. i7core_dev->mci = NULL;
  1784. }
  1785. static int i7core_register_mci(struct i7core_dev *i7core_dev)
  1786. {
  1787. struct mem_ctl_info *mci;
  1788. struct i7core_pvt *pvt;
  1789. int rc;
  1790. struct edac_mc_layer layers[2];
  1791. /* allocate a new MC control structure */
  1792. layers[0].type = EDAC_MC_LAYER_CHANNEL;
  1793. layers[0].size = NUM_CHANS;
  1794. layers[0].is_virt_csrow = false;
  1795. layers[1].type = EDAC_MC_LAYER_SLOT;
  1796. layers[1].size = MAX_DIMMS;
  1797. layers[1].is_virt_csrow = true;
  1798. mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
  1799. sizeof(*pvt));
  1800. if (unlikely(!mci))
  1801. return -ENOMEM;
  1802. edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
  1803. pvt = mci->pvt_info;
  1804. memset(pvt, 0, sizeof(*pvt));
  1805. /* Associates i7core_dev and mci for future usage */
  1806. pvt->i7core_dev = i7core_dev;
  1807. i7core_dev->mci = mci;
  1808. /*
  1809. * FIXME: how to handle RDDR3 at MCI level? It is possible to have
  1810. * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
  1811. * memory channels
  1812. */
  1813. mci->mtype_cap = MEM_FLAG_DDR3;
  1814. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  1815. mci->edac_cap = EDAC_FLAG_NONE;
  1816. mci->mod_name = "i7core_edac.c";
  1817. mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d", i7core_dev->socket);
  1818. if (!mci->ctl_name) {
  1819. rc = -ENOMEM;
  1820. goto fail1;
  1821. }
  1822. mci->dev_name = pci_name(i7core_dev->pdev[0]);
  1823. mci->ctl_page_to_phys = NULL;
  1824. /* Store pci devices at mci for faster access */
  1825. rc = mci_bind_devs(mci, i7core_dev);
  1826. if (unlikely(rc < 0))
  1827. goto fail0;
  1828. /* Get dimm basic config */
  1829. get_dimm_config(mci);
  1830. /* record ptr to the generic device */
  1831. mci->pdev = &i7core_dev->pdev[0]->dev;
  1832. /* Enable scrubrate setting */
  1833. if (pvt->enable_scrub)
  1834. enable_sdram_scrub_setting(mci);
  1835. /* add this new MC control structure to EDAC's list of MCs */
  1836. if (unlikely(edac_mc_add_mc_with_groups(mci, i7core_dev_groups))) {
  1837. edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
  1838. /* FIXME: perhaps some code should go here that disables error
  1839. * reporting if we just enabled it
  1840. */
  1841. rc = -EINVAL;
  1842. goto fail0;
  1843. }
  1844. if (i7core_create_sysfs_devices(mci)) {
  1845. edac_dbg(0, "MC: failed to create sysfs nodes\n");
  1846. edac_mc_del_mc(mci->pdev);
  1847. rc = -EINVAL;
  1848. goto fail0;
  1849. }
  1850. /* Default error mask is any memory */
  1851. pvt->inject.channel = 0;
  1852. pvt->inject.dimm = -1;
  1853. pvt->inject.rank = -1;
  1854. pvt->inject.bank = -1;
  1855. pvt->inject.page = -1;
  1856. pvt->inject.col = -1;
  1857. /* allocating generic PCI control info */
  1858. i7core_pci_ctl_create(pvt);
  1859. /* DCLK for scrub rate setting */
  1860. pvt->dclk_freq = get_dclk_freq();
  1861. return 0;
  1862. fail0:
  1863. kfree(mci->ctl_name);
  1864. fail1:
  1865. edac_mc_free(mci);
  1866. i7core_dev->mci = NULL;
  1867. return rc;
  1868. }
  1869. /*
  1870. * i7core_probe Probe for ONE instance of device to see if it is
  1871. * present.
  1872. * return:
  1873. * 0 for FOUND a device
  1874. * < 0 for error code
  1875. */
  1876. static int i7core_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1877. {
  1878. int rc, count = 0;
  1879. struct i7core_dev *i7core_dev;
  1880. /* get the pci devices we want to reserve for our use */
  1881. mutex_lock(&i7core_edac_lock);
  1882. /*
  1883. * All memory controllers are allocated at the first pass.
  1884. */
  1885. if (unlikely(probed >= 1)) {
  1886. mutex_unlock(&i7core_edac_lock);
  1887. return -ENODEV;
  1888. }
  1889. probed++;
  1890. rc = i7core_get_all_devices();
  1891. if (unlikely(rc < 0))
  1892. goto fail0;
  1893. list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
  1894. count++;
  1895. rc = i7core_register_mci(i7core_dev);
  1896. if (unlikely(rc < 0))
  1897. goto fail1;
  1898. }
  1899. /*
  1900. * Nehalem-EX uses a different memory controller. However, as the
  1901. * memory controller is not visible on some Nehalem/Nehalem-EP, we
  1902. * need to indirectly probe via a X58 PCI device. The same devices
  1903. * are found on (some) Nehalem-EX. So, on those machines, the
  1904. * probe routine needs to return -ENODEV, as the actual Memory
  1905. * Controller registers won't be detected.
  1906. */
  1907. if (!count) {
  1908. rc = -ENODEV;
  1909. goto fail1;
  1910. }
  1911. i7core_printk(KERN_INFO,
  1912. "Driver loaded, %d memory controller(s) found.\n",
  1913. count);
  1914. mutex_unlock(&i7core_edac_lock);
  1915. return 0;
  1916. fail1:
  1917. list_for_each_entry(i7core_dev, &i7core_edac_list, list)
  1918. i7core_unregister_mci(i7core_dev);
  1919. i7core_put_all_devices();
  1920. fail0:
  1921. mutex_unlock(&i7core_edac_lock);
  1922. return rc;
  1923. }
  1924. /*
  1925. * i7core_remove destructor for one instance of device
  1926. *
  1927. */
  1928. static void i7core_remove(struct pci_dev *pdev)
  1929. {
  1930. struct i7core_dev *i7core_dev;
  1931. edac_dbg(0, "\n");
  1932. /*
  1933. * we have a trouble here: pdev value for removal will be wrong, since
  1934. * it will point to the X58 register used to detect that the machine
  1935. * is a Nehalem or upper design. However, due to the way several PCI
  1936. * devices are grouped together to provide MC functionality, we need
  1937. * to use a different method for releasing the devices
  1938. */
  1939. mutex_lock(&i7core_edac_lock);
  1940. if (unlikely(!probed)) {
  1941. mutex_unlock(&i7core_edac_lock);
  1942. return;
  1943. }
  1944. list_for_each_entry(i7core_dev, &i7core_edac_list, list)
  1945. i7core_unregister_mci(i7core_dev);
  1946. /* Release PCI resources */
  1947. i7core_put_all_devices();
  1948. probed--;
  1949. mutex_unlock(&i7core_edac_lock);
  1950. }
  1951. MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
  1952. /*
  1953. * i7core_driver pci_driver structure for this module
  1954. *
  1955. */
  1956. static struct pci_driver i7core_driver = {
  1957. .name = "i7core_edac",
  1958. .probe = i7core_probe,
  1959. .remove = i7core_remove,
  1960. .id_table = i7core_pci_tbl,
  1961. };
  1962. /*
  1963. * i7core_init Module entry function
  1964. * Try to initialize this module for its devices
  1965. */
  1966. static int __init i7core_init(void)
  1967. {
  1968. int pci_rc;
  1969. edac_dbg(2, "\n");
  1970. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  1971. opstate_init();
  1972. if (use_pci_fixup)
  1973. i7core_xeon_pci_fixup(pci_dev_table);
  1974. pci_rc = pci_register_driver(&i7core_driver);
  1975. if (pci_rc >= 0) {
  1976. mce_register_decode_chain(&i7_mce_dec);
  1977. return 0;
  1978. }
  1979. i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
  1980. pci_rc);
  1981. return pci_rc;
  1982. }
  1983. /*
  1984. * i7core_exit() Module exit function
  1985. * Unregister the driver
  1986. */
  1987. static void __exit i7core_exit(void)
  1988. {
  1989. edac_dbg(2, "\n");
  1990. pci_unregister_driver(&i7core_driver);
  1991. mce_unregister_decode_chain(&i7_mce_dec);
  1992. }
  1993. module_init(i7core_init);
  1994. module_exit(i7core_exit);
  1995. MODULE_LICENSE("GPL");
  1996. MODULE_AUTHOR("Mauro Carvalho Chehab");
  1997. MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)");
  1998. MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
  1999. I7CORE_REVISION);
  2000. module_param(edac_op_state, int, 0444);
  2001. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");