i5000_edac.c 42 KB

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  1. /*
  2. * Intel 5000(P/V/X) class Memory Controllers kernel module
  3. *
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License.
  6. *
  7. * Written by Douglas Thompson Linux Networx (http://lnxi.com)
  8. * norsk5@xmission.com
  9. *
  10. * This module is based on the following document:
  11. *
  12. * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
  13. * http://developer.intel.com/design/chipsets/datashts/313070.htm
  14. *
  15. */
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/pci.h>
  19. #include <linux/pci_ids.h>
  20. #include <linux/slab.h>
  21. #include <linux/edac.h>
  22. #include <asm/mmzone.h>
  23. #include "edac_module.h"
  24. /*
  25. * Alter this version for the I5000 module when modifications are made
  26. */
  27. #define I5000_REVISION " Ver: 2.0.12"
  28. #define EDAC_MOD_STR "i5000_edac"
  29. #define i5000_printk(level, fmt, arg...) \
  30. edac_printk(level, "i5000", fmt, ##arg)
  31. #define i5000_mc_printk(mci, level, fmt, arg...) \
  32. edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
  33. #ifndef PCI_DEVICE_ID_INTEL_FBD_0
  34. #define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5
  35. #endif
  36. #ifndef PCI_DEVICE_ID_INTEL_FBD_1
  37. #define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6
  38. #endif
  39. /* Device 16,
  40. * Function 0: System Address
  41. * Function 1: Memory Branch Map, Control, Errors Register
  42. * Function 2: FSB Error Registers
  43. *
  44. * All 3 functions of Device 16 (0,1,2) share the SAME DID
  45. */
  46. #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
  47. /* OFFSETS for Function 0 */
  48. /* OFFSETS for Function 1 */
  49. #define AMBASE 0x48
  50. #define MAXCH 0x56
  51. #define MAXDIMMPERCH 0x57
  52. #define TOLM 0x6C
  53. #define REDMEMB 0x7C
  54. #define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF)
  55. #define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
  56. #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00)
  57. #define MIR0 0x80
  58. #define MIR1 0x84
  59. #define MIR2 0x88
  60. #define AMIR0 0x8C
  61. #define AMIR1 0x90
  62. #define AMIR2 0x94
  63. #define FERR_FAT_FBD 0x98
  64. #define NERR_FAT_FBD 0x9C
  65. #define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
  66. #define FERR_FAT_FBDCHAN 0x30000000
  67. #define FERR_FAT_M3ERR 0x00000004
  68. #define FERR_FAT_M2ERR 0x00000002
  69. #define FERR_FAT_M1ERR 0x00000001
  70. #define FERR_FAT_MASK (FERR_FAT_M1ERR | \
  71. FERR_FAT_M2ERR | \
  72. FERR_FAT_M3ERR)
  73. #define FERR_NF_FBD 0xA0
  74. /* Thermal and SPD or BFD errors */
  75. #define FERR_NF_M28ERR 0x01000000
  76. #define FERR_NF_M27ERR 0x00800000
  77. #define FERR_NF_M26ERR 0x00400000
  78. #define FERR_NF_M25ERR 0x00200000
  79. #define FERR_NF_M24ERR 0x00100000
  80. #define FERR_NF_M23ERR 0x00080000
  81. #define FERR_NF_M22ERR 0x00040000
  82. #define FERR_NF_M21ERR 0x00020000
  83. /* Correctable errors */
  84. #define FERR_NF_M20ERR 0x00010000
  85. #define FERR_NF_M19ERR 0x00008000
  86. #define FERR_NF_M18ERR 0x00004000
  87. #define FERR_NF_M17ERR 0x00002000
  88. /* Non-Retry or redundant Retry errors */
  89. #define FERR_NF_M16ERR 0x00001000
  90. #define FERR_NF_M15ERR 0x00000800
  91. #define FERR_NF_M14ERR 0x00000400
  92. #define FERR_NF_M13ERR 0x00000200
  93. /* Uncorrectable errors */
  94. #define FERR_NF_M12ERR 0x00000100
  95. #define FERR_NF_M11ERR 0x00000080
  96. #define FERR_NF_M10ERR 0x00000040
  97. #define FERR_NF_M9ERR 0x00000020
  98. #define FERR_NF_M8ERR 0x00000010
  99. #define FERR_NF_M7ERR 0x00000008
  100. #define FERR_NF_M6ERR 0x00000004
  101. #define FERR_NF_M5ERR 0x00000002
  102. #define FERR_NF_M4ERR 0x00000001
  103. #define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
  104. FERR_NF_M11ERR | \
  105. FERR_NF_M10ERR | \
  106. FERR_NF_M9ERR | \
  107. FERR_NF_M8ERR | \
  108. FERR_NF_M7ERR | \
  109. FERR_NF_M6ERR | \
  110. FERR_NF_M5ERR | \
  111. FERR_NF_M4ERR)
  112. #define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
  113. FERR_NF_M19ERR | \
  114. FERR_NF_M18ERR | \
  115. FERR_NF_M17ERR)
  116. #define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
  117. FERR_NF_M28ERR)
  118. #define FERR_NF_THERMAL (FERR_NF_M26ERR | \
  119. FERR_NF_M25ERR | \
  120. FERR_NF_M24ERR | \
  121. FERR_NF_M23ERR)
  122. #define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
  123. #define FERR_NF_NORTH_CRC (FERR_NF_M21ERR)
  124. #define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \
  125. FERR_NF_M14ERR | \
  126. FERR_NF_M15ERR)
  127. #define NERR_NF_FBD 0xA4
  128. #define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \
  129. FERR_NF_CORRECTABLE | \
  130. FERR_NF_DIMM_SPARE | \
  131. FERR_NF_THERMAL | \
  132. FERR_NF_SPD_PROTOCOL | \
  133. FERR_NF_NORTH_CRC | \
  134. FERR_NF_NON_RETRY)
  135. #define EMASK_FBD 0xA8
  136. #define EMASK_FBD_M28ERR 0x08000000
  137. #define EMASK_FBD_M27ERR 0x04000000
  138. #define EMASK_FBD_M26ERR 0x02000000
  139. #define EMASK_FBD_M25ERR 0x01000000
  140. #define EMASK_FBD_M24ERR 0x00800000
  141. #define EMASK_FBD_M23ERR 0x00400000
  142. #define EMASK_FBD_M22ERR 0x00200000
  143. #define EMASK_FBD_M21ERR 0x00100000
  144. #define EMASK_FBD_M20ERR 0x00080000
  145. #define EMASK_FBD_M19ERR 0x00040000
  146. #define EMASK_FBD_M18ERR 0x00020000
  147. #define EMASK_FBD_M17ERR 0x00010000
  148. #define EMASK_FBD_M15ERR 0x00004000
  149. #define EMASK_FBD_M14ERR 0x00002000
  150. #define EMASK_FBD_M13ERR 0x00001000
  151. #define EMASK_FBD_M12ERR 0x00000800
  152. #define EMASK_FBD_M11ERR 0x00000400
  153. #define EMASK_FBD_M10ERR 0x00000200
  154. #define EMASK_FBD_M9ERR 0x00000100
  155. #define EMASK_FBD_M8ERR 0x00000080
  156. #define EMASK_FBD_M7ERR 0x00000040
  157. #define EMASK_FBD_M6ERR 0x00000020
  158. #define EMASK_FBD_M5ERR 0x00000010
  159. #define EMASK_FBD_M4ERR 0x00000008
  160. #define EMASK_FBD_M3ERR 0x00000004
  161. #define EMASK_FBD_M2ERR 0x00000002
  162. #define EMASK_FBD_M1ERR 0x00000001
  163. #define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \
  164. EMASK_FBD_M2ERR | \
  165. EMASK_FBD_M3ERR)
  166. #define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \
  167. EMASK_FBD_M5ERR | \
  168. EMASK_FBD_M6ERR | \
  169. EMASK_FBD_M7ERR | \
  170. EMASK_FBD_M8ERR | \
  171. EMASK_FBD_M9ERR | \
  172. EMASK_FBD_M10ERR | \
  173. EMASK_FBD_M11ERR | \
  174. EMASK_FBD_M12ERR)
  175. #define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \
  176. EMASK_FBD_M18ERR | \
  177. EMASK_FBD_M19ERR | \
  178. EMASK_FBD_M20ERR)
  179. #define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
  180. EMASK_FBD_M28ERR)
  181. #define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \
  182. EMASK_FBD_M25ERR | \
  183. EMASK_FBD_M24ERR | \
  184. EMASK_FBD_M23ERR)
  185. #define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR)
  186. #define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR)
  187. #define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \
  188. EMASK_FBD_M14ERR | \
  189. EMASK_FBD_M13ERR)
  190. #define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \
  191. ENABLE_EMASK_FBD_NORTH_CRC | \
  192. ENABLE_EMASK_FBD_SPD_PROTOCOL | \
  193. ENABLE_EMASK_FBD_THERMALS | \
  194. ENABLE_EMASK_FBD_DIMM_SPARE | \
  195. ENABLE_EMASK_FBD_FATAL_ERRORS | \
  196. ENABLE_EMASK_FBD_CORRECTABLE | \
  197. ENABLE_EMASK_FBD_UNCORRECTABLE)
  198. #define ERR0_FBD 0xAC
  199. #define ERR1_FBD 0xB0
  200. #define ERR2_FBD 0xB4
  201. #define MCERR_FBD 0xB8
  202. #define NRECMEMA 0xBE
  203. #define NREC_BANK(x) (((x)>>12) & 0x7)
  204. #define NREC_RDWR(x) (((x)>>11) & 1)
  205. #define NREC_RANK(x) (((x)>>8) & 0x7)
  206. #define NRECMEMB 0xC0
  207. #define NREC_CAS(x) (((x)>>16) & 0xFFF)
  208. #define NREC_RAS(x) ((x) & 0x7FFF)
  209. #define NRECFGLOG 0xC4
  210. #define NREEECFBDA 0xC8
  211. #define NREEECFBDB 0xCC
  212. #define NREEECFBDC 0xD0
  213. #define NREEECFBDD 0xD4
  214. #define NREEECFBDE 0xD8
  215. #define REDMEMA 0xDC
  216. #define RECMEMA 0xE2
  217. #define REC_BANK(x) (((x)>>12) & 0x7)
  218. #define REC_RDWR(x) (((x)>>11) & 1)
  219. #define REC_RANK(x) (((x)>>8) & 0x7)
  220. #define RECMEMB 0xE4
  221. #define REC_CAS(x) (((x)>>16) & 0xFFFFFF)
  222. #define REC_RAS(x) ((x) & 0x7FFF)
  223. #define RECFGLOG 0xE8
  224. #define RECFBDA 0xEC
  225. #define RECFBDB 0xF0
  226. #define RECFBDC 0xF4
  227. #define RECFBDD 0xF8
  228. #define RECFBDE 0xFC
  229. /* OFFSETS for Function 2 */
  230. /*
  231. * Device 21,
  232. * Function 0: Memory Map Branch 0
  233. *
  234. * Device 22,
  235. * Function 0: Memory Map Branch 1
  236. */
  237. #define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5
  238. #define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6
  239. #define AMB_PRESENT_0 0x64
  240. #define AMB_PRESENT_1 0x66
  241. #define MTR0 0x80
  242. #define MTR1 0x84
  243. #define MTR2 0x88
  244. #define MTR3 0x8C
  245. #define NUM_MTRS 4
  246. #define CHANNELS_PER_BRANCH 2
  247. #define MAX_BRANCHES 2
  248. /* Defines to extract the various fields from the
  249. * MTRx - Memory Technology Registers
  250. */
  251. #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
  252. #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
  253. #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
  254. #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
  255. #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
  256. #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
  257. #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
  258. #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
  259. #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
  260. #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
  261. /* enables the report of miscellaneous messages as CE errors - default off */
  262. static int misc_messages;
  263. /* Enumeration of supported devices */
  264. enum i5000_chips {
  265. I5000P = 0,
  266. I5000V = 1, /* future */
  267. I5000X = 2 /* future */
  268. };
  269. /* Device name and register DID (Device ID) */
  270. struct i5000_dev_info {
  271. const char *ctl_name; /* name for this device */
  272. u16 fsb_mapping_errors; /* DID for the branchmap,control */
  273. };
  274. /* Table of devices attributes supported by this driver */
  275. static const struct i5000_dev_info i5000_devs[] = {
  276. [I5000P] = {
  277. .ctl_name = "I5000",
  278. .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
  279. },
  280. };
  281. struct i5000_dimm_info {
  282. int megabytes; /* size, 0 means not present */
  283. int dual_rank;
  284. };
  285. #define MAX_CHANNELS 6 /* max possible channels */
  286. #define MAX_CSROWS (8*2) /* max possible csrows per channel */
  287. /* driver private data structure */
  288. struct i5000_pvt {
  289. struct pci_dev *system_address; /* 16.0 */
  290. struct pci_dev *branchmap_werrors; /* 16.1 */
  291. struct pci_dev *fsb_error_regs; /* 16.2 */
  292. struct pci_dev *branch_0; /* 21.0 */
  293. struct pci_dev *branch_1; /* 22.0 */
  294. u16 tolm; /* top of low memory */
  295. union {
  296. u64 ambase; /* AMB BAR */
  297. struct {
  298. u32 ambase_bottom;
  299. u32 ambase_top;
  300. } u __packed;
  301. };
  302. u16 mir0, mir1, mir2;
  303. u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
  304. u16 b0_ambpresent0; /* Branch 0, Channel 0 */
  305. u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
  306. u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
  307. u16 b1_ambpresent0; /* Branch 1, Channel 8 */
  308. u16 b1_ambpresent1; /* Branch 1, Channel 1 */
  309. /* DIMM information matrix, allocating architecture maximums */
  310. struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
  311. /* Actual values for this controller */
  312. int maxch; /* Max channels */
  313. int maxdimmperch; /* Max DIMMs per channel */
  314. };
  315. /* I5000 MCH error information retrieved from Hardware */
  316. struct i5000_error_info {
  317. /* These registers are always read from the MC */
  318. u32 ferr_fat_fbd; /* First Errors Fatal */
  319. u32 nerr_fat_fbd; /* Next Errors Fatal */
  320. u32 ferr_nf_fbd; /* First Errors Non-Fatal */
  321. u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
  322. /* These registers are input ONLY if there was a Recoverable Error */
  323. u32 redmemb; /* Recoverable Mem Data Error log B */
  324. u16 recmema; /* Recoverable Mem Error log A */
  325. u32 recmemb; /* Recoverable Mem Error log B */
  326. /* These registers are input ONLY if there was a
  327. * Non-Recoverable Error */
  328. u16 nrecmema; /* Non-Recoverable Mem log A */
  329. u32 nrecmemb; /* Non-Recoverable Mem log B */
  330. };
  331. static struct edac_pci_ctl_info *i5000_pci;
  332. /*
  333. * i5000_get_error_info Retrieve the hardware error information from
  334. * the hardware and cache it in the 'info'
  335. * structure
  336. */
  337. static void i5000_get_error_info(struct mem_ctl_info *mci,
  338. struct i5000_error_info *info)
  339. {
  340. struct i5000_pvt *pvt;
  341. u32 value;
  342. pvt = mci->pvt_info;
  343. /* read in the 1st FATAL error register */
  344. pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
  345. /* Mask only the bits that the doc says are valid
  346. */
  347. value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
  348. /* If there is an error, then read in the */
  349. /* NEXT FATAL error register and the Memory Error Log Register A */
  350. if (value & FERR_FAT_MASK) {
  351. info->ferr_fat_fbd = value;
  352. /* harvest the various error data we need */
  353. pci_read_config_dword(pvt->branchmap_werrors,
  354. NERR_FAT_FBD, &info->nerr_fat_fbd);
  355. pci_read_config_word(pvt->branchmap_werrors,
  356. NRECMEMA, &info->nrecmema);
  357. pci_read_config_dword(pvt->branchmap_werrors,
  358. NRECMEMB, &info->nrecmemb);
  359. /* Clear the error bits, by writing them back */
  360. pci_write_config_dword(pvt->branchmap_werrors,
  361. FERR_FAT_FBD, value);
  362. } else {
  363. info->ferr_fat_fbd = 0;
  364. info->nerr_fat_fbd = 0;
  365. info->nrecmema = 0;
  366. info->nrecmemb = 0;
  367. }
  368. /* read in the 1st NON-FATAL error register */
  369. pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
  370. /* If there is an error, then read in the 1st NON-FATAL error
  371. * register as well */
  372. if (value & FERR_NF_MASK) {
  373. info->ferr_nf_fbd = value;
  374. /* harvest the various error data we need */
  375. pci_read_config_dword(pvt->branchmap_werrors,
  376. NERR_NF_FBD, &info->nerr_nf_fbd);
  377. pci_read_config_word(pvt->branchmap_werrors,
  378. RECMEMA, &info->recmema);
  379. pci_read_config_dword(pvt->branchmap_werrors,
  380. RECMEMB, &info->recmemb);
  381. pci_read_config_dword(pvt->branchmap_werrors,
  382. REDMEMB, &info->redmemb);
  383. /* Clear the error bits, by writing them back */
  384. pci_write_config_dword(pvt->branchmap_werrors,
  385. FERR_NF_FBD, value);
  386. } else {
  387. info->ferr_nf_fbd = 0;
  388. info->nerr_nf_fbd = 0;
  389. info->recmema = 0;
  390. info->recmemb = 0;
  391. info->redmemb = 0;
  392. }
  393. }
  394. /*
  395. * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
  396. * struct i5000_error_info *info,
  397. * int handle_errors);
  398. *
  399. * handle the Intel FATAL errors, if any
  400. */
  401. static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
  402. struct i5000_error_info *info,
  403. int handle_errors)
  404. {
  405. char msg[EDAC_MC_LABEL_LEN + 1 + 160];
  406. char *specific = NULL;
  407. u32 allErrors;
  408. int channel;
  409. int bank;
  410. int rank;
  411. int rdwr;
  412. int ras, cas;
  413. /* mask off the Error bits that are possible */
  414. allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
  415. if (!allErrors)
  416. return; /* if no error, return now */
  417. channel = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
  418. /* Use the NON-Recoverable macros to extract data */
  419. bank = NREC_BANK(info->nrecmema);
  420. rank = NREC_RANK(info->nrecmema);
  421. rdwr = NREC_RDWR(info->nrecmema);
  422. ras = NREC_RAS(info->nrecmemb);
  423. cas = NREC_CAS(info->nrecmemb);
  424. edac_dbg(0, "\t\tCSROW= %d Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
  425. rank, channel, bank,
  426. rdwr ? "Write" : "Read", ras, cas);
  427. /* Only 1 bit will be on */
  428. switch (allErrors) {
  429. case FERR_FAT_M1ERR:
  430. specific = "Alert on non-redundant retry or fast "
  431. "reset timeout";
  432. break;
  433. case FERR_FAT_M2ERR:
  434. specific = "Northbound CRC error on non-redundant "
  435. "retry";
  436. break;
  437. case FERR_FAT_M3ERR:
  438. {
  439. static int done;
  440. /*
  441. * This error is generated to inform that the intelligent
  442. * throttling is disabled and the temperature passed the
  443. * specified middle point. Since this is something the BIOS
  444. * should take care of, we'll warn only once to avoid
  445. * worthlessly flooding the log.
  446. */
  447. if (done)
  448. return;
  449. done++;
  450. specific = ">Tmid Thermal event with intelligent "
  451. "throttling disabled";
  452. }
  453. break;
  454. }
  455. /* Form out message */
  456. snprintf(msg, sizeof(msg),
  457. "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)",
  458. bank, ras, cas, allErrors, specific);
  459. /* Call the helper to output message */
  460. edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0,
  461. channel >> 1, channel & 1, rank,
  462. rdwr ? "Write error" : "Read error",
  463. msg);
  464. }
  465. /*
  466. * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
  467. * struct i5000_error_info *info,
  468. * int handle_errors);
  469. *
  470. * handle the Intel NON-FATAL errors, if any
  471. */
  472. static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
  473. struct i5000_error_info *info,
  474. int handle_errors)
  475. {
  476. char msg[EDAC_MC_LABEL_LEN + 1 + 170];
  477. char *specific = NULL;
  478. u32 allErrors;
  479. u32 ue_errors;
  480. u32 ce_errors;
  481. u32 misc_errors;
  482. int branch;
  483. int channel;
  484. int bank;
  485. int rank;
  486. int rdwr;
  487. int ras, cas;
  488. /* mask off the Error bits that are possible */
  489. allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
  490. if (!allErrors)
  491. return; /* if no error, return now */
  492. /* ONLY ONE of the possible error bits will be set, as per the docs */
  493. ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
  494. if (ue_errors) {
  495. edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors);
  496. branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
  497. /*
  498. * According with i5000 datasheet, bit 28 has no significance
  499. * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
  500. */
  501. channel = branch & 2;
  502. bank = NREC_BANK(info->nrecmema);
  503. rank = NREC_RANK(info->nrecmema);
  504. rdwr = NREC_RDWR(info->nrecmema);
  505. ras = NREC_RAS(info->nrecmemb);
  506. cas = NREC_CAS(info->nrecmemb);
  507. edac_dbg(0, "\t\tCSROW= %d Channels= %d,%d (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
  508. rank, channel, channel + 1, branch >> 1, bank,
  509. rdwr ? "Write" : "Read", ras, cas);
  510. switch (ue_errors) {
  511. case FERR_NF_M12ERR:
  512. specific = "Non-Aliased Uncorrectable Patrol Data ECC";
  513. break;
  514. case FERR_NF_M11ERR:
  515. specific = "Non-Aliased Uncorrectable Spare-Copy "
  516. "Data ECC";
  517. break;
  518. case FERR_NF_M10ERR:
  519. specific = "Non-Aliased Uncorrectable Mirrored Demand "
  520. "Data ECC";
  521. break;
  522. case FERR_NF_M9ERR:
  523. specific = "Non-Aliased Uncorrectable Non-Mirrored "
  524. "Demand Data ECC";
  525. break;
  526. case FERR_NF_M8ERR:
  527. specific = "Aliased Uncorrectable Patrol Data ECC";
  528. break;
  529. case FERR_NF_M7ERR:
  530. specific = "Aliased Uncorrectable Spare-Copy Data ECC";
  531. break;
  532. case FERR_NF_M6ERR:
  533. specific = "Aliased Uncorrectable Mirrored Demand "
  534. "Data ECC";
  535. break;
  536. case FERR_NF_M5ERR:
  537. specific = "Aliased Uncorrectable Non-Mirrored Demand "
  538. "Data ECC";
  539. break;
  540. case FERR_NF_M4ERR:
  541. specific = "Uncorrectable Data ECC on Replay";
  542. break;
  543. }
  544. /* Form out message */
  545. snprintf(msg, sizeof(msg),
  546. "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)",
  547. rank, bank, ras, cas, ue_errors, specific);
  548. /* Call the helper to output message */
  549. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
  550. channel >> 1, -1, rank,
  551. rdwr ? "Write error" : "Read error",
  552. msg);
  553. }
  554. /* Check correctable errors */
  555. ce_errors = allErrors & FERR_NF_CORRECTABLE;
  556. if (ce_errors) {
  557. edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors);
  558. branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
  559. channel = 0;
  560. if (REC_ECC_LOCATOR_ODD(info->redmemb))
  561. channel = 1;
  562. /* Convert channel to be based from zero, instead of
  563. * from branch base of 0 */
  564. channel += branch;
  565. bank = REC_BANK(info->recmema);
  566. rank = REC_RANK(info->recmema);
  567. rdwr = REC_RDWR(info->recmema);
  568. ras = REC_RAS(info->recmemb);
  569. cas = REC_CAS(info->recmemb);
  570. edac_dbg(0, "\t\tCSROW= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
  571. rank, channel, branch >> 1, bank,
  572. rdwr ? "Write" : "Read", ras, cas);
  573. switch (ce_errors) {
  574. case FERR_NF_M17ERR:
  575. specific = "Correctable Non-Mirrored Demand Data ECC";
  576. break;
  577. case FERR_NF_M18ERR:
  578. specific = "Correctable Mirrored Demand Data ECC";
  579. break;
  580. case FERR_NF_M19ERR:
  581. specific = "Correctable Spare-Copy Data ECC";
  582. break;
  583. case FERR_NF_M20ERR:
  584. specific = "Correctable Patrol Data ECC";
  585. break;
  586. }
  587. /* Form out message */
  588. snprintf(msg, sizeof(msg),
  589. "Rank=%d Bank=%d RDWR=%s RAS=%d "
  590. "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
  591. rdwr ? "Write" : "Read", ras, cas, ce_errors,
  592. specific);
  593. /* Call the helper to output message */
  594. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
  595. channel >> 1, channel % 2, rank,
  596. rdwr ? "Write error" : "Read error",
  597. msg);
  598. }
  599. if (!misc_messages)
  600. return;
  601. misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
  602. FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
  603. if (misc_errors) {
  604. switch (misc_errors) {
  605. case FERR_NF_M13ERR:
  606. specific = "Non-Retry or Redundant Retry FBD Memory "
  607. "Alert or Redundant Fast Reset Timeout";
  608. break;
  609. case FERR_NF_M14ERR:
  610. specific = "Non-Retry or Redundant Retry FBD "
  611. "Configuration Alert";
  612. break;
  613. case FERR_NF_M15ERR:
  614. specific = "Non-Retry or Redundant Retry FBD "
  615. "Northbound CRC error on read data";
  616. break;
  617. case FERR_NF_M21ERR:
  618. specific = "FBD Northbound CRC error on "
  619. "FBD Sync Status";
  620. break;
  621. case FERR_NF_M22ERR:
  622. specific = "SPD protocol error";
  623. break;
  624. case FERR_NF_M27ERR:
  625. specific = "DIMM-spare copy started";
  626. break;
  627. case FERR_NF_M28ERR:
  628. specific = "DIMM-spare copy completed";
  629. break;
  630. }
  631. branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
  632. /* Form out message */
  633. snprintf(msg, sizeof(msg),
  634. "Err=%#x (%s)", misc_errors, specific);
  635. /* Call the helper to output message */
  636. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
  637. branch >> 1, -1, -1,
  638. "Misc error", msg);
  639. }
  640. }
  641. /*
  642. * i5000_process_error_info Process the error info that is
  643. * in the 'info' structure, previously retrieved from hardware
  644. */
  645. static void i5000_process_error_info(struct mem_ctl_info *mci,
  646. struct i5000_error_info *info,
  647. int handle_errors)
  648. {
  649. /* First handle any fatal errors that occurred */
  650. i5000_process_fatal_error_info(mci, info, handle_errors);
  651. /* now handle any non-fatal errors that occurred */
  652. i5000_process_nonfatal_error_info(mci, info, handle_errors);
  653. }
  654. /*
  655. * i5000_clear_error Retrieve any error from the hardware
  656. * but do NOT process that error.
  657. * Used for 'clearing' out of previous errors
  658. * Called by the Core module.
  659. */
  660. static void i5000_clear_error(struct mem_ctl_info *mci)
  661. {
  662. struct i5000_error_info info;
  663. i5000_get_error_info(mci, &info);
  664. }
  665. /*
  666. * i5000_check_error Retrieve and process errors reported by the
  667. * hardware. Called by the Core module.
  668. */
  669. static void i5000_check_error(struct mem_ctl_info *mci)
  670. {
  671. struct i5000_error_info info;
  672. edac_dbg(4, "MC%d\n", mci->mc_idx);
  673. i5000_get_error_info(mci, &info);
  674. i5000_process_error_info(mci, &info, 1);
  675. }
  676. /*
  677. * i5000_get_devices Find and perform 'get' operation on the MCH's
  678. * device/functions we want to reference for this driver
  679. *
  680. * Need to 'get' device 16 func 1 and func 2
  681. */
  682. static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
  683. {
  684. //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
  685. struct i5000_pvt *pvt;
  686. struct pci_dev *pdev;
  687. pvt = mci->pvt_info;
  688. /* Attempt to 'get' the MCH register we want */
  689. pdev = NULL;
  690. while (1) {
  691. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  692. PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
  693. /* End of list, leave */
  694. if (pdev == NULL) {
  695. i5000_printk(KERN_ERR,
  696. "'system address,Process Bus' "
  697. "device not found:"
  698. "vendor 0x%x device 0x%x FUNC 1 "
  699. "(broken BIOS?)\n",
  700. PCI_VENDOR_ID_INTEL,
  701. PCI_DEVICE_ID_INTEL_I5000_DEV16);
  702. return 1;
  703. }
  704. /* Scan for device 16 func 1 */
  705. if (PCI_FUNC(pdev->devfn) == 1)
  706. break;
  707. }
  708. pvt->branchmap_werrors = pdev;
  709. /* Attempt to 'get' the MCH register we want */
  710. pdev = NULL;
  711. while (1) {
  712. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  713. PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
  714. if (pdev == NULL) {
  715. i5000_printk(KERN_ERR,
  716. "MC: 'branchmap,control,errors' "
  717. "device not found:"
  718. "vendor 0x%x device 0x%x Func 2 "
  719. "(broken BIOS?)\n",
  720. PCI_VENDOR_ID_INTEL,
  721. PCI_DEVICE_ID_INTEL_I5000_DEV16);
  722. pci_dev_put(pvt->branchmap_werrors);
  723. return 1;
  724. }
  725. /* Scan for device 16 func 1 */
  726. if (PCI_FUNC(pdev->devfn) == 2)
  727. break;
  728. }
  729. pvt->fsb_error_regs = pdev;
  730. edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n",
  731. pci_name(pvt->system_address),
  732. pvt->system_address->vendor, pvt->system_address->device);
  733. edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
  734. pci_name(pvt->branchmap_werrors),
  735. pvt->branchmap_werrors->vendor,
  736. pvt->branchmap_werrors->device);
  737. edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n",
  738. pci_name(pvt->fsb_error_regs),
  739. pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
  740. pdev = NULL;
  741. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  742. PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
  743. if (pdev == NULL) {
  744. i5000_printk(KERN_ERR,
  745. "MC: 'BRANCH 0' device not found:"
  746. "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
  747. PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
  748. pci_dev_put(pvt->branchmap_werrors);
  749. pci_dev_put(pvt->fsb_error_regs);
  750. return 1;
  751. }
  752. pvt->branch_0 = pdev;
  753. /* If this device claims to have more than 2 channels then
  754. * fetch Branch 1's information
  755. */
  756. if (pvt->maxch >= CHANNELS_PER_BRANCH) {
  757. pdev = NULL;
  758. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  759. PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
  760. if (pdev == NULL) {
  761. i5000_printk(KERN_ERR,
  762. "MC: 'BRANCH 1' device not found:"
  763. "vendor 0x%x device 0x%x Func 0 "
  764. "(broken BIOS?)\n",
  765. PCI_VENDOR_ID_INTEL,
  766. PCI_DEVICE_ID_I5000_BRANCH_1);
  767. pci_dev_put(pvt->branchmap_werrors);
  768. pci_dev_put(pvt->fsb_error_regs);
  769. pci_dev_put(pvt->branch_0);
  770. return 1;
  771. }
  772. pvt->branch_1 = pdev;
  773. }
  774. return 0;
  775. }
  776. /*
  777. * i5000_put_devices 'put' all the devices that we have
  778. * reserved via 'get'
  779. */
  780. static void i5000_put_devices(struct mem_ctl_info *mci)
  781. {
  782. struct i5000_pvt *pvt;
  783. pvt = mci->pvt_info;
  784. pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
  785. pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
  786. pci_dev_put(pvt->branch_0); /* DEV 21 */
  787. /* Only if more than 2 channels do we release the second branch */
  788. if (pvt->maxch >= CHANNELS_PER_BRANCH)
  789. pci_dev_put(pvt->branch_1); /* DEV 22 */
  790. }
  791. /*
  792. * determine_amb_resent
  793. *
  794. * the information is contained in NUM_MTRS different registers
  795. * determineing which of the NUM_MTRS requires knowing
  796. * which channel is in question
  797. *
  798. * 2 branches, each with 2 channels
  799. * b0_ambpresent0 for channel '0'
  800. * b0_ambpresent1 for channel '1'
  801. * b1_ambpresent0 for channel '2'
  802. * b1_ambpresent1 for channel '3'
  803. */
  804. static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
  805. {
  806. int amb_present;
  807. if (channel < CHANNELS_PER_BRANCH) {
  808. if (channel & 0x1)
  809. amb_present = pvt->b0_ambpresent1;
  810. else
  811. amb_present = pvt->b0_ambpresent0;
  812. } else {
  813. if (channel & 0x1)
  814. amb_present = pvt->b1_ambpresent1;
  815. else
  816. amb_present = pvt->b1_ambpresent0;
  817. }
  818. return amb_present;
  819. }
  820. /*
  821. * determine_mtr(pvt, csrow, channel)
  822. *
  823. * return the proper MTR register as determine by the csrow and channel desired
  824. */
  825. static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel)
  826. {
  827. int mtr;
  828. if (channel < CHANNELS_PER_BRANCH)
  829. mtr = pvt->b0_mtr[slot];
  830. else
  831. mtr = pvt->b1_mtr[slot];
  832. return mtr;
  833. }
  834. /*
  835. */
  836. static void decode_mtr(int slot_row, u16 mtr)
  837. {
  838. int ans;
  839. ans = MTR_DIMMS_PRESENT(mtr);
  840. edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n",
  841. slot_row, mtr, ans ? "" : "NOT ");
  842. if (!ans)
  843. return;
  844. edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
  845. edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
  846. edac_dbg(2, "\t\tNUMRANK: %s\n",
  847. MTR_DIMM_RANK(mtr) ? "double" : "single");
  848. edac_dbg(2, "\t\tNUMROW: %s\n",
  849. MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
  850. MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
  851. MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
  852. "reserved");
  853. edac_dbg(2, "\t\tNUMCOL: %s\n",
  854. MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
  855. MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
  856. MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
  857. "reserved");
  858. }
  859. static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
  860. struct i5000_dimm_info *dinfo)
  861. {
  862. int mtr;
  863. int amb_present_reg;
  864. int addrBits;
  865. mtr = determine_mtr(pvt, slot, channel);
  866. if (MTR_DIMMS_PRESENT(mtr)) {
  867. amb_present_reg = determine_amb_present_reg(pvt, channel);
  868. /* Determine if there is a DIMM present in this DIMM slot */
  869. if (amb_present_reg) {
  870. dinfo->dual_rank = MTR_DIMM_RANK(mtr);
  871. /* Start with the number of bits for a Bank
  872. * on the DRAM */
  873. addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
  874. /* Add the number of ROW bits */
  875. addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
  876. /* add the number of COLUMN bits */
  877. addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
  878. /* Dual-rank memories have twice the size */
  879. if (dinfo->dual_rank)
  880. addrBits++;
  881. addrBits += 6; /* add 64 bits per DIMM */
  882. addrBits -= 20; /* divide by 2^^20 */
  883. addrBits -= 3; /* 8 bits per bytes */
  884. dinfo->megabytes = 1 << addrBits;
  885. }
  886. }
  887. }
  888. /*
  889. * calculate_dimm_size
  890. *
  891. * also will output a DIMM matrix map, if debug is enabled, for viewing
  892. * how the DIMMs are populated
  893. */
  894. static void calculate_dimm_size(struct i5000_pvt *pvt)
  895. {
  896. struct i5000_dimm_info *dinfo;
  897. int slot, channel, branch;
  898. char *p, *mem_buffer;
  899. int space, n;
  900. /* ================= Generate some debug output ================= */
  901. space = PAGE_SIZE;
  902. mem_buffer = p = kmalloc(space, GFP_KERNEL);
  903. if (p == NULL) {
  904. i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
  905. __FILE__, __func__);
  906. return;
  907. }
  908. /* Scan all the actual slots
  909. * and calculate the information for each DIMM
  910. * Start with the highest slot first, to display it first
  911. * and work toward the 0th slot
  912. */
  913. for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) {
  914. /* on an odd slot, first output a 'boundary' marker,
  915. * then reset the message buffer */
  916. if (slot & 0x1) {
  917. n = snprintf(p, space, "--------------------------"
  918. "--------------------------------");
  919. p += n;
  920. space -= n;
  921. edac_dbg(2, "%s\n", mem_buffer);
  922. p = mem_buffer;
  923. space = PAGE_SIZE;
  924. }
  925. n = snprintf(p, space, "slot %2d ", slot);
  926. p += n;
  927. space -= n;
  928. for (channel = 0; channel < pvt->maxch; channel++) {
  929. dinfo = &pvt->dimm_info[slot][channel];
  930. handle_channel(pvt, slot, channel, dinfo);
  931. if (dinfo->megabytes)
  932. n = snprintf(p, space, "%4d MB %dR| ",
  933. dinfo->megabytes, dinfo->dual_rank + 1);
  934. else
  935. n = snprintf(p, space, "%4d MB | ", 0);
  936. p += n;
  937. space -= n;
  938. }
  939. p += n;
  940. space -= n;
  941. edac_dbg(2, "%s\n", mem_buffer);
  942. p = mem_buffer;
  943. space = PAGE_SIZE;
  944. }
  945. /* Output the last bottom 'boundary' marker */
  946. n = snprintf(p, space, "--------------------------"
  947. "--------------------------------");
  948. p += n;
  949. space -= n;
  950. edac_dbg(2, "%s\n", mem_buffer);
  951. p = mem_buffer;
  952. space = PAGE_SIZE;
  953. /* now output the 'channel' labels */
  954. n = snprintf(p, space, " ");
  955. p += n;
  956. space -= n;
  957. for (channel = 0; channel < pvt->maxch; channel++) {
  958. n = snprintf(p, space, "channel %d | ", channel);
  959. p += n;
  960. space -= n;
  961. }
  962. edac_dbg(2, "%s\n", mem_buffer);
  963. p = mem_buffer;
  964. space = PAGE_SIZE;
  965. n = snprintf(p, space, " ");
  966. p += n;
  967. for (branch = 0; branch < MAX_BRANCHES; branch++) {
  968. n = snprintf(p, space, " branch %d | ", branch);
  969. p += n;
  970. space -= n;
  971. }
  972. /* output the last message and free buffer */
  973. edac_dbg(2, "%s\n", mem_buffer);
  974. kfree(mem_buffer);
  975. }
  976. /*
  977. * i5000_get_mc_regs read in the necessary registers and
  978. * cache locally
  979. *
  980. * Fills in the private data members
  981. */
  982. static void i5000_get_mc_regs(struct mem_ctl_info *mci)
  983. {
  984. struct i5000_pvt *pvt;
  985. u32 actual_tolm;
  986. u16 limit;
  987. int slot_row;
  988. int way0, way1;
  989. pvt = mci->pvt_info;
  990. pci_read_config_dword(pvt->system_address, AMBASE,
  991. &pvt->u.ambase_bottom);
  992. pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
  993. &pvt->u.ambase_top);
  994. edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
  995. (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
  996. /* Get the Branch Map regs */
  997. pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
  998. pvt->tolm >>= 12;
  999. edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
  1000. pvt->tolm, pvt->tolm);
  1001. actual_tolm = pvt->tolm << 28;
  1002. edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n",
  1003. actual_tolm, actual_tolm);
  1004. pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
  1005. pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
  1006. pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
  1007. /* Get the MIR[0-2] regs */
  1008. limit = (pvt->mir0 >> 4) & 0x0FFF;
  1009. way0 = pvt->mir0 & 0x1;
  1010. way1 = pvt->mir0 & 0x2;
  1011. edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n",
  1012. limit, way1, way0);
  1013. limit = (pvt->mir1 >> 4) & 0x0FFF;
  1014. way0 = pvt->mir1 & 0x1;
  1015. way1 = pvt->mir1 & 0x2;
  1016. edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n",
  1017. limit, way1, way0);
  1018. limit = (pvt->mir2 >> 4) & 0x0FFF;
  1019. way0 = pvt->mir2 & 0x1;
  1020. way1 = pvt->mir2 & 0x2;
  1021. edac_dbg(2, "MIR2: limit= 0x%x WAY1= %u WAY0= %x\n",
  1022. limit, way1, way0);
  1023. /* Get the MTR[0-3] regs */
  1024. for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
  1025. int where = MTR0 + (slot_row * sizeof(u32));
  1026. pci_read_config_word(pvt->branch_0, where,
  1027. &pvt->b0_mtr[slot_row]);
  1028. edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
  1029. slot_row, where, pvt->b0_mtr[slot_row]);
  1030. if (pvt->maxch >= CHANNELS_PER_BRANCH) {
  1031. pci_read_config_word(pvt->branch_1, where,
  1032. &pvt->b1_mtr[slot_row]);
  1033. edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
  1034. slot_row, where, pvt->b1_mtr[slot_row]);
  1035. } else {
  1036. pvt->b1_mtr[slot_row] = 0;
  1037. }
  1038. }
  1039. /* Read and dump branch 0's MTRs */
  1040. edac_dbg(2, "Memory Technology Registers:\n");
  1041. edac_dbg(2, " Branch 0:\n");
  1042. for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
  1043. decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
  1044. }
  1045. pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
  1046. &pvt->b0_ambpresent0);
  1047. edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
  1048. pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
  1049. &pvt->b0_ambpresent1);
  1050. edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
  1051. /* Only if we have 2 branchs (4 channels) */
  1052. if (pvt->maxch < CHANNELS_PER_BRANCH) {
  1053. pvt->b1_ambpresent0 = 0;
  1054. pvt->b1_ambpresent1 = 0;
  1055. } else {
  1056. /* Read and dump branch 1's MTRs */
  1057. edac_dbg(2, " Branch 1:\n");
  1058. for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
  1059. decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
  1060. }
  1061. pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
  1062. &pvt->b1_ambpresent0);
  1063. edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
  1064. pvt->b1_ambpresent0);
  1065. pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
  1066. &pvt->b1_ambpresent1);
  1067. edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
  1068. pvt->b1_ambpresent1);
  1069. }
  1070. /* Go and determine the size of each DIMM and place in an
  1071. * orderly matrix */
  1072. calculate_dimm_size(pvt);
  1073. }
  1074. /*
  1075. * i5000_init_csrows Initialize the 'csrows' table within
  1076. * the mci control structure with the
  1077. * addressing of memory.
  1078. *
  1079. * return:
  1080. * 0 success
  1081. * 1 no actual memory found on this MC
  1082. */
  1083. static int i5000_init_csrows(struct mem_ctl_info *mci)
  1084. {
  1085. struct i5000_pvt *pvt;
  1086. struct dimm_info *dimm;
  1087. int empty;
  1088. int max_csrows;
  1089. int mtr;
  1090. int csrow_megs;
  1091. int channel;
  1092. int slot;
  1093. pvt = mci->pvt_info;
  1094. max_csrows = pvt->maxdimmperch * 2;
  1095. empty = 1; /* Assume NO memory */
  1096. /*
  1097. * FIXME: The memory layout used to map slot/channel into the
  1098. * real memory architecture is weird: branch+slot are "csrows"
  1099. * and channel is channel. That required an extra array (dimm_info)
  1100. * to map the dimms. A good cleanup would be to remove this array,
  1101. * and do a loop here with branch, channel, slot
  1102. */
  1103. for (slot = 0; slot < max_csrows; slot++) {
  1104. for (channel = 0; channel < pvt->maxch; channel++) {
  1105. mtr = determine_mtr(pvt, slot, channel);
  1106. if (!MTR_DIMMS_PRESENT(mtr))
  1107. continue;
  1108. dimm = edac_get_dimm(mci, channel / MAX_BRANCHES,
  1109. channel % MAX_BRANCHES, slot);
  1110. csrow_megs = pvt->dimm_info[slot][channel].megabytes;
  1111. dimm->grain = 8;
  1112. /* Assume DDR2 for now */
  1113. dimm->mtype = MEM_FB_DDR2;
  1114. /* ask what device type on this row */
  1115. if (MTR_DRAM_WIDTH(mtr) == 8)
  1116. dimm->dtype = DEV_X8;
  1117. else
  1118. dimm->dtype = DEV_X4;
  1119. dimm->edac_mode = EDAC_S8ECD8ED;
  1120. dimm->nr_pages = csrow_megs << 8;
  1121. }
  1122. empty = 0;
  1123. }
  1124. return empty;
  1125. }
  1126. /*
  1127. * i5000_enable_error_reporting
  1128. * Turn on the memory reporting features of the hardware
  1129. */
  1130. static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
  1131. {
  1132. struct i5000_pvt *pvt;
  1133. u32 fbd_error_mask;
  1134. pvt = mci->pvt_info;
  1135. /* Read the FBD Error Mask Register */
  1136. pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
  1137. &fbd_error_mask);
  1138. /* Enable with a '0' */
  1139. fbd_error_mask &= ~(ENABLE_EMASK_ALL);
  1140. pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
  1141. fbd_error_mask);
  1142. }
  1143. /*
  1144. * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels)
  1145. *
  1146. * ask the device how many channels are present and how many CSROWS
  1147. * as well
  1148. */
  1149. static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
  1150. int *num_dimms_per_channel,
  1151. int *num_channels)
  1152. {
  1153. u8 value;
  1154. /* Need to retrieve just how many channels and dimms per channel are
  1155. * supported on this memory controller
  1156. */
  1157. pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
  1158. *num_dimms_per_channel = (int)value;
  1159. pci_read_config_byte(pdev, MAXCH, &value);
  1160. *num_channels = (int)value;
  1161. }
  1162. /*
  1163. * i5000_probe1 Probe for ONE instance of device to see if it is
  1164. * present.
  1165. * return:
  1166. * 0 for FOUND a device
  1167. * < 0 for error code
  1168. */
  1169. static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
  1170. {
  1171. struct mem_ctl_info *mci;
  1172. struct edac_mc_layer layers[3];
  1173. struct i5000_pvt *pvt;
  1174. int num_channels;
  1175. int num_dimms_per_channel;
  1176. edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
  1177. pdev->bus->number,
  1178. PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
  1179. /* We only are looking for func 0 of the set */
  1180. if (PCI_FUNC(pdev->devfn) != 0)
  1181. return -ENODEV;
  1182. /* Ask the devices for the number of CSROWS and CHANNELS so
  1183. * that we can calculate the memory resources, etc
  1184. *
  1185. * The Chipset will report what it can handle which will be greater
  1186. * or equal to what the motherboard manufacturer will implement.
  1187. *
  1188. * As we don't have a motherboard identification routine to determine
  1189. * actual number of slots/dimms per channel, we thus utilize the
  1190. * resource as specified by the chipset. Thus, we might have
  1191. * have more DIMMs per channel than actually on the mobo, but this
  1192. * allows the driver to support up to the chipset max, without
  1193. * some fancy mobo determination.
  1194. */
  1195. i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
  1196. &num_channels);
  1197. edac_dbg(0, "MC: Number of Branches=2 Channels= %d DIMMS= %d\n",
  1198. num_channels, num_dimms_per_channel);
  1199. /* allocate a new MC control structure */
  1200. layers[0].type = EDAC_MC_LAYER_BRANCH;
  1201. layers[0].size = MAX_BRANCHES;
  1202. layers[0].is_virt_csrow = false;
  1203. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  1204. layers[1].size = num_channels / MAX_BRANCHES;
  1205. layers[1].is_virt_csrow = false;
  1206. layers[2].type = EDAC_MC_LAYER_SLOT;
  1207. layers[2].size = num_dimms_per_channel;
  1208. layers[2].is_virt_csrow = true;
  1209. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
  1210. if (mci == NULL)
  1211. return -ENOMEM;
  1212. edac_dbg(0, "MC: mci = %p\n", mci);
  1213. mci->pdev = &pdev->dev; /* record ptr to the generic device */
  1214. pvt = mci->pvt_info;
  1215. pvt->system_address = pdev; /* Record this device in our private */
  1216. pvt->maxch = num_channels;
  1217. pvt->maxdimmperch = num_dimms_per_channel;
  1218. /* 'get' the pci devices we want to reserve for our use */
  1219. if (i5000_get_devices(mci, dev_idx))
  1220. goto fail0;
  1221. /* Time to get serious */
  1222. i5000_get_mc_regs(mci); /* retrieve the hardware registers */
  1223. mci->mc_idx = 0;
  1224. mci->mtype_cap = MEM_FLAG_FB_DDR2;
  1225. mci->edac_ctl_cap = EDAC_FLAG_NONE;
  1226. mci->edac_cap = EDAC_FLAG_NONE;
  1227. mci->mod_name = "i5000_edac.c";
  1228. mci->ctl_name = i5000_devs[dev_idx].ctl_name;
  1229. mci->dev_name = pci_name(pdev);
  1230. mci->ctl_page_to_phys = NULL;
  1231. /* Set the function pointer to an actual operation function */
  1232. mci->edac_check = i5000_check_error;
  1233. /* initialize the MC control structure 'csrows' table
  1234. * with the mapping and control information */
  1235. if (i5000_init_csrows(mci)) {
  1236. edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonzero value\n");
  1237. mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
  1238. } else {
  1239. edac_dbg(1, "MC: Enable error reporting now\n");
  1240. i5000_enable_error_reporting(mci);
  1241. }
  1242. /* add this new MC control structure to EDAC's list of MCs */
  1243. if (edac_mc_add_mc(mci)) {
  1244. edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
  1245. /* FIXME: perhaps some code should go here that disables error
  1246. * reporting if we just enabled it
  1247. */
  1248. goto fail1;
  1249. }
  1250. i5000_clear_error(mci);
  1251. /* allocating generic PCI control info */
  1252. i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  1253. if (!i5000_pci) {
  1254. printk(KERN_WARNING
  1255. "%s(): Unable to create PCI control\n",
  1256. __func__);
  1257. printk(KERN_WARNING
  1258. "%s(): PCI error report via EDAC not setup\n",
  1259. __func__);
  1260. }
  1261. return 0;
  1262. /* Error exit unwinding stack */
  1263. fail1:
  1264. i5000_put_devices(mci);
  1265. fail0:
  1266. edac_mc_free(mci);
  1267. return -ENODEV;
  1268. }
  1269. /*
  1270. * i5000_init_one constructor for one instance of device
  1271. *
  1272. * returns:
  1273. * negative on error
  1274. * count (>= 0)
  1275. */
  1276. static int i5000_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  1277. {
  1278. int rc;
  1279. edac_dbg(0, "MC:\n");
  1280. /* wake up device */
  1281. rc = pci_enable_device(pdev);
  1282. if (rc)
  1283. return rc;
  1284. /* now probe and enable the device */
  1285. return i5000_probe1(pdev, id->driver_data);
  1286. }
  1287. /*
  1288. * i5000_remove_one destructor for one instance of device
  1289. *
  1290. */
  1291. static void i5000_remove_one(struct pci_dev *pdev)
  1292. {
  1293. struct mem_ctl_info *mci;
  1294. edac_dbg(0, "\n");
  1295. if (i5000_pci)
  1296. edac_pci_release_generic_ctl(i5000_pci);
  1297. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  1298. return;
  1299. /* retrieve references to resources, and free those resources */
  1300. i5000_put_devices(mci);
  1301. edac_mc_free(mci);
  1302. }
  1303. /*
  1304. * pci_device_id table for which devices we are looking for
  1305. *
  1306. * The "E500P" device is the first device supported.
  1307. */
  1308. static const struct pci_device_id i5000_pci_tbl[] = {
  1309. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
  1310. .driver_data = I5000P},
  1311. {0,} /* 0 terminated list. */
  1312. };
  1313. MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
  1314. /*
  1315. * i5000_driver pci_driver structure for this module
  1316. *
  1317. */
  1318. static struct pci_driver i5000_driver = {
  1319. .name = KBUILD_BASENAME,
  1320. .probe = i5000_init_one,
  1321. .remove = i5000_remove_one,
  1322. .id_table = i5000_pci_tbl,
  1323. };
  1324. /*
  1325. * i5000_init Module entry function
  1326. * Try to initialize this module for its devices
  1327. */
  1328. static int __init i5000_init(void)
  1329. {
  1330. int pci_rc;
  1331. edac_dbg(2, "MC:\n");
  1332. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  1333. opstate_init();
  1334. pci_rc = pci_register_driver(&i5000_driver);
  1335. return (pci_rc < 0) ? pci_rc : 0;
  1336. }
  1337. /*
  1338. * i5000_exit() Module exit function
  1339. * Unregister the driver
  1340. */
  1341. static void __exit i5000_exit(void)
  1342. {
  1343. edac_dbg(2, "MC:\n");
  1344. pci_unregister_driver(&i5000_driver);
  1345. }
  1346. module_init(i5000_init);
  1347. module_exit(i5000_exit);
  1348. MODULE_LICENSE("GPL");
  1349. MODULE_AUTHOR
  1350. ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
  1351. MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
  1352. I5000_REVISION);
  1353. module_param(edac_op_state, int, 0444);
  1354. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
  1355. module_param(misc_messages, int, 0444);
  1356. MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");