i3000_edac.c 14 KB

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  1. /*
  2. * Intel 3000/3010 Memory Controller kernel module
  3. * Copyright (C) 2007 Akamai Technologies, Inc.
  4. * Shamelessly copied from:
  5. * Intel D82875P Memory Controller kernel module
  6. * (C) 2003 Linux Networx (http://lnxi.com)
  7. *
  8. * This file may be distributed under the terms of the
  9. * GNU General Public License.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/pci.h>
  14. #include <linux/pci_ids.h>
  15. #include <linux/edac.h>
  16. #include "edac_module.h"
  17. #define EDAC_MOD_STR "i3000_edac"
  18. #define I3000_RANKS 8
  19. #define I3000_RANKS_PER_CHANNEL 4
  20. #define I3000_CHANNELS 2
  21. /* Intel 3000 register addresses - device 0 function 0 - DRAM Controller */
  22. #define I3000_MCHBAR 0x44 /* MCH Memory Mapped Register BAR */
  23. #define I3000_MCHBAR_MASK 0xffffc000
  24. #define I3000_MMR_WINDOW_SIZE 16384
  25. #define I3000_EDEAP 0x70 /* Extended DRAM Error Address Pointer (8b)
  26. *
  27. * 7:1 reserved
  28. * 0 bit 32 of address
  29. */
  30. #define I3000_DEAP 0x58 /* DRAM Error Address Pointer (32b)
  31. *
  32. * 31:7 address
  33. * 6:1 reserved
  34. * 0 Error channel 0/1
  35. */
  36. #define I3000_DEAP_GRAIN (1 << 7)
  37. /*
  38. * Helper functions to decode the DEAP/EDEAP hardware registers.
  39. *
  40. * The type promotion here is deliberate; we're deriving an
  41. * unsigned long pfn and offset from hardware regs which are u8/u32.
  42. */
  43. static inline unsigned long deap_pfn(u8 edeap, u32 deap)
  44. {
  45. deap >>= PAGE_SHIFT;
  46. deap |= (edeap & 1) << (32 - PAGE_SHIFT);
  47. return deap;
  48. }
  49. static inline unsigned long deap_offset(u32 deap)
  50. {
  51. return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
  52. }
  53. static inline int deap_channel(u32 deap)
  54. {
  55. return deap & 1;
  56. }
  57. #define I3000_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
  58. *
  59. * 7:0 DRAM ECC Syndrome
  60. */
  61. #define I3000_ERRSTS 0xc8 /* Error Status Register (16b)
  62. *
  63. * 15:12 reserved
  64. * 11 MCH Thermal Sensor Event
  65. * for SMI/SCI/SERR
  66. * 10 reserved
  67. * 9 LOCK to non-DRAM Memory Flag (LCKF)
  68. * 8 Received Refresh Timeout Flag (RRTOF)
  69. * 7:2 reserved
  70. * 1 Multi-bit DRAM ECC Error Flag (DMERR)
  71. * 0 Single-bit DRAM ECC Error Flag (DSERR)
  72. */
  73. #define I3000_ERRSTS_BITS 0x0b03 /* bits which indicate errors */
  74. #define I3000_ERRSTS_UE 0x0002
  75. #define I3000_ERRSTS_CE 0x0001
  76. #define I3000_ERRCMD 0xca /* Error Command (16b)
  77. *
  78. * 15:12 reserved
  79. * 11 SERR on MCH Thermal Sensor Event
  80. * (TSESERR)
  81. * 10 reserved
  82. * 9 SERR on LOCK to non-DRAM Memory
  83. * (LCKERR)
  84. * 8 SERR on DRAM Refresh Timeout
  85. * (DRTOERR)
  86. * 7:2 reserved
  87. * 1 SERR Multi-Bit DRAM ECC Error
  88. * (DMERR)
  89. * 0 SERR on Single-Bit ECC Error
  90. * (DSERR)
  91. */
  92. /* Intel MMIO register space - device 0 function 0 - MMR space */
  93. #define I3000_DRB_SHIFT 25 /* 32MiB grain */
  94. #define I3000_C0DRB 0x100 /* Channel 0 DRAM Rank Boundary (8b x 4)
  95. *
  96. * 7:0 Channel 0 DRAM Rank Boundary Address
  97. */
  98. #define I3000_C1DRB 0x180 /* Channel 1 DRAM Rank Boundary (8b x 4)
  99. *
  100. * 7:0 Channel 1 DRAM Rank Boundary Address
  101. */
  102. #define I3000_C0DRA 0x108 /* Channel 0 DRAM Rank Attribute (8b x 2)
  103. *
  104. * 7 reserved
  105. * 6:4 DRAM odd Rank Attribute
  106. * 3 reserved
  107. * 2:0 DRAM even Rank Attribute
  108. *
  109. * Each attribute defines the page
  110. * size of the corresponding rank:
  111. * 000: unpopulated
  112. * 001: reserved
  113. * 010: 4 KB
  114. * 011: 8 KB
  115. * 100: 16 KB
  116. * Others: reserved
  117. */
  118. #define I3000_C1DRA 0x188 /* Channel 1 DRAM Rank Attribute (8b x 2) */
  119. static inline unsigned char odd_rank_attrib(unsigned char dra)
  120. {
  121. return (dra & 0x70) >> 4;
  122. }
  123. static inline unsigned char even_rank_attrib(unsigned char dra)
  124. {
  125. return dra & 0x07;
  126. }
  127. #define I3000_C0DRC0 0x120 /* DRAM Controller Mode 0 (32b)
  128. *
  129. * 31:30 reserved
  130. * 29 Initialization Complete (IC)
  131. * 28:11 reserved
  132. * 10:8 Refresh Mode Select (RMS)
  133. * 7 reserved
  134. * 6:4 Mode Select (SMS)
  135. * 3:2 reserved
  136. * 1:0 DRAM Type (DT)
  137. */
  138. #define I3000_C0DRC1 0x124 /* DRAM Controller Mode 1 (32b)
  139. *
  140. * 31 Enhanced Addressing Enable (ENHADE)
  141. * 30:0 reserved
  142. */
  143. enum i3000p_chips {
  144. I3000 = 0,
  145. };
  146. struct i3000_dev_info {
  147. const char *ctl_name;
  148. };
  149. struct i3000_error_info {
  150. u16 errsts;
  151. u8 derrsyn;
  152. u8 edeap;
  153. u32 deap;
  154. u16 errsts2;
  155. };
  156. static const struct i3000_dev_info i3000_devs[] = {
  157. [I3000] = {
  158. .ctl_name = "i3000"},
  159. };
  160. static struct pci_dev *mci_pdev;
  161. static int i3000_registered = 1;
  162. static struct edac_pci_ctl_info *i3000_pci;
  163. static void i3000_get_error_info(struct mem_ctl_info *mci,
  164. struct i3000_error_info *info)
  165. {
  166. struct pci_dev *pdev;
  167. pdev = to_pci_dev(mci->pdev);
  168. /*
  169. * This is a mess because there is no atomic way to read all the
  170. * registers at once and the registers can transition from CE being
  171. * overwritten by UE.
  172. */
  173. pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
  174. if (!(info->errsts & I3000_ERRSTS_BITS))
  175. return;
  176. pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
  177. pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
  178. pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
  179. pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
  180. /*
  181. * If the error is the same for both reads then the first set
  182. * of reads is valid. If there is a change then there is a CE
  183. * with no info and the second set of reads is valid and
  184. * should be UE info.
  185. */
  186. if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
  187. pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
  188. pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
  189. pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
  190. }
  191. /*
  192. * Clear any error bits.
  193. * (Yes, we really clear bits by writing 1 to them.)
  194. */
  195. pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
  196. I3000_ERRSTS_BITS);
  197. }
  198. static int i3000_process_error_info(struct mem_ctl_info *mci,
  199. struct i3000_error_info *info,
  200. int handle_errors)
  201. {
  202. int row, multi_chan, channel;
  203. unsigned long pfn, offset;
  204. multi_chan = mci->csrows[0]->nr_channels - 1;
  205. if (!(info->errsts & I3000_ERRSTS_BITS))
  206. return 0;
  207. if (!handle_errors)
  208. return 1;
  209. if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
  210. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
  211. -1, -1, -1,
  212. "UE overwrote CE", "");
  213. info->errsts = info->errsts2;
  214. }
  215. pfn = deap_pfn(info->edeap, info->deap);
  216. offset = deap_offset(info->deap);
  217. channel = deap_channel(info->deap);
  218. row = edac_mc_find_csrow_by_page(mci, pfn);
  219. if (info->errsts & I3000_ERRSTS_UE)
  220. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  221. pfn, offset, 0,
  222. row, -1, -1,
  223. "i3000 UE", "");
  224. else
  225. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  226. pfn, offset, info->derrsyn,
  227. row, multi_chan ? channel : 0, -1,
  228. "i3000 CE", "");
  229. return 1;
  230. }
  231. static void i3000_check(struct mem_ctl_info *mci)
  232. {
  233. struct i3000_error_info info;
  234. edac_dbg(1, "MC%d\n", mci->mc_idx);
  235. i3000_get_error_info(mci, &info);
  236. i3000_process_error_info(mci, &info, 1);
  237. }
  238. static int i3000_is_interleaved(const unsigned char *c0dra,
  239. const unsigned char *c1dra,
  240. const unsigned char *c0drb,
  241. const unsigned char *c1drb)
  242. {
  243. int i;
  244. /*
  245. * If the channels aren't populated identically then
  246. * we're not interleaved.
  247. */
  248. for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
  249. if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
  250. even_rank_attrib(c0dra[i]) !=
  251. even_rank_attrib(c1dra[i]))
  252. return 0;
  253. /*
  254. * If the rank boundaries for the two channels are different
  255. * then we're not interleaved.
  256. */
  257. for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
  258. if (c0drb[i] != c1drb[i])
  259. return 0;
  260. return 1;
  261. }
  262. static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
  263. {
  264. int rc;
  265. int i, j;
  266. struct mem_ctl_info *mci = NULL;
  267. struct edac_mc_layer layers[2];
  268. unsigned long last_cumul_size, nr_pages;
  269. int interleaved, nr_channels;
  270. unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
  271. unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
  272. unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
  273. unsigned long mchbar;
  274. void __iomem *window;
  275. edac_dbg(0, "MC:\n");
  276. pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
  277. mchbar &= I3000_MCHBAR_MASK;
  278. window = ioremap(mchbar, I3000_MMR_WINDOW_SIZE);
  279. if (!window) {
  280. printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
  281. mchbar);
  282. return -ENODEV;
  283. }
  284. c0dra[0] = readb(window + I3000_C0DRA + 0); /* ranks 0,1 */
  285. c0dra[1] = readb(window + I3000_C0DRA + 1); /* ranks 2,3 */
  286. c1dra[0] = readb(window + I3000_C1DRA + 0); /* ranks 0,1 */
  287. c1dra[1] = readb(window + I3000_C1DRA + 1); /* ranks 2,3 */
  288. for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
  289. c0drb[i] = readb(window + I3000_C0DRB + i);
  290. c1drb[i] = readb(window + I3000_C1DRB + i);
  291. }
  292. iounmap(window);
  293. /*
  294. * Figure out how many channels we have.
  295. *
  296. * If we have what the datasheet calls "asymmetric channels"
  297. * (essentially the same as what was called "virtual single
  298. * channel mode" in the i82875) then it's a single channel as
  299. * far as EDAC is concerned.
  300. */
  301. interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
  302. nr_channels = interleaved ? 2 : 1;
  303. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  304. layers[0].size = I3000_RANKS / nr_channels;
  305. layers[0].is_virt_csrow = true;
  306. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  307. layers[1].size = nr_channels;
  308. layers[1].is_virt_csrow = false;
  309. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
  310. if (!mci)
  311. return -ENOMEM;
  312. edac_dbg(3, "MC: init mci\n");
  313. mci->pdev = &pdev->dev;
  314. mci->mtype_cap = MEM_FLAG_DDR2;
  315. mci->edac_ctl_cap = EDAC_FLAG_SECDED;
  316. mci->edac_cap = EDAC_FLAG_SECDED;
  317. mci->mod_name = EDAC_MOD_STR;
  318. mci->ctl_name = i3000_devs[dev_idx].ctl_name;
  319. mci->dev_name = pci_name(pdev);
  320. mci->edac_check = i3000_check;
  321. mci->ctl_page_to_phys = NULL;
  322. /*
  323. * The dram rank boundary (DRB) reg values are boundary addresses
  324. * for each DRAM rank with a granularity of 32MB. DRB regs are
  325. * cumulative; the last one will contain the total memory
  326. * contained in all ranks.
  327. *
  328. * If we're in interleaved mode then we're only walking through
  329. * the ranks of controller 0, so we double all the values we see.
  330. */
  331. for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
  332. u8 value;
  333. u32 cumul_size;
  334. struct csrow_info *csrow = mci->csrows[i];
  335. value = drb[i];
  336. cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
  337. if (interleaved)
  338. cumul_size <<= 1;
  339. edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
  340. if (cumul_size == last_cumul_size)
  341. continue;
  342. csrow->first_page = last_cumul_size;
  343. csrow->last_page = cumul_size - 1;
  344. nr_pages = cumul_size - last_cumul_size;
  345. last_cumul_size = cumul_size;
  346. for (j = 0; j < nr_channels; j++) {
  347. struct dimm_info *dimm = csrow->channels[j]->dimm;
  348. dimm->nr_pages = nr_pages / nr_channels;
  349. dimm->grain = I3000_DEAP_GRAIN;
  350. dimm->mtype = MEM_DDR2;
  351. dimm->dtype = DEV_UNKNOWN;
  352. dimm->edac_mode = EDAC_UNKNOWN;
  353. }
  354. }
  355. /*
  356. * Clear any error bits.
  357. * (Yes, we really clear bits by writing 1 to them.)
  358. */
  359. pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
  360. I3000_ERRSTS_BITS);
  361. rc = -ENODEV;
  362. if (edac_mc_add_mc(mci)) {
  363. edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
  364. goto fail;
  365. }
  366. /* allocating generic PCI control info */
  367. i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  368. if (!i3000_pci) {
  369. printk(KERN_WARNING
  370. "%s(): Unable to create PCI control\n",
  371. __func__);
  372. printk(KERN_WARNING
  373. "%s(): PCI error report via EDAC not setup\n",
  374. __func__);
  375. }
  376. /* get this far and it's successful */
  377. edac_dbg(3, "MC: success\n");
  378. return 0;
  379. fail:
  380. if (mci)
  381. edac_mc_free(mci);
  382. return rc;
  383. }
  384. /* returns count (>= 0), or negative on error */
  385. static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  386. {
  387. int rc;
  388. edac_dbg(0, "MC:\n");
  389. if (pci_enable_device(pdev) < 0)
  390. return -EIO;
  391. rc = i3000_probe1(pdev, ent->driver_data);
  392. if (!mci_pdev)
  393. mci_pdev = pci_dev_get(pdev);
  394. return rc;
  395. }
  396. static void i3000_remove_one(struct pci_dev *pdev)
  397. {
  398. struct mem_ctl_info *mci;
  399. edac_dbg(0, "\n");
  400. if (i3000_pci)
  401. edac_pci_release_generic_ctl(i3000_pci);
  402. mci = edac_mc_del_mc(&pdev->dev);
  403. if (!mci)
  404. return;
  405. edac_mc_free(mci);
  406. }
  407. static const struct pci_device_id i3000_pci_tbl[] = {
  408. {
  409. PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  410. I3000},
  411. {
  412. 0,
  413. } /* 0 terminated list. */
  414. };
  415. MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
  416. static struct pci_driver i3000_driver = {
  417. .name = EDAC_MOD_STR,
  418. .probe = i3000_init_one,
  419. .remove = i3000_remove_one,
  420. .id_table = i3000_pci_tbl,
  421. };
  422. static int __init i3000_init(void)
  423. {
  424. int pci_rc;
  425. edac_dbg(3, "MC:\n");
  426. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  427. opstate_init();
  428. pci_rc = pci_register_driver(&i3000_driver);
  429. if (pci_rc < 0)
  430. goto fail0;
  431. if (!mci_pdev) {
  432. i3000_registered = 0;
  433. mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  434. PCI_DEVICE_ID_INTEL_3000_HB, NULL);
  435. if (!mci_pdev) {
  436. edac_dbg(0, "i3000 pci_get_device fail\n");
  437. pci_rc = -ENODEV;
  438. goto fail1;
  439. }
  440. pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
  441. if (pci_rc < 0) {
  442. edac_dbg(0, "i3000 init fail\n");
  443. pci_rc = -ENODEV;
  444. goto fail1;
  445. }
  446. }
  447. return 0;
  448. fail1:
  449. pci_unregister_driver(&i3000_driver);
  450. fail0:
  451. pci_dev_put(mci_pdev);
  452. return pci_rc;
  453. }
  454. static void __exit i3000_exit(void)
  455. {
  456. edac_dbg(3, "MC:\n");
  457. pci_unregister_driver(&i3000_driver);
  458. if (!i3000_registered) {
  459. i3000_remove_one(mci_pdev);
  460. pci_dev_put(mci_pdev);
  461. }
  462. }
  463. module_init(i3000_init);
  464. module_exit(i3000_exit);
  465. MODULE_LICENSE("GPL");
  466. MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
  467. MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
  468. module_param(edac_op_state, int, 0444);
  469. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");