i10nm_base.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Driver for Intel(R) 10nm server memory controller.
  4. * Copyright (c) 2019, Intel Corporation.
  5. *
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/io.h>
  9. #include <asm/cpu_device_id.h>
  10. #include <asm/intel-family.h>
  11. #include <asm/mce.h>
  12. #include "edac_module.h"
  13. #include "skx_common.h"
  14. #define I10NM_REVISION "v0.0.3"
  15. #define EDAC_MOD_STR "i10nm_edac"
  16. /* Debug macros */
  17. #define i10nm_printk(level, fmt, arg...) \
  18. edac_printk(level, "i10nm", fmt, ##arg)
  19. #define I10NM_GET_SCK_BAR(d, reg) \
  20. pci_read_config_dword((d)->uracu, 0xd0, &(reg))
  21. #define I10NM_GET_IMC_BAR(d, i, reg) \
  22. pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
  23. #define I10NM_GET_DIMMMTR(m, i, j) \
  24. readl((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4)
  25. #define I10NM_GET_MCDDRTCFG(m, i) \
  26. readl((m)->mbase + 0x20970 + (i) * 0x4000)
  27. #define I10NM_GET_MCMTR(m, i) \
  28. readl((m)->mbase + 0x20ef8 + (i) * 0x4000)
  29. #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
  30. #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
  31. #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
  32. GET_BITFIELD(reg, 0, 10) + 1) << 12)
  33. static struct list_head *i10nm_edac_list;
  34. static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
  35. unsigned int dev, unsigned int fun)
  36. {
  37. struct pci_dev *pdev;
  38. pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
  39. if (!pdev) {
  40. edac_dbg(2, "No device %02x:%02x.%x\n",
  41. bus, dev, fun);
  42. return NULL;
  43. }
  44. if (unlikely(pci_enable_device(pdev) < 0)) {
  45. edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
  46. bus, dev, fun);
  47. return NULL;
  48. }
  49. pci_dev_get(pdev);
  50. return pdev;
  51. }
  52. static int i10nm_get_all_munits(void)
  53. {
  54. struct pci_dev *mdev;
  55. void __iomem *mbase;
  56. unsigned long size;
  57. struct skx_dev *d;
  58. int i, j = 0;
  59. u32 reg, off;
  60. u64 base;
  61. list_for_each_entry(d, i10nm_edac_list, list) {
  62. d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
  63. if (!d->util_all)
  64. return -ENODEV;
  65. d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
  66. if (!d->uracu)
  67. return -ENODEV;
  68. if (I10NM_GET_SCK_BAR(d, reg)) {
  69. i10nm_printk(KERN_ERR, "Failed to socket bar\n");
  70. return -ENODEV;
  71. }
  72. base = I10NM_GET_SCK_MMIO_BASE(reg);
  73. edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
  74. j++, base, reg);
  75. for (i = 0; i < I10NM_NUM_IMC; i++) {
  76. mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
  77. 12 + i, 0);
  78. if (i == 0 && !mdev) {
  79. i10nm_printk(KERN_ERR, "No IMC found\n");
  80. return -ENODEV;
  81. }
  82. if (!mdev)
  83. continue;
  84. d->imc[i].mdev = mdev;
  85. if (I10NM_GET_IMC_BAR(d, i, reg)) {
  86. i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
  87. return -ENODEV;
  88. }
  89. off = I10NM_GET_IMC_MMIO_OFFSET(reg);
  90. size = I10NM_GET_IMC_MMIO_SIZE(reg);
  91. edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
  92. i, base + off, size, reg);
  93. mbase = ioremap(base + off, size);
  94. if (!mbase) {
  95. i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
  96. base + off);
  97. return -ENODEV;
  98. }
  99. d->imc[i].mbase = mbase;
  100. }
  101. }
  102. return 0;
  103. }
  104. static struct res_config i10nm_cfg0 = {
  105. .type = I10NM,
  106. .decs_did = 0x3452,
  107. .busno_cfg_offset = 0xcc,
  108. };
  109. static struct res_config i10nm_cfg1 = {
  110. .type = I10NM,
  111. .decs_did = 0x3452,
  112. .busno_cfg_offset = 0xd0,
  113. };
  114. static const struct x86_cpu_id i10nm_cpuids[] = {
  115. X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
  116. X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
  117. X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
  118. X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
  119. X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
  120. {}
  121. };
  122. MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
  123. static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
  124. {
  125. u32 mcmtr;
  126. mcmtr = I10NM_GET_MCMTR(imc, chan);
  127. edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
  128. return !!GET_BITFIELD(mcmtr, 2, 2);
  129. }
  130. static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
  131. {
  132. struct skx_pvt *pvt = mci->pvt_info;
  133. struct skx_imc *imc = pvt->imc;
  134. struct dimm_info *dimm;
  135. u32 mtr, mcddrtcfg;
  136. int i, j, ndimms;
  137. for (i = 0; i < I10NM_NUM_CHANNELS; i++) {
  138. if (!imc->mbase)
  139. continue;
  140. ndimms = 0;
  141. mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
  142. for (j = 0; j < I10NM_NUM_DIMMS; j++) {
  143. dimm = edac_get_dimm(mci, i, j, 0);
  144. mtr = I10NM_GET_DIMMMTR(imc, i, j);
  145. edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
  146. mtr, mcddrtcfg, imc->mc, i, j);
  147. if (IS_DIMM_PRESENT(mtr))
  148. ndimms += skx_get_dimm_info(mtr, 0, 0, dimm,
  149. imc, i, j);
  150. else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
  151. ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
  152. EDAC_MOD_STR);
  153. }
  154. if (ndimms && !i10nm_check_ecc(imc, i)) {
  155. i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
  156. imc->mc, i);
  157. return -ENODEV;
  158. }
  159. }
  160. return 0;
  161. }
  162. static struct notifier_block i10nm_mce_dec = {
  163. .notifier_call = skx_mce_check_error,
  164. .priority = MCE_PRIO_EDAC,
  165. };
  166. #ifdef CONFIG_EDAC_DEBUG
  167. /*
  168. * Debug feature.
  169. * Exercise the address decode logic by writing an address to
  170. * /sys/kernel/debug/edac/i10nm_test/addr.
  171. */
  172. static struct dentry *i10nm_test;
  173. static int debugfs_u64_set(void *data, u64 val)
  174. {
  175. struct mce m;
  176. pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
  177. memset(&m, 0, sizeof(m));
  178. /* ADDRV + MemRd + Unknown channel */
  179. m.status = MCI_STATUS_ADDRV + 0x90;
  180. /* One corrected error */
  181. m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
  182. m.addr = val;
  183. skx_mce_check_error(NULL, 0, &m);
  184. return 0;
  185. }
  186. DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
  187. static void setup_i10nm_debug(void)
  188. {
  189. i10nm_test = edac_debugfs_create_dir("i10nm_test");
  190. if (!i10nm_test)
  191. return;
  192. if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
  193. NULL, &fops_u64_wo)) {
  194. debugfs_remove(i10nm_test);
  195. i10nm_test = NULL;
  196. }
  197. }
  198. static void teardown_i10nm_debug(void)
  199. {
  200. debugfs_remove_recursive(i10nm_test);
  201. }
  202. #else
  203. static inline void setup_i10nm_debug(void) {}
  204. static inline void teardown_i10nm_debug(void) {}
  205. #endif /*CONFIG_EDAC_DEBUG*/
  206. static int __init i10nm_init(void)
  207. {
  208. u8 mc = 0, src_id = 0, node_id = 0;
  209. const struct x86_cpu_id *id;
  210. struct res_config *cfg;
  211. const char *owner;
  212. struct skx_dev *d;
  213. int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
  214. u64 tolm, tohm;
  215. edac_dbg(2, "\n");
  216. owner = edac_get_owner();
  217. if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
  218. return -EBUSY;
  219. if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
  220. return -ENODEV;
  221. id = x86_match_cpu(i10nm_cpuids);
  222. if (!id)
  223. return -ENODEV;
  224. cfg = (struct res_config *)id->driver_data;
  225. rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
  226. if (rc)
  227. return rc;
  228. rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
  229. if (rc < 0)
  230. goto fail;
  231. if (rc == 0) {
  232. i10nm_printk(KERN_ERR, "No memory controllers found\n");
  233. return -ENODEV;
  234. }
  235. rc = i10nm_get_all_munits();
  236. if (rc < 0)
  237. goto fail;
  238. list_for_each_entry(d, i10nm_edac_list, list) {
  239. rc = skx_get_src_id(d, 0xf8, &src_id);
  240. if (rc < 0)
  241. goto fail;
  242. rc = skx_get_node_id(d, &node_id);
  243. if (rc < 0)
  244. goto fail;
  245. edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
  246. for (i = 0; i < I10NM_NUM_IMC; i++) {
  247. if (!d->imc[i].mdev)
  248. continue;
  249. d->imc[i].mc = mc++;
  250. d->imc[i].lmc = i;
  251. d->imc[i].src_id = src_id;
  252. d->imc[i].node_id = node_id;
  253. rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
  254. "Intel_10nm Socket", EDAC_MOD_STR,
  255. i10nm_get_dimm_config);
  256. if (rc < 0)
  257. goto fail;
  258. }
  259. }
  260. rc = skx_adxl_get();
  261. if (rc)
  262. goto fail;
  263. opstate_init();
  264. mce_register_decode_chain(&i10nm_mce_dec);
  265. setup_i10nm_debug();
  266. i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
  267. return 0;
  268. fail:
  269. skx_remove();
  270. return rc;
  271. }
  272. static void __exit i10nm_exit(void)
  273. {
  274. edac_dbg(2, "\n");
  275. teardown_i10nm_debug();
  276. mce_unregister_decode_chain(&i10nm_mce_dec);
  277. skx_adxl_put();
  278. skx_remove();
  279. }
  280. module_init(i10nm_init);
  281. module_exit(i10nm_exit);
  282. MODULE_LICENSE("GPL v2");
  283. MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");