highbank_mc_edac.c 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright 2011-2012 Calxeda, Inc.
  4. */
  5. #include <linux/types.h>
  6. #include <linux/kernel.h>
  7. #include <linux/ctype.h>
  8. #include <linux/edac.h>
  9. #include <linux/interrupt.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/of_platform.h>
  12. #include <linux/uaccess.h>
  13. #include "edac_module.h"
  14. /* DDR Ctrlr Error Registers */
  15. #define HB_DDR_ECC_ERR_BASE 0x128
  16. #define MW_DDR_ECC_ERR_BASE 0x1b4
  17. #define HB_DDR_ECC_OPT 0x00
  18. #define HB_DDR_ECC_U_ERR_ADDR 0x08
  19. #define HB_DDR_ECC_U_ERR_STAT 0x0c
  20. #define HB_DDR_ECC_U_ERR_DATAL 0x10
  21. #define HB_DDR_ECC_U_ERR_DATAH 0x14
  22. #define HB_DDR_ECC_C_ERR_ADDR 0x18
  23. #define HB_DDR_ECC_C_ERR_STAT 0x1c
  24. #define HB_DDR_ECC_C_ERR_DATAL 0x20
  25. #define HB_DDR_ECC_C_ERR_DATAH 0x24
  26. #define HB_DDR_ECC_OPT_MODE_MASK 0x3
  27. #define HB_DDR_ECC_OPT_FWC 0x100
  28. #define HB_DDR_ECC_OPT_XOR_SHIFT 16
  29. /* DDR Ctrlr Interrupt Registers */
  30. #define HB_DDR_ECC_INT_BASE 0x180
  31. #define MW_DDR_ECC_INT_BASE 0x218
  32. #define HB_DDR_ECC_INT_STATUS 0x00
  33. #define HB_DDR_ECC_INT_ACK 0x04
  34. #define HB_DDR_ECC_INT_STAT_CE 0x8
  35. #define HB_DDR_ECC_INT_STAT_DOUBLE_CE 0x10
  36. #define HB_DDR_ECC_INT_STAT_UE 0x20
  37. #define HB_DDR_ECC_INT_STAT_DOUBLE_UE 0x40
  38. struct hb_mc_drvdata {
  39. void __iomem *mc_err_base;
  40. void __iomem *mc_int_base;
  41. };
  42. static irqreturn_t highbank_mc_err_handler(int irq, void *dev_id)
  43. {
  44. struct mem_ctl_info *mci = dev_id;
  45. struct hb_mc_drvdata *drvdata = mci->pvt_info;
  46. u32 status, err_addr;
  47. /* Read the interrupt status register */
  48. status = readl(drvdata->mc_int_base + HB_DDR_ECC_INT_STATUS);
  49. if (status & HB_DDR_ECC_INT_STAT_UE) {
  50. err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_U_ERR_ADDR);
  51. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  52. err_addr >> PAGE_SHIFT,
  53. err_addr & ~PAGE_MASK, 0,
  54. 0, 0, -1,
  55. mci->ctl_name, "");
  56. }
  57. if (status & HB_DDR_ECC_INT_STAT_CE) {
  58. u32 syndrome = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_STAT);
  59. syndrome = (syndrome >> 8) & 0xff;
  60. err_addr = readl(drvdata->mc_err_base + HB_DDR_ECC_C_ERR_ADDR);
  61. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  62. err_addr >> PAGE_SHIFT,
  63. err_addr & ~PAGE_MASK, syndrome,
  64. 0, 0, -1,
  65. mci->ctl_name, "");
  66. }
  67. /* clear the error, clears the interrupt */
  68. writel(status, drvdata->mc_int_base + HB_DDR_ECC_INT_ACK);
  69. return IRQ_HANDLED;
  70. }
  71. static void highbank_mc_err_inject(struct mem_ctl_info *mci, u8 synd)
  72. {
  73. struct hb_mc_drvdata *pdata = mci->pvt_info;
  74. u32 reg;
  75. reg = readl(pdata->mc_err_base + HB_DDR_ECC_OPT);
  76. reg &= HB_DDR_ECC_OPT_MODE_MASK;
  77. reg |= (synd << HB_DDR_ECC_OPT_XOR_SHIFT) | HB_DDR_ECC_OPT_FWC;
  78. writel(reg, pdata->mc_err_base + HB_DDR_ECC_OPT);
  79. }
  80. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  81. static ssize_t highbank_mc_inject_ctrl(struct device *dev,
  82. struct device_attribute *attr, const char *buf, size_t count)
  83. {
  84. struct mem_ctl_info *mci = to_mci(dev);
  85. u8 synd;
  86. if (kstrtou8(buf, 16, &synd))
  87. return -EINVAL;
  88. highbank_mc_err_inject(mci, synd);
  89. return count;
  90. }
  91. static DEVICE_ATTR(inject_ctrl, S_IWUSR, NULL, highbank_mc_inject_ctrl);
  92. static struct attribute *highbank_dev_attrs[] = {
  93. &dev_attr_inject_ctrl.attr,
  94. NULL
  95. };
  96. ATTRIBUTE_GROUPS(highbank_dev);
  97. struct hb_mc_settings {
  98. int err_offset;
  99. int int_offset;
  100. };
  101. static struct hb_mc_settings hb_settings = {
  102. .err_offset = HB_DDR_ECC_ERR_BASE,
  103. .int_offset = HB_DDR_ECC_INT_BASE,
  104. };
  105. static struct hb_mc_settings mw_settings = {
  106. .err_offset = MW_DDR_ECC_ERR_BASE,
  107. .int_offset = MW_DDR_ECC_INT_BASE,
  108. };
  109. static const struct of_device_id hb_ddr_ctrl_of_match[] = {
  110. { .compatible = "calxeda,hb-ddr-ctrl", .data = &hb_settings },
  111. { .compatible = "calxeda,ecx-2000-ddr-ctrl", .data = &mw_settings },
  112. {},
  113. };
  114. MODULE_DEVICE_TABLE(of, hb_ddr_ctrl_of_match);
  115. static int highbank_mc_probe(struct platform_device *pdev)
  116. {
  117. const struct of_device_id *id;
  118. const struct hb_mc_settings *settings;
  119. struct edac_mc_layer layers[2];
  120. struct mem_ctl_info *mci;
  121. struct hb_mc_drvdata *drvdata;
  122. struct dimm_info *dimm;
  123. struct resource *r;
  124. void __iomem *base;
  125. u32 control;
  126. int irq;
  127. int res = 0;
  128. id = of_match_device(hb_ddr_ctrl_of_match, &pdev->dev);
  129. if (!id)
  130. return -ENODEV;
  131. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  132. layers[0].size = 1;
  133. layers[0].is_virt_csrow = true;
  134. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  135. layers[1].size = 1;
  136. layers[1].is_virt_csrow = false;
  137. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
  138. sizeof(struct hb_mc_drvdata));
  139. if (!mci)
  140. return -ENOMEM;
  141. mci->pdev = &pdev->dev;
  142. drvdata = mci->pvt_info;
  143. platform_set_drvdata(pdev, mci);
  144. if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
  145. return -ENOMEM;
  146. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  147. if (!r) {
  148. dev_err(&pdev->dev, "Unable to get mem resource\n");
  149. res = -ENODEV;
  150. goto err;
  151. }
  152. if (!devm_request_mem_region(&pdev->dev, r->start,
  153. resource_size(r), dev_name(&pdev->dev))) {
  154. dev_err(&pdev->dev, "Error while requesting mem region\n");
  155. res = -EBUSY;
  156. goto err;
  157. }
  158. base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  159. if (!base) {
  160. dev_err(&pdev->dev, "Unable to map regs\n");
  161. res = -ENOMEM;
  162. goto err;
  163. }
  164. settings = id->data;
  165. drvdata->mc_err_base = base + settings->err_offset;
  166. drvdata->mc_int_base = base + settings->int_offset;
  167. control = readl(drvdata->mc_err_base + HB_DDR_ECC_OPT) & 0x3;
  168. if (!control || (control == 0x2)) {
  169. dev_err(&pdev->dev, "No ECC present, or ECC disabled\n");
  170. res = -ENODEV;
  171. goto err;
  172. }
  173. mci->mtype_cap = MEM_FLAG_DDR3;
  174. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
  175. mci->edac_cap = EDAC_FLAG_SECDED;
  176. mci->mod_name = pdev->dev.driver->name;
  177. mci->ctl_name = id->compatible;
  178. mci->dev_name = dev_name(&pdev->dev);
  179. mci->scrub_mode = SCRUB_SW_SRC;
  180. /* Only a single 4GB DIMM is supported */
  181. dimm = *mci->dimms;
  182. dimm->nr_pages = (~0UL >> PAGE_SHIFT) + 1;
  183. dimm->grain = 8;
  184. dimm->dtype = DEV_X8;
  185. dimm->mtype = MEM_DDR3;
  186. dimm->edac_mode = EDAC_SECDED;
  187. res = edac_mc_add_mc_with_groups(mci, highbank_dev_groups);
  188. if (res < 0)
  189. goto err;
  190. irq = platform_get_irq(pdev, 0);
  191. res = devm_request_irq(&pdev->dev, irq, highbank_mc_err_handler,
  192. 0, dev_name(&pdev->dev), mci);
  193. if (res < 0) {
  194. dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
  195. goto err2;
  196. }
  197. devres_close_group(&pdev->dev, NULL);
  198. return 0;
  199. err2:
  200. edac_mc_del_mc(&pdev->dev);
  201. err:
  202. devres_release_group(&pdev->dev, NULL);
  203. edac_mc_free(mci);
  204. return res;
  205. }
  206. static int highbank_mc_remove(struct platform_device *pdev)
  207. {
  208. struct mem_ctl_info *mci = platform_get_drvdata(pdev);
  209. edac_mc_del_mc(&pdev->dev);
  210. edac_mc_free(mci);
  211. return 0;
  212. }
  213. static struct platform_driver highbank_mc_edac_driver = {
  214. .probe = highbank_mc_probe,
  215. .remove = highbank_mc_remove,
  216. .driver = {
  217. .name = "hb_mc_edac",
  218. .of_match_table = hb_ddr_ctrl_of_match,
  219. },
  220. };
  221. module_platform_driver(highbank_mc_edac_driver);
  222. MODULE_LICENSE("GPL v2");
  223. MODULE_AUTHOR("Calxeda, Inc.");
  224. MODULE_DESCRIPTION("EDAC Driver for Calxeda Highbank");