fsl_ddr_edac.c 16 KB

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  1. /*
  2. * Freescale Memory Controller kernel module
  3. *
  4. * Support Power-based SoCs including MPC85xx, MPC86xx, MPC83xx and
  5. * ARM-based Layerscape SoCs including LS2xxx and LS1021A. Originally
  6. * split out from mpc85xx_edac EDAC driver.
  7. *
  8. * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc.
  9. *
  10. * Author: Dave Jiang <djiang@mvista.com>
  11. *
  12. * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under
  13. * the terms of the GNU General Public License version 2. This program
  14. * is licensed "as is" without any warranty of any kind, whether express
  15. * or implied.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ctype.h>
  21. #include <linux/io.h>
  22. #include <linux/mod_devicetable.h>
  23. #include <linux/edac.h>
  24. #include <linux/smp.h>
  25. #include <linux/gfp.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/of_device.h>
  28. #include <linux/of_address.h>
  29. #include "edac_module.h"
  30. #include "fsl_ddr_edac.h"
  31. #define EDAC_MOD_STR "fsl_ddr_edac"
  32. static int edac_mc_idx;
  33. static u32 orig_ddr_err_disable;
  34. static u32 orig_ddr_err_sbe;
  35. static bool little_endian;
  36. static inline u32 ddr_in32(void __iomem *addr)
  37. {
  38. return little_endian ? ioread32(addr) : ioread32be(addr);
  39. }
  40. static inline void ddr_out32(void __iomem *addr, u32 value)
  41. {
  42. if (little_endian)
  43. iowrite32(value, addr);
  44. else
  45. iowrite32be(value, addr);
  46. }
  47. #ifdef CONFIG_EDAC_DEBUG
  48. /************************ MC SYSFS parts ***********************************/
  49. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  50. static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
  51. struct device_attribute *mattr,
  52. char *data)
  53. {
  54. struct mem_ctl_info *mci = to_mci(dev);
  55. struct fsl_mc_pdata *pdata = mci->pvt_info;
  56. return sprintf(data, "0x%08x",
  57. ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI));
  58. }
  59. static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
  60. struct device_attribute *mattr,
  61. char *data)
  62. {
  63. struct mem_ctl_info *mci = to_mci(dev);
  64. struct fsl_mc_pdata *pdata = mci->pvt_info;
  65. return sprintf(data, "0x%08x",
  66. ddr_in32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO));
  67. }
  68. static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
  69. struct device_attribute *mattr,
  70. char *data)
  71. {
  72. struct mem_ctl_info *mci = to_mci(dev);
  73. struct fsl_mc_pdata *pdata = mci->pvt_info;
  74. return sprintf(data, "0x%08x",
  75. ddr_in32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
  76. }
  77. static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
  78. struct device_attribute *mattr,
  79. const char *data, size_t count)
  80. {
  81. struct mem_ctl_info *mci = to_mci(dev);
  82. struct fsl_mc_pdata *pdata = mci->pvt_info;
  83. unsigned long val;
  84. int rc;
  85. if (isdigit(*data)) {
  86. rc = kstrtoul(data, 0, &val);
  87. if (rc)
  88. return rc;
  89. ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI, val);
  90. return count;
  91. }
  92. return 0;
  93. }
  94. static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
  95. struct device_attribute *mattr,
  96. const char *data, size_t count)
  97. {
  98. struct mem_ctl_info *mci = to_mci(dev);
  99. struct fsl_mc_pdata *pdata = mci->pvt_info;
  100. unsigned long val;
  101. int rc;
  102. if (isdigit(*data)) {
  103. rc = kstrtoul(data, 0, &val);
  104. if (rc)
  105. return rc;
  106. ddr_out32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO, val);
  107. return count;
  108. }
  109. return 0;
  110. }
  111. static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
  112. struct device_attribute *mattr,
  113. const char *data, size_t count)
  114. {
  115. struct mem_ctl_info *mci = to_mci(dev);
  116. struct fsl_mc_pdata *pdata = mci->pvt_info;
  117. unsigned long val;
  118. int rc;
  119. if (isdigit(*data)) {
  120. rc = kstrtoul(data, 0, &val);
  121. if (rc)
  122. return rc;
  123. ddr_out32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT, val);
  124. return count;
  125. }
  126. return 0;
  127. }
  128. static DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
  129. fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
  130. static DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
  131. fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
  132. static DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
  133. fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
  134. #endif /* CONFIG_EDAC_DEBUG */
  135. static struct attribute *fsl_ddr_dev_attrs[] = {
  136. #ifdef CONFIG_EDAC_DEBUG
  137. &dev_attr_inject_data_hi.attr,
  138. &dev_attr_inject_data_lo.attr,
  139. &dev_attr_inject_ctrl.attr,
  140. #endif
  141. NULL
  142. };
  143. ATTRIBUTE_GROUPS(fsl_ddr_dev);
  144. /**************************** MC Err device ***************************/
  145. /*
  146. * Taken from table 8-55 in the MPC8641 User's Manual and/or 9-61 in the
  147. * MPC8572 User's Manual. Each line represents a syndrome bit column as a
  148. * 64-bit value, but split into an upper and lower 32-bit chunk. The labels
  149. * below correspond to Freescale's manuals.
  150. */
  151. static unsigned int ecc_table[16] = {
  152. /* MSB LSB */
  153. /* [0:31] [32:63] */
  154. 0xf00fe11e, 0xc33c0ff7, /* Syndrome bit 7 */
  155. 0x00ff00ff, 0x00fff0ff,
  156. 0x0f0f0f0f, 0x0f0fff00,
  157. 0x11113333, 0x7777000f,
  158. 0x22224444, 0x8888222f,
  159. 0x44448888, 0xffff4441,
  160. 0x8888ffff, 0x11118882,
  161. 0xffff1111, 0x22221114, /* Syndrome bit 0 */
  162. };
  163. /*
  164. * Calculate the correct ECC value for a 64-bit value specified by high:low
  165. */
  166. static u8 calculate_ecc(u32 high, u32 low)
  167. {
  168. u32 mask_low;
  169. u32 mask_high;
  170. int bit_cnt;
  171. u8 ecc = 0;
  172. int i;
  173. int j;
  174. for (i = 0; i < 8; i++) {
  175. mask_high = ecc_table[i * 2];
  176. mask_low = ecc_table[i * 2 + 1];
  177. bit_cnt = 0;
  178. for (j = 0; j < 32; j++) {
  179. if ((mask_high >> j) & 1)
  180. bit_cnt ^= (high >> j) & 1;
  181. if ((mask_low >> j) & 1)
  182. bit_cnt ^= (low >> j) & 1;
  183. }
  184. ecc |= bit_cnt << i;
  185. }
  186. return ecc;
  187. }
  188. /*
  189. * Create the syndrome code which is generated if the data line specified by
  190. * 'bit' failed. Eg generate an 8-bit codes seen in Table 8-55 in the MPC8641
  191. * User's Manual and 9-61 in the MPC8572 User's Manual.
  192. */
  193. static u8 syndrome_from_bit(unsigned int bit) {
  194. int i;
  195. u8 syndrome = 0;
  196. /*
  197. * Cycle through the upper or lower 32-bit portion of each value in
  198. * ecc_table depending on if 'bit' is in the upper or lower half of
  199. * 64-bit data.
  200. */
  201. for (i = bit < 32; i < 16; i += 2)
  202. syndrome |= ((ecc_table[i] >> (bit % 32)) & 1) << (i / 2);
  203. return syndrome;
  204. }
  205. /*
  206. * Decode data and ecc syndrome to determine what went wrong
  207. * Note: This can only decode single-bit errors
  208. */
  209. static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
  210. int *bad_data_bit, int *bad_ecc_bit)
  211. {
  212. int i;
  213. u8 syndrome;
  214. *bad_data_bit = -1;
  215. *bad_ecc_bit = -1;
  216. /*
  217. * Calculate the ECC of the captured data and XOR it with the captured
  218. * ECC to find an ECC syndrome value we can search for
  219. */
  220. syndrome = calculate_ecc(cap_high, cap_low) ^ cap_ecc;
  221. /* Check if a data line is stuck... */
  222. for (i = 0; i < 64; i++) {
  223. if (syndrome == syndrome_from_bit(i)) {
  224. *bad_data_bit = i;
  225. return;
  226. }
  227. }
  228. /* If data is correct, check ECC bits for errors... */
  229. for (i = 0; i < 8; i++) {
  230. if ((syndrome >> i) & 0x1) {
  231. *bad_ecc_bit = i;
  232. return;
  233. }
  234. }
  235. }
  236. #define make64(high, low) (((u64)(high) << 32) | (low))
  237. static void fsl_mc_check(struct mem_ctl_info *mci)
  238. {
  239. struct fsl_mc_pdata *pdata = mci->pvt_info;
  240. struct csrow_info *csrow;
  241. u32 bus_width;
  242. u32 err_detect;
  243. u32 syndrome;
  244. u64 err_addr;
  245. u32 pfn;
  246. int row_index;
  247. u32 cap_high;
  248. u32 cap_low;
  249. int bad_data_bit;
  250. int bad_ecc_bit;
  251. err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
  252. if (!err_detect)
  253. return;
  254. fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
  255. err_detect);
  256. /* no more processing if not ECC bit errors */
  257. if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
  258. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
  259. return;
  260. }
  261. syndrome = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
  262. /* Mask off appropriate bits of syndrome based on bus width */
  263. bus_width = (ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
  264. DSC_DBW_MASK) ? 32 : 64;
  265. if (bus_width == 64)
  266. syndrome &= 0xff;
  267. else
  268. syndrome &= 0xffff;
  269. err_addr = make64(
  270. ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
  271. ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
  272. pfn = err_addr >> PAGE_SHIFT;
  273. for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
  274. csrow = mci->csrows[row_index];
  275. if ((pfn >= csrow->first_page) && (pfn <= csrow->last_page))
  276. break;
  277. }
  278. cap_high = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
  279. cap_low = ddr_in32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
  280. /*
  281. * Analyze single-bit errors on 64-bit wide buses
  282. * TODO: Add support for 32-bit wide buses
  283. */
  284. if ((err_detect & DDR_EDE_SBE) && (bus_width == 64)) {
  285. sbe_ecc_decode(cap_high, cap_low, syndrome,
  286. &bad_data_bit, &bad_ecc_bit);
  287. if (bad_data_bit != -1)
  288. fsl_mc_printk(mci, KERN_ERR,
  289. "Faulty Data bit: %d\n", bad_data_bit);
  290. if (bad_ecc_bit != -1)
  291. fsl_mc_printk(mci, KERN_ERR,
  292. "Faulty ECC bit: %d\n", bad_ecc_bit);
  293. fsl_mc_printk(mci, KERN_ERR,
  294. "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
  295. cap_high ^ (1 << (bad_data_bit - 32)),
  296. cap_low ^ (1 << bad_data_bit),
  297. syndrome ^ (1 << bad_ecc_bit));
  298. }
  299. fsl_mc_printk(mci, KERN_ERR,
  300. "Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
  301. cap_high, cap_low, syndrome);
  302. fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
  303. fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
  304. /* we are out of range */
  305. if (row_index == mci->nr_csrows)
  306. fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
  307. if (err_detect & DDR_EDE_SBE)
  308. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  309. pfn, err_addr & ~PAGE_MASK, syndrome,
  310. row_index, 0, -1,
  311. mci->ctl_name, "");
  312. if (err_detect & DDR_EDE_MBE)
  313. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  314. pfn, err_addr & ~PAGE_MASK, syndrome,
  315. row_index, 0, -1,
  316. mci->ctl_name, "");
  317. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
  318. }
  319. static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
  320. {
  321. struct mem_ctl_info *mci = dev_id;
  322. struct fsl_mc_pdata *pdata = mci->pvt_info;
  323. u32 err_detect;
  324. err_detect = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
  325. if (!err_detect)
  326. return IRQ_NONE;
  327. fsl_mc_check(mci);
  328. return IRQ_HANDLED;
  329. }
  330. static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
  331. {
  332. struct fsl_mc_pdata *pdata = mci->pvt_info;
  333. struct csrow_info *csrow;
  334. struct dimm_info *dimm;
  335. u32 sdram_ctl;
  336. u32 sdtype;
  337. enum mem_type mtype;
  338. u32 cs_bnds;
  339. int index;
  340. sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
  341. sdtype = sdram_ctl & DSC_SDTYPE_MASK;
  342. if (sdram_ctl & DSC_RD_EN) {
  343. switch (sdtype) {
  344. case 0x02000000:
  345. mtype = MEM_RDDR;
  346. break;
  347. case 0x03000000:
  348. mtype = MEM_RDDR2;
  349. break;
  350. case 0x07000000:
  351. mtype = MEM_RDDR3;
  352. break;
  353. case 0x05000000:
  354. mtype = MEM_RDDR4;
  355. break;
  356. default:
  357. mtype = MEM_UNKNOWN;
  358. break;
  359. }
  360. } else {
  361. switch (sdtype) {
  362. case 0x02000000:
  363. mtype = MEM_DDR;
  364. break;
  365. case 0x03000000:
  366. mtype = MEM_DDR2;
  367. break;
  368. case 0x07000000:
  369. mtype = MEM_DDR3;
  370. break;
  371. case 0x05000000:
  372. mtype = MEM_DDR4;
  373. break;
  374. default:
  375. mtype = MEM_UNKNOWN;
  376. break;
  377. }
  378. }
  379. for (index = 0; index < mci->nr_csrows; index++) {
  380. u32 start;
  381. u32 end;
  382. csrow = mci->csrows[index];
  383. dimm = csrow->channels[0]->dimm;
  384. cs_bnds = ddr_in32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
  385. (index * FSL_MC_CS_BNDS_OFS));
  386. start = (cs_bnds & 0xffff0000) >> 16;
  387. end = (cs_bnds & 0x0000ffff);
  388. if (start == end)
  389. continue; /* not populated */
  390. start <<= (24 - PAGE_SHIFT);
  391. end <<= (24 - PAGE_SHIFT);
  392. end |= (1 << (24 - PAGE_SHIFT)) - 1;
  393. csrow->first_page = start;
  394. csrow->last_page = end;
  395. dimm->nr_pages = end + 1 - start;
  396. dimm->grain = 8;
  397. dimm->mtype = mtype;
  398. dimm->dtype = DEV_UNKNOWN;
  399. if (sdram_ctl & DSC_X32_EN)
  400. dimm->dtype = DEV_X32;
  401. dimm->edac_mode = EDAC_SECDED;
  402. }
  403. }
  404. int fsl_mc_err_probe(struct platform_device *op)
  405. {
  406. struct mem_ctl_info *mci;
  407. struct edac_mc_layer layers[2];
  408. struct fsl_mc_pdata *pdata;
  409. struct resource r;
  410. u32 sdram_ctl;
  411. int res;
  412. if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
  413. return -ENOMEM;
  414. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  415. layers[0].size = 4;
  416. layers[0].is_virt_csrow = true;
  417. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  418. layers[1].size = 1;
  419. layers[1].is_virt_csrow = false;
  420. mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
  421. sizeof(*pdata));
  422. if (!mci) {
  423. devres_release_group(&op->dev, fsl_mc_err_probe);
  424. return -ENOMEM;
  425. }
  426. pdata = mci->pvt_info;
  427. pdata->name = "fsl_mc_err";
  428. mci->pdev = &op->dev;
  429. pdata->edac_idx = edac_mc_idx++;
  430. dev_set_drvdata(mci->pdev, mci);
  431. mci->ctl_name = pdata->name;
  432. mci->dev_name = pdata->name;
  433. /*
  434. * Get the endianness of DDR controller registers.
  435. * Default is big endian.
  436. */
  437. little_endian = of_property_read_bool(op->dev.of_node, "little-endian");
  438. res = of_address_to_resource(op->dev.of_node, 0, &r);
  439. if (res) {
  440. pr_err("%s: Unable to get resource for MC err regs\n",
  441. __func__);
  442. goto err;
  443. }
  444. if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r),
  445. pdata->name)) {
  446. pr_err("%s: Error while requesting mem region\n",
  447. __func__);
  448. res = -EBUSY;
  449. goto err;
  450. }
  451. pdata->mc_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r));
  452. if (!pdata->mc_vbase) {
  453. pr_err("%s: Unable to setup MC err regs\n", __func__);
  454. res = -ENOMEM;
  455. goto err;
  456. }
  457. sdram_ctl = ddr_in32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
  458. if (!(sdram_ctl & DSC_ECC_EN)) {
  459. /* no ECC */
  460. pr_warn("%s: No ECC DIMMs discovered\n", __func__);
  461. res = -ENODEV;
  462. goto err;
  463. }
  464. edac_dbg(3, "init mci\n");
  465. mci->mtype_cap = MEM_FLAG_DDR | MEM_FLAG_RDDR |
  466. MEM_FLAG_DDR2 | MEM_FLAG_RDDR2 |
  467. MEM_FLAG_DDR3 | MEM_FLAG_RDDR3 |
  468. MEM_FLAG_DDR4 | MEM_FLAG_RDDR4;
  469. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
  470. mci->edac_cap = EDAC_FLAG_SECDED;
  471. mci->mod_name = EDAC_MOD_STR;
  472. if (edac_op_state == EDAC_OPSTATE_POLL)
  473. mci->edac_check = fsl_mc_check;
  474. mci->ctl_page_to_phys = NULL;
  475. mci->scrub_mode = SCRUB_SW_SRC;
  476. fsl_ddr_init_csrows(mci);
  477. /* store the original error disable bits */
  478. orig_ddr_err_disable = ddr_in32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
  479. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
  480. /* clear all error bits */
  481. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
  482. res = edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups);
  483. if (res) {
  484. edac_dbg(3, "failed edac_mc_add_mc()\n");
  485. goto err;
  486. }
  487. if (edac_op_state == EDAC_OPSTATE_INT) {
  488. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
  489. DDR_EIE_MBEE | DDR_EIE_SBEE);
  490. /* store the original error management threshold */
  491. orig_ddr_err_sbe = ddr_in32(pdata->mc_vbase +
  492. FSL_MC_ERR_SBE) & 0xff0000;
  493. /* set threshold to 1 error per interrupt */
  494. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
  495. /* register interrupts */
  496. pdata->irq = platform_get_irq(op, 0);
  497. res = devm_request_irq(&op->dev, pdata->irq,
  498. fsl_mc_isr,
  499. IRQF_SHARED,
  500. "[EDAC] MC err", mci);
  501. if (res < 0) {
  502. pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
  503. __func__, pdata->irq);
  504. res = -ENODEV;
  505. goto err2;
  506. }
  507. pr_info(EDAC_MOD_STR " acquired irq %d for MC\n",
  508. pdata->irq);
  509. }
  510. devres_remove_group(&op->dev, fsl_mc_err_probe);
  511. edac_dbg(3, "success\n");
  512. pr_info(EDAC_MOD_STR " MC err registered\n");
  513. return 0;
  514. err2:
  515. edac_mc_del_mc(&op->dev);
  516. err:
  517. devres_release_group(&op->dev, fsl_mc_err_probe);
  518. edac_mc_free(mci);
  519. return res;
  520. }
  521. int fsl_mc_err_remove(struct platform_device *op)
  522. {
  523. struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
  524. struct fsl_mc_pdata *pdata = mci->pvt_info;
  525. edac_dbg(0, "\n");
  526. if (edac_op_state == EDAC_OPSTATE_INT) {
  527. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
  528. }
  529. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
  530. orig_ddr_err_disable);
  531. ddr_out32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
  532. edac_mc_del_mc(&op->dev);
  533. edac_mc_free(mci);
  534. return 0;
  535. }