e7xxx_edac.c 16 KB

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  1. /*
  2. * Intel e7xxx Memory Controller kernel module
  3. * (C) 2003 Linux Networx (http://lnxi.com)
  4. * This file may be distributed under the terms of the
  5. * GNU General Public License.
  6. *
  7. * See "enum e7xxx_chips" below for supported chipsets
  8. *
  9. * Written by Thayne Harbaugh
  10. * Based on work by Dan Hollis <goemon at anime dot net> and others.
  11. * http://www.anime.net/~goemon/linux-ecc/
  12. *
  13. * Datasheet:
  14. * http://www.intel.com/content/www/us/en/chipsets/e7501-chipset-memory-controller-hub-datasheet.html
  15. *
  16. * Contributors:
  17. * Eric Biederman (Linux Networx)
  18. * Tom Zimmerman (Linux Networx)
  19. * Jim Garlick (Lawrence Livermore National Labs)
  20. * Dave Peterson (Lawrence Livermore National Labs)
  21. * That One Guy (Some other place)
  22. * Wang Zhenyu (intel.com)
  23. *
  24. * $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
  25. *
  26. */
  27. #include <linux/module.h>
  28. #include <linux/init.h>
  29. #include <linux/pci.h>
  30. #include <linux/pci_ids.h>
  31. #include <linux/edac.h>
  32. #include "edac_module.h"
  33. #define EDAC_MOD_STR "e7xxx_edac"
  34. #define e7xxx_printk(level, fmt, arg...) \
  35. edac_printk(level, "e7xxx", fmt, ##arg)
  36. #define e7xxx_mc_printk(mci, level, fmt, arg...) \
  37. edac_mc_chipset_printk(mci, level, "e7xxx", fmt, ##arg)
  38. #ifndef PCI_DEVICE_ID_INTEL_7205_0
  39. #define PCI_DEVICE_ID_INTEL_7205_0 0x255d
  40. #endif /* PCI_DEVICE_ID_INTEL_7205_0 */
  41. #ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
  42. #define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
  43. #endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
  44. #ifndef PCI_DEVICE_ID_INTEL_7500_0
  45. #define PCI_DEVICE_ID_INTEL_7500_0 0x2540
  46. #endif /* PCI_DEVICE_ID_INTEL_7500_0 */
  47. #ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
  48. #define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
  49. #endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
  50. #ifndef PCI_DEVICE_ID_INTEL_7501_0
  51. #define PCI_DEVICE_ID_INTEL_7501_0 0x254c
  52. #endif /* PCI_DEVICE_ID_INTEL_7501_0 */
  53. #ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
  54. #define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
  55. #endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
  56. #ifndef PCI_DEVICE_ID_INTEL_7505_0
  57. #define PCI_DEVICE_ID_INTEL_7505_0 0x2550
  58. #endif /* PCI_DEVICE_ID_INTEL_7505_0 */
  59. #ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
  60. #define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
  61. #endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
  62. #define E7XXX_NR_CSROWS 8 /* number of csrows */
  63. #define E7XXX_NR_DIMMS 8 /* 2 channels, 4 dimms/channel */
  64. /* E7XXX register addresses - device 0 function 0 */
  65. #define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
  66. #define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
  67. /*
  68. * 31 Device width row 7 0=x8 1=x4
  69. * 27 Device width row 6
  70. * 23 Device width row 5
  71. * 19 Device width row 4
  72. * 15 Device width row 3
  73. * 11 Device width row 2
  74. * 7 Device width row 1
  75. * 3 Device width row 0
  76. */
  77. #define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
  78. /*
  79. * 22 Number channels 0=1,1=2
  80. * 19:18 DRB Granularity 32/64MB
  81. */
  82. #define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
  83. #define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
  84. #define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
  85. /* E7XXX register addresses - device 0 function 1 */
  86. #define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
  87. #define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
  88. #define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
  89. /* error address register (32b) */
  90. /*
  91. * 31:28 Reserved
  92. * 27:6 CE address (4k block 33:12)
  93. * 5:0 Reserved
  94. */
  95. #define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
  96. /* error address register (32b) */
  97. /*
  98. * 31:28 Reserved
  99. * 27:6 CE address (4k block 33:12)
  100. * 5:0 Reserved
  101. */
  102. #define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
  103. /* error syndrome register (16b) */
  104. enum e7xxx_chips {
  105. E7500 = 0,
  106. E7501,
  107. E7505,
  108. E7205,
  109. };
  110. struct e7xxx_pvt {
  111. struct pci_dev *bridge_ck;
  112. u32 tolm;
  113. u32 remapbase;
  114. u32 remaplimit;
  115. const struct e7xxx_dev_info *dev_info;
  116. };
  117. struct e7xxx_dev_info {
  118. u16 err_dev;
  119. const char *ctl_name;
  120. };
  121. struct e7xxx_error_info {
  122. u8 dram_ferr;
  123. u8 dram_nerr;
  124. u32 dram_celog_add;
  125. u16 dram_celog_syndrome;
  126. u32 dram_uelog_add;
  127. };
  128. static struct edac_pci_ctl_info *e7xxx_pci;
  129. static const struct e7xxx_dev_info e7xxx_devs[] = {
  130. [E7500] = {
  131. .err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
  132. .ctl_name = "E7500"},
  133. [E7501] = {
  134. .err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
  135. .ctl_name = "E7501"},
  136. [E7505] = {
  137. .err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
  138. .ctl_name = "E7505"},
  139. [E7205] = {
  140. .err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
  141. .ctl_name = "E7205"},
  142. };
  143. /* FIXME - is this valid for both SECDED and S4ECD4ED? */
  144. static inline int e7xxx_find_channel(u16 syndrome)
  145. {
  146. edac_dbg(3, "\n");
  147. if ((syndrome & 0xff00) == 0)
  148. return 0;
  149. if ((syndrome & 0x00ff) == 0)
  150. return 1;
  151. if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
  152. return 0;
  153. return 1;
  154. }
  155. static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci,
  156. unsigned long page)
  157. {
  158. u32 remap;
  159. struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
  160. edac_dbg(3, "\n");
  161. if ((page < pvt->tolm) ||
  162. ((page >= 0x100000) && (page < pvt->remapbase)))
  163. return page;
  164. remap = (page - pvt->tolm) + pvt->remapbase;
  165. if (remap < pvt->remaplimit)
  166. return remap;
  167. e7xxx_printk(KERN_ERR, "Invalid page %lx - out of range\n", page);
  168. return pvt->tolm - 1;
  169. }
  170. static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
  171. {
  172. u32 error_1b, page;
  173. u16 syndrome;
  174. int row;
  175. int channel;
  176. edac_dbg(3, "\n");
  177. /* read the error address */
  178. error_1b = info->dram_celog_add;
  179. /* FIXME - should use PAGE_SHIFT */
  180. page = error_1b >> 6; /* convert the address to 4k page */
  181. /* read the syndrome */
  182. syndrome = info->dram_celog_syndrome;
  183. /* FIXME - check for -1 */
  184. row = edac_mc_find_csrow_by_page(mci, page);
  185. /* convert syndrome to channel */
  186. channel = e7xxx_find_channel(syndrome);
  187. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, page, 0, syndrome,
  188. row, channel, -1, "e7xxx CE", "");
  189. }
  190. static void process_ce_no_info(struct mem_ctl_info *mci)
  191. {
  192. edac_dbg(3, "\n");
  193. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
  194. "e7xxx CE log register overflow", "");
  195. }
  196. static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
  197. {
  198. u32 error_2b, block_page;
  199. int row;
  200. edac_dbg(3, "\n");
  201. /* read the error address */
  202. error_2b = info->dram_uelog_add;
  203. /* FIXME - should use PAGE_SHIFT */
  204. block_page = error_2b >> 6; /* convert to 4k address */
  205. row = edac_mc_find_csrow_by_page(mci, block_page);
  206. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, block_page, 0, 0,
  207. row, -1, -1, "e7xxx UE", "");
  208. }
  209. static void process_ue_no_info(struct mem_ctl_info *mci)
  210. {
  211. edac_dbg(3, "\n");
  212. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, -1, -1, -1,
  213. "e7xxx UE log register overflow", "");
  214. }
  215. static void e7xxx_get_error_info(struct mem_ctl_info *mci,
  216. struct e7xxx_error_info *info)
  217. {
  218. struct e7xxx_pvt *pvt;
  219. pvt = (struct e7xxx_pvt *)mci->pvt_info;
  220. pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
  221. pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
  222. if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
  223. pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
  224. &info->dram_celog_add);
  225. pci_read_config_word(pvt->bridge_ck,
  226. E7XXX_DRAM_CELOG_SYNDROME,
  227. &info->dram_celog_syndrome);
  228. }
  229. if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
  230. pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
  231. &info->dram_uelog_add);
  232. if (info->dram_ferr & 3)
  233. pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
  234. if (info->dram_nerr & 3)
  235. pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
  236. }
  237. static int e7xxx_process_error_info(struct mem_ctl_info *mci,
  238. struct e7xxx_error_info *info,
  239. int handle_errors)
  240. {
  241. int error_found;
  242. error_found = 0;
  243. /* decode and report errors */
  244. if (info->dram_ferr & 1) { /* check first error correctable */
  245. error_found = 1;
  246. if (handle_errors)
  247. process_ce(mci, info);
  248. }
  249. if (info->dram_ferr & 2) { /* check first error uncorrectable */
  250. error_found = 1;
  251. if (handle_errors)
  252. process_ue(mci, info);
  253. }
  254. if (info->dram_nerr & 1) { /* check next error correctable */
  255. error_found = 1;
  256. if (handle_errors) {
  257. if (info->dram_ferr & 1)
  258. process_ce_no_info(mci);
  259. else
  260. process_ce(mci, info);
  261. }
  262. }
  263. if (info->dram_nerr & 2) { /* check next error uncorrectable */
  264. error_found = 1;
  265. if (handle_errors) {
  266. if (info->dram_ferr & 2)
  267. process_ue_no_info(mci);
  268. else
  269. process_ue(mci, info);
  270. }
  271. }
  272. return error_found;
  273. }
  274. static void e7xxx_check(struct mem_ctl_info *mci)
  275. {
  276. struct e7xxx_error_info info;
  277. edac_dbg(3, "\n");
  278. e7xxx_get_error_info(mci, &info);
  279. e7xxx_process_error_info(mci, &info, 1);
  280. }
  281. /* Return 1 if dual channel mode is active. Else return 0. */
  282. static inline int dual_channel_active(u32 drc, int dev_idx)
  283. {
  284. return (dev_idx == E7501) ? ((drc >> 22) & 0x1) : 1;
  285. }
  286. /* Return DRB granularity (0=32mb, 1=64mb). */
  287. static inline int drb_granularity(u32 drc, int dev_idx)
  288. {
  289. /* only e7501 can be single channel */
  290. return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
  291. }
  292. static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
  293. int dev_idx, u32 drc)
  294. {
  295. unsigned long last_cumul_size;
  296. int index, j;
  297. u8 value;
  298. u32 dra, cumul_size, nr_pages;
  299. int drc_chan, drc_drbg, drc_ddim, mem_dev;
  300. struct csrow_info *csrow;
  301. struct dimm_info *dimm;
  302. enum edac_type edac_mode;
  303. pci_read_config_dword(pdev, E7XXX_DRA, &dra);
  304. drc_chan = dual_channel_active(drc, dev_idx);
  305. drc_drbg = drb_granularity(drc, dev_idx);
  306. drc_ddim = (drc >> 20) & 0x3;
  307. last_cumul_size = 0;
  308. /* The dram row boundary (DRB) reg values are boundary address
  309. * for each DRAM row with a granularity of 32 or 64MB (single/dual
  310. * channel operation). DRB regs are cumulative; therefore DRB7 will
  311. * contain the total memory contained in all eight rows.
  312. */
  313. for (index = 0; index < mci->nr_csrows; index++) {
  314. /* mem_dev 0=x8, 1=x4 */
  315. mem_dev = (dra >> (index * 4 + 3)) & 0x1;
  316. csrow = mci->csrows[index];
  317. pci_read_config_byte(pdev, E7XXX_DRB + index, &value);
  318. /* convert a 64 or 32 MiB DRB to a page size. */
  319. cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
  320. edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size);
  321. if (cumul_size == last_cumul_size)
  322. continue; /* not populated */
  323. csrow->first_page = last_cumul_size;
  324. csrow->last_page = cumul_size - 1;
  325. nr_pages = cumul_size - last_cumul_size;
  326. last_cumul_size = cumul_size;
  327. /*
  328. * if single channel or x8 devices then SECDED
  329. * if dual channel and x4 then S4ECD4ED
  330. */
  331. if (drc_ddim) {
  332. if (drc_chan && mem_dev) {
  333. edac_mode = EDAC_S4ECD4ED;
  334. mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
  335. } else {
  336. edac_mode = EDAC_SECDED;
  337. mci->edac_cap |= EDAC_FLAG_SECDED;
  338. }
  339. } else
  340. edac_mode = EDAC_NONE;
  341. for (j = 0; j < drc_chan + 1; j++) {
  342. dimm = csrow->channels[j]->dimm;
  343. dimm->nr_pages = nr_pages / (drc_chan + 1);
  344. dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
  345. dimm->mtype = MEM_RDDR; /* only one type supported */
  346. dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
  347. dimm->edac_mode = edac_mode;
  348. }
  349. }
  350. }
  351. static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
  352. {
  353. u16 pci_data;
  354. struct mem_ctl_info *mci = NULL;
  355. struct edac_mc_layer layers[2];
  356. struct e7xxx_pvt *pvt = NULL;
  357. u32 drc;
  358. int drc_chan;
  359. struct e7xxx_error_info discard;
  360. edac_dbg(0, "mci\n");
  361. pci_read_config_dword(pdev, E7XXX_DRC, &drc);
  362. drc_chan = dual_channel_active(drc, dev_idx);
  363. /*
  364. * According with the datasheet, this device has a maximum of
  365. * 4 DIMMS per channel, either single-rank or dual-rank. So, the
  366. * total amount of dimms is 8 (E7XXX_NR_DIMMS).
  367. * That means that the DIMM is mapped as CSROWs, and the channel
  368. * will map the rank. So, an error to either channel should be
  369. * attributed to the same dimm.
  370. */
  371. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  372. layers[0].size = E7XXX_NR_CSROWS;
  373. layers[0].is_virt_csrow = true;
  374. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  375. layers[1].size = drc_chan + 1;
  376. layers[1].is_virt_csrow = false;
  377. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
  378. if (mci == NULL)
  379. return -ENOMEM;
  380. edac_dbg(3, "init mci\n");
  381. mci->mtype_cap = MEM_FLAG_RDDR;
  382. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED |
  383. EDAC_FLAG_S4ECD4ED;
  384. /* FIXME - what if different memory types are in different csrows? */
  385. mci->mod_name = EDAC_MOD_STR;
  386. mci->pdev = &pdev->dev;
  387. edac_dbg(3, "init pvt\n");
  388. pvt = (struct e7xxx_pvt *)mci->pvt_info;
  389. pvt->dev_info = &e7xxx_devs[dev_idx];
  390. pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
  391. pvt->dev_info->err_dev, pvt->bridge_ck);
  392. if (!pvt->bridge_ck) {
  393. e7xxx_printk(KERN_ERR, "error reporting device not found:"
  394. "vendor %x device 0x%x (broken BIOS?)\n",
  395. PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
  396. goto fail0;
  397. }
  398. edac_dbg(3, "more mci init\n");
  399. mci->ctl_name = pvt->dev_info->ctl_name;
  400. mci->dev_name = pci_name(pdev);
  401. mci->edac_check = e7xxx_check;
  402. mci->ctl_page_to_phys = ctl_page_to_phys;
  403. e7xxx_init_csrows(mci, pdev, dev_idx, drc);
  404. mci->edac_cap |= EDAC_FLAG_NONE;
  405. edac_dbg(3, "tolm, remapbase, remaplimit\n");
  406. /* load the top of low memory, remap base, and remap limit vars */
  407. pci_read_config_word(pdev, E7XXX_TOLM, &pci_data);
  408. pvt->tolm = ((u32) pci_data) << 4;
  409. pci_read_config_word(pdev, E7XXX_REMAPBASE, &pci_data);
  410. pvt->remapbase = ((u32) pci_data) << 14;
  411. pci_read_config_word(pdev, E7XXX_REMAPLIMIT, &pci_data);
  412. pvt->remaplimit = ((u32) pci_data) << 14;
  413. e7xxx_printk(KERN_INFO,
  414. "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
  415. pvt->remapbase, pvt->remaplimit);
  416. /* clear any pending errors, or initial state bits */
  417. e7xxx_get_error_info(mci, &discard);
  418. /* Here we assume that we will never see multiple instances of this
  419. * type of memory controller. The ID is therefore hardcoded to 0.
  420. */
  421. if (edac_mc_add_mc(mci)) {
  422. edac_dbg(3, "failed edac_mc_add_mc()\n");
  423. goto fail1;
  424. }
  425. /* allocating generic PCI control info */
  426. e7xxx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  427. if (!e7xxx_pci) {
  428. printk(KERN_WARNING
  429. "%s(): Unable to create PCI control\n",
  430. __func__);
  431. printk(KERN_WARNING
  432. "%s(): PCI error report via EDAC not setup\n",
  433. __func__);
  434. }
  435. /* get this far and it's successful */
  436. edac_dbg(3, "success\n");
  437. return 0;
  438. fail1:
  439. pci_dev_put(pvt->bridge_ck);
  440. fail0:
  441. edac_mc_free(mci);
  442. return -ENODEV;
  443. }
  444. /* returns count (>= 0), or negative on error */
  445. static int e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  446. {
  447. edac_dbg(0, "\n");
  448. /* wake up and enable device */
  449. return pci_enable_device(pdev) ?
  450. -EIO : e7xxx_probe1(pdev, ent->driver_data);
  451. }
  452. static void e7xxx_remove_one(struct pci_dev *pdev)
  453. {
  454. struct mem_ctl_info *mci;
  455. struct e7xxx_pvt *pvt;
  456. edac_dbg(0, "\n");
  457. if (e7xxx_pci)
  458. edac_pci_release_generic_ctl(e7xxx_pci);
  459. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  460. return;
  461. pvt = (struct e7xxx_pvt *)mci->pvt_info;
  462. pci_dev_put(pvt->bridge_ck);
  463. edac_mc_free(mci);
  464. }
  465. static const struct pci_device_id e7xxx_pci_tbl[] = {
  466. {
  467. PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  468. E7205},
  469. {
  470. PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  471. E7500},
  472. {
  473. PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  474. E7501},
  475. {
  476. PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
  477. E7505},
  478. {
  479. 0,
  480. } /* 0 terminated list. */
  481. };
  482. MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
  483. static struct pci_driver e7xxx_driver = {
  484. .name = EDAC_MOD_STR,
  485. .probe = e7xxx_init_one,
  486. .remove = e7xxx_remove_one,
  487. .id_table = e7xxx_pci_tbl,
  488. };
  489. static int __init e7xxx_init(void)
  490. {
  491. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  492. opstate_init();
  493. return pci_register_driver(&e7xxx_driver);
  494. }
  495. static void __exit e7xxx_exit(void)
  496. {
  497. pci_unregister_driver(&e7xxx_driver);
  498. }
  499. module_init(e7xxx_init);
  500. module_exit(e7xxx_exit);
  501. MODULE_LICENSE("GPL");
  502. MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
  503. "Based on.work by Dan Hollis et al");
  504. MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
  505. module_param(edac_op_state, int, 0444);
  506. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");