cell_edac.c 7.7 KB

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  1. /*
  2. * Cell MIC driver for ECC counting
  3. *
  4. * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
  5. * <benh@kernel.crashing.org>
  6. *
  7. * This file may be distributed under the terms of the
  8. * GNU General Public License.
  9. */
  10. #undef DEBUG
  11. #include <linux/edac.h>
  12. #include <linux/module.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/stop_machine.h>
  16. #include <linux/io.h>
  17. #include <linux/of_address.h>
  18. #include <asm/machdep.h>
  19. #include <asm/cell-regs.h>
  20. #include "edac_module.h"
  21. struct cell_edac_priv
  22. {
  23. struct cbe_mic_tm_regs __iomem *regs;
  24. int node;
  25. int chanmask;
  26. #ifdef DEBUG
  27. u64 prev_fir;
  28. #endif
  29. };
  30. static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
  31. {
  32. struct cell_edac_priv *priv = mci->pvt_info;
  33. struct csrow_info *csrow = mci->csrows[0];
  34. unsigned long address, pfn, offset, syndrome;
  35. dev_dbg(mci->pdev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n",
  36. priv->node, chan, ar);
  37. /* Address decoding is likely a bit bogus, to dbl check */
  38. address = (ar & 0xffffffffe0000000ul) >> 29;
  39. if (priv->chanmask == 0x3)
  40. address = (address << 1) | chan;
  41. pfn = address >> PAGE_SHIFT;
  42. offset = address & ~PAGE_MASK;
  43. syndrome = (ar & 0x000000001fe00000ul) >> 21;
  44. /* TODO: Decoding of the error address */
  45. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  46. csrow->first_page + pfn, offset, syndrome,
  47. 0, chan, -1, "", "");
  48. }
  49. static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
  50. {
  51. struct cell_edac_priv *priv = mci->pvt_info;
  52. struct csrow_info *csrow = mci->csrows[0];
  53. unsigned long address, pfn, offset;
  54. dev_dbg(mci->pdev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n",
  55. priv->node, chan, ar);
  56. /* Address decoding is likely a bit bogus, to dbl check */
  57. address = (ar & 0xffffffffe0000000ul) >> 29;
  58. if (priv->chanmask == 0x3)
  59. address = (address << 1) | chan;
  60. pfn = address >> PAGE_SHIFT;
  61. offset = address & ~PAGE_MASK;
  62. /* TODO: Decoding of the error address */
  63. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  64. csrow->first_page + pfn, offset, 0,
  65. 0, chan, -1, "", "");
  66. }
  67. static void cell_edac_check(struct mem_ctl_info *mci)
  68. {
  69. struct cell_edac_priv *priv = mci->pvt_info;
  70. u64 fir, addreg, clear = 0;
  71. fir = in_be64(&priv->regs->mic_fir);
  72. #ifdef DEBUG
  73. if (fir != priv->prev_fir) {
  74. dev_dbg(mci->pdev, "fir change : 0x%016lx\n", fir);
  75. priv->prev_fir = fir;
  76. }
  77. #endif
  78. if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
  79. addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
  80. clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
  81. cell_edac_count_ce(mci, 0, addreg);
  82. }
  83. if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
  84. addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
  85. clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
  86. cell_edac_count_ce(mci, 1, addreg);
  87. }
  88. if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
  89. addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
  90. clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
  91. cell_edac_count_ue(mci, 0, addreg);
  92. }
  93. if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
  94. addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
  95. clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
  96. cell_edac_count_ue(mci, 1, addreg);
  97. }
  98. /* The procedure for clearing FIR bits is a bit ... weird */
  99. if (clear) {
  100. fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
  101. fir |= CBE_MIC_FIR_ECC_RESET_MASK;
  102. fir &= ~clear;
  103. out_be64(&priv->regs->mic_fir, fir);
  104. (void)in_be64(&priv->regs->mic_fir);
  105. mb(); /* sync up */
  106. #ifdef DEBUG
  107. fir = in_be64(&priv->regs->mic_fir);
  108. dev_dbg(mci->pdev, "fir clear : 0x%016lx\n", fir);
  109. #endif
  110. }
  111. }
  112. static void cell_edac_init_csrows(struct mem_ctl_info *mci)
  113. {
  114. struct csrow_info *csrow = mci->csrows[0];
  115. struct dimm_info *dimm;
  116. struct cell_edac_priv *priv = mci->pvt_info;
  117. struct device_node *np;
  118. int j;
  119. u32 nr_pages;
  120. for_each_node_by_name(np, "memory") {
  121. struct resource r;
  122. /* We "know" that the Cell firmware only creates one entry
  123. * in the "memory" nodes. If that changes, this code will
  124. * need to be adapted.
  125. */
  126. if (of_address_to_resource(np, 0, &r))
  127. continue;
  128. if (of_node_to_nid(np) != priv->node)
  129. continue;
  130. csrow->first_page = r.start >> PAGE_SHIFT;
  131. nr_pages = resource_size(&r) >> PAGE_SHIFT;
  132. csrow->last_page = csrow->first_page + nr_pages - 1;
  133. for (j = 0; j < csrow->nr_channels; j++) {
  134. dimm = csrow->channels[j]->dimm;
  135. dimm->mtype = MEM_XDR;
  136. dimm->edac_mode = EDAC_SECDED;
  137. dimm->nr_pages = nr_pages / csrow->nr_channels;
  138. }
  139. dev_dbg(mci->pdev,
  140. "Initialized on node %d, chanmask=0x%x,"
  141. " first_page=0x%lx, nr_pages=0x%x\n",
  142. priv->node, priv->chanmask,
  143. csrow->first_page, nr_pages);
  144. break;
  145. }
  146. of_node_put(np);
  147. }
  148. static int cell_edac_probe(struct platform_device *pdev)
  149. {
  150. struct cbe_mic_tm_regs __iomem *regs;
  151. struct mem_ctl_info *mci;
  152. struct edac_mc_layer layers[2];
  153. struct cell_edac_priv *priv;
  154. u64 reg;
  155. int rc, chanmask, num_chans;
  156. regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
  157. if (regs == NULL)
  158. return -ENODEV;
  159. edac_op_state = EDAC_OPSTATE_POLL;
  160. /* Get channel population */
  161. reg = in_be64(&regs->mic_mnt_cfg);
  162. dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg);
  163. chanmask = 0;
  164. if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
  165. chanmask |= 0x1;
  166. if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
  167. chanmask |= 0x2;
  168. if (chanmask == 0) {
  169. dev_warn(&pdev->dev,
  170. "Yuck ! No channel populated ? Aborting !\n");
  171. return -ENODEV;
  172. }
  173. dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n",
  174. in_be64(&regs->mic_fir));
  175. /* Allocate & init EDAC MC data structure */
  176. num_chans = chanmask == 3 ? 2 : 1;
  177. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  178. layers[0].size = 1;
  179. layers[0].is_virt_csrow = true;
  180. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  181. layers[1].size = num_chans;
  182. layers[1].is_virt_csrow = false;
  183. mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
  184. sizeof(struct cell_edac_priv));
  185. if (mci == NULL)
  186. return -ENOMEM;
  187. priv = mci->pvt_info;
  188. priv->regs = regs;
  189. priv->node = pdev->id;
  190. priv->chanmask = chanmask;
  191. mci->pdev = &pdev->dev;
  192. mci->mtype_cap = MEM_FLAG_XDR;
  193. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  194. mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  195. mci->mod_name = "cell_edac";
  196. mci->ctl_name = "MIC";
  197. mci->dev_name = dev_name(&pdev->dev);
  198. mci->edac_check = cell_edac_check;
  199. cell_edac_init_csrows(mci);
  200. /* Register with EDAC core */
  201. rc = edac_mc_add_mc(mci);
  202. if (rc) {
  203. dev_err(&pdev->dev, "failed to register with EDAC core\n");
  204. edac_mc_free(mci);
  205. return rc;
  206. }
  207. return 0;
  208. }
  209. static int cell_edac_remove(struct platform_device *pdev)
  210. {
  211. struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
  212. if (mci)
  213. edac_mc_free(mci);
  214. return 0;
  215. }
  216. static struct platform_driver cell_edac_driver = {
  217. .driver = {
  218. .name = "cbe-mic",
  219. },
  220. .probe = cell_edac_probe,
  221. .remove = cell_edac_remove,
  222. };
  223. static int __init cell_edac_init(void)
  224. {
  225. /* Sanity check registers data structure */
  226. BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
  227. mic_df_ecc_address_0) != 0xf8);
  228. BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
  229. mic_df_ecc_address_1) != 0x1b8);
  230. BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
  231. mic_df_config) != 0x218);
  232. BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
  233. mic_fir) != 0x230);
  234. BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
  235. mic_mnt_cfg) != 0x210);
  236. BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
  237. mic_exc) != 0x208);
  238. return platform_driver_register(&cell_edac_driver);
  239. }
  240. static void __exit cell_edac_exit(void)
  241. {
  242. platform_driver_unregister(&cell_edac_driver);
  243. }
  244. module_init(cell_edac_init);
  245. module_exit(cell_edac_exit);
  246. MODULE_LICENSE("GPL");
  247. MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
  248. MODULE_DESCRIPTION("ECC counting for Cell MIC");