bluefield_edac.c 9.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Bluefield-specific EDAC driver.
  4. *
  5. * Copyright (c) 2019 Mellanox Technologies.
  6. */
  7. #include <linux/acpi.h>
  8. #include <linux/arm-smccc.h>
  9. #include <linux/bitfield.h>
  10. #include <linux/edac.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/platform_device.h>
  14. #include "edac_module.h"
  15. #define DRIVER_NAME "bluefield-edac"
  16. /*
  17. * Mellanox BlueField EMI (External Memory Interface) register definitions.
  18. */
  19. #define MLXBF_ECC_CNT 0x340
  20. #define MLXBF_ECC_CNT__SERR_CNT GENMASK(15, 0)
  21. #define MLXBF_ECC_CNT__DERR_CNT GENMASK(31, 16)
  22. #define MLXBF_ECC_ERR 0x348
  23. #define MLXBF_ECC_ERR__SECC BIT(0)
  24. #define MLXBF_ECC_ERR__DECC BIT(16)
  25. #define MLXBF_ECC_LATCH_SEL 0x354
  26. #define MLXBF_ECC_LATCH_SEL__START BIT(24)
  27. #define MLXBF_ERR_ADDR_0 0x358
  28. #define MLXBF_ERR_ADDR_1 0x37c
  29. #define MLXBF_SYNDROM 0x35c
  30. #define MLXBF_SYNDROM__DERR BIT(0)
  31. #define MLXBF_SYNDROM__SERR BIT(1)
  32. #define MLXBF_SYNDROM__SYN GENMASK(25, 16)
  33. #define MLXBF_ADD_INFO 0x364
  34. #define MLXBF_ADD_INFO__ERR_PRANK GENMASK(9, 8)
  35. #define MLXBF_EDAC_MAX_DIMM_PER_MC 2
  36. #define MLXBF_EDAC_ERROR_GRAIN 8
  37. /*
  38. * Request MLNX_SIP_GET_DIMM_INFO
  39. *
  40. * Retrieve information about DIMM on a certain slot.
  41. *
  42. * Call register usage:
  43. * a0: MLNX_SIP_GET_DIMM_INFO
  44. * a1: (Memory controller index) << 16 | (Dimm index in memory controller)
  45. * a2-7: not used.
  46. *
  47. * Return status:
  48. * a0: MLXBF_DIMM_INFO defined below describing the DIMM.
  49. * a1-3: not used.
  50. */
  51. #define MLNX_SIP_GET_DIMM_INFO 0x82000008
  52. /* Format for the SMC response about the memory information */
  53. #define MLXBF_DIMM_INFO__SIZE_GB GENMASK_ULL(15, 0)
  54. #define MLXBF_DIMM_INFO__IS_RDIMM BIT(16)
  55. #define MLXBF_DIMM_INFO__IS_LRDIMM BIT(17)
  56. #define MLXBF_DIMM_INFO__IS_NVDIMM BIT(18)
  57. #define MLXBF_DIMM_INFO__RANKS GENMASK_ULL(23, 21)
  58. #define MLXBF_DIMM_INFO__PACKAGE_X GENMASK_ULL(31, 24)
  59. struct bluefield_edac_priv {
  60. int dimm_ranks[MLXBF_EDAC_MAX_DIMM_PER_MC];
  61. void __iomem *emi_base;
  62. int dimm_per_mc;
  63. };
  64. static u64 smc_call1(u64 smc_op, u64 smc_arg)
  65. {
  66. struct arm_smccc_res res;
  67. arm_smccc_smc(smc_op, smc_arg, 0, 0, 0, 0, 0, 0, &res);
  68. return res.a0;
  69. }
  70. /*
  71. * Gather the ECC information from the External Memory Interface registers
  72. * and report it to the edac handler.
  73. */
  74. static void bluefield_gather_report_ecc(struct mem_ctl_info *mci,
  75. int error_cnt,
  76. int is_single_ecc)
  77. {
  78. struct bluefield_edac_priv *priv = mci->pvt_info;
  79. u32 dram_additional_info, err_prank, edea0, edea1;
  80. u32 ecc_latch_select, dram_syndrom, serr, derr, syndrom;
  81. enum hw_event_mc_err_type ecc_type;
  82. u64 ecc_dimm_addr;
  83. int ecc_dimm;
  84. ecc_type = is_single_ecc ? HW_EVENT_ERR_CORRECTED :
  85. HW_EVENT_ERR_UNCORRECTED;
  86. /*
  87. * Tell the External Memory Interface to populate the relevant
  88. * registers with information about the last ECC error occurrence.
  89. */
  90. ecc_latch_select = MLXBF_ECC_LATCH_SEL__START;
  91. writel(ecc_latch_select, priv->emi_base + MLXBF_ECC_LATCH_SEL);
  92. /*
  93. * Verify that the ECC reported info in the registers is of the
  94. * same type as the one asked to report. If not, just report the
  95. * error without the detailed information.
  96. */
  97. dram_syndrom = readl(priv->emi_base + MLXBF_SYNDROM);
  98. serr = FIELD_GET(MLXBF_SYNDROM__SERR, dram_syndrom);
  99. derr = FIELD_GET(MLXBF_SYNDROM__DERR, dram_syndrom);
  100. syndrom = FIELD_GET(MLXBF_SYNDROM__SYN, dram_syndrom);
  101. if ((is_single_ecc && !serr) || (!is_single_ecc && !derr)) {
  102. edac_mc_handle_error(ecc_type, mci, error_cnt, 0, 0, 0,
  103. 0, 0, -1, mci->ctl_name, "");
  104. return;
  105. }
  106. dram_additional_info = readl(priv->emi_base + MLXBF_ADD_INFO);
  107. err_prank = FIELD_GET(MLXBF_ADD_INFO__ERR_PRANK, dram_additional_info);
  108. ecc_dimm = (err_prank >= 2 && priv->dimm_ranks[0] <= 2) ? 1 : 0;
  109. edea0 = readl(priv->emi_base + MLXBF_ERR_ADDR_0);
  110. edea1 = readl(priv->emi_base + MLXBF_ERR_ADDR_1);
  111. ecc_dimm_addr = ((u64)edea1 << 32) | edea0;
  112. edac_mc_handle_error(ecc_type, mci, error_cnt,
  113. PFN_DOWN(ecc_dimm_addr),
  114. offset_in_page(ecc_dimm_addr),
  115. syndrom, ecc_dimm, 0, 0, mci->ctl_name, "");
  116. }
  117. static void bluefield_edac_check(struct mem_ctl_info *mci)
  118. {
  119. struct bluefield_edac_priv *priv = mci->pvt_info;
  120. u32 ecc_count, single_error_count, double_error_count, ecc_error = 0;
  121. /*
  122. * The memory controller might not be initialized by the firmware
  123. * when there isn't memory, which may lead to bad register readings.
  124. */
  125. if (mci->edac_cap == EDAC_FLAG_NONE)
  126. return;
  127. ecc_count = readl(priv->emi_base + MLXBF_ECC_CNT);
  128. single_error_count = FIELD_GET(MLXBF_ECC_CNT__SERR_CNT, ecc_count);
  129. double_error_count = FIELD_GET(MLXBF_ECC_CNT__DERR_CNT, ecc_count);
  130. if (single_error_count) {
  131. ecc_error |= MLXBF_ECC_ERR__SECC;
  132. bluefield_gather_report_ecc(mci, single_error_count, 1);
  133. }
  134. if (double_error_count) {
  135. ecc_error |= MLXBF_ECC_ERR__DECC;
  136. bluefield_gather_report_ecc(mci, double_error_count, 0);
  137. }
  138. /* Write to clear reported errors. */
  139. if (ecc_count)
  140. writel(ecc_error, priv->emi_base + MLXBF_ECC_ERR);
  141. }
  142. /* Initialize the DIMMs information for the given memory controller. */
  143. static void bluefield_edac_init_dimms(struct mem_ctl_info *mci)
  144. {
  145. struct bluefield_edac_priv *priv = mci->pvt_info;
  146. int mem_ctrl_idx = mci->mc_idx;
  147. struct dimm_info *dimm;
  148. u64 smc_info, smc_arg;
  149. int is_empty = 1, i;
  150. for (i = 0; i < priv->dimm_per_mc; i++) {
  151. dimm = mci->dimms[i];
  152. smc_arg = mem_ctrl_idx << 16 | i;
  153. smc_info = smc_call1(MLNX_SIP_GET_DIMM_INFO, smc_arg);
  154. if (!FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info)) {
  155. dimm->mtype = MEM_EMPTY;
  156. continue;
  157. }
  158. is_empty = 0;
  159. dimm->edac_mode = EDAC_SECDED;
  160. if (FIELD_GET(MLXBF_DIMM_INFO__IS_NVDIMM, smc_info))
  161. dimm->mtype = MEM_NVDIMM;
  162. else if (FIELD_GET(MLXBF_DIMM_INFO__IS_LRDIMM, smc_info))
  163. dimm->mtype = MEM_LRDDR4;
  164. else if (FIELD_GET(MLXBF_DIMM_INFO__IS_RDIMM, smc_info))
  165. dimm->mtype = MEM_RDDR4;
  166. else
  167. dimm->mtype = MEM_DDR4;
  168. dimm->nr_pages =
  169. FIELD_GET(MLXBF_DIMM_INFO__SIZE_GB, smc_info) *
  170. (SZ_1G / PAGE_SIZE);
  171. dimm->grain = MLXBF_EDAC_ERROR_GRAIN;
  172. /* Mem controller for BlueField only supports x4, x8 and x16 */
  173. switch (FIELD_GET(MLXBF_DIMM_INFO__PACKAGE_X, smc_info)) {
  174. case 4:
  175. dimm->dtype = DEV_X4;
  176. break;
  177. case 8:
  178. dimm->dtype = DEV_X8;
  179. break;
  180. case 16:
  181. dimm->dtype = DEV_X16;
  182. break;
  183. default:
  184. dimm->dtype = DEV_UNKNOWN;
  185. }
  186. priv->dimm_ranks[i] =
  187. FIELD_GET(MLXBF_DIMM_INFO__RANKS, smc_info);
  188. }
  189. if (is_empty)
  190. mci->edac_cap = EDAC_FLAG_NONE;
  191. else
  192. mci->edac_cap = EDAC_FLAG_SECDED;
  193. }
  194. static int bluefield_edac_mc_probe(struct platform_device *pdev)
  195. {
  196. struct bluefield_edac_priv *priv;
  197. struct device *dev = &pdev->dev;
  198. struct edac_mc_layer layers[1];
  199. struct mem_ctl_info *mci;
  200. struct resource *emi_res;
  201. unsigned int mc_idx, dimm_count;
  202. int rc, ret;
  203. /* Read the MSS (Memory SubSystem) index from ACPI table. */
  204. if (device_property_read_u32(dev, "mss_number", &mc_idx)) {
  205. dev_warn(dev, "bf_edac: MSS number unknown\n");
  206. return -EINVAL;
  207. }
  208. /* Read the DIMMs per MC from ACPI table. */
  209. if (device_property_read_u32(dev, "dimm_per_mc", &dimm_count)) {
  210. dev_warn(dev, "bf_edac: DIMMs per MC unknown\n");
  211. return -EINVAL;
  212. }
  213. if (dimm_count > MLXBF_EDAC_MAX_DIMM_PER_MC) {
  214. dev_warn(dev, "bf_edac: DIMMs per MC not valid\n");
  215. return -EINVAL;
  216. }
  217. emi_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  218. if (!emi_res)
  219. return -EINVAL;
  220. layers[0].type = EDAC_MC_LAYER_SLOT;
  221. layers[0].size = dimm_count;
  222. layers[0].is_virt_csrow = true;
  223. mci = edac_mc_alloc(mc_idx, ARRAY_SIZE(layers), layers, sizeof(*priv));
  224. if (!mci)
  225. return -ENOMEM;
  226. priv = mci->pvt_info;
  227. priv->dimm_per_mc = dimm_count;
  228. priv->emi_base = devm_ioremap_resource(dev, emi_res);
  229. if (IS_ERR(priv->emi_base)) {
  230. dev_err(dev, "failed to map EMI IO resource\n");
  231. ret = PTR_ERR(priv->emi_base);
  232. goto err;
  233. }
  234. mci->pdev = dev;
  235. mci->mtype_cap = MEM_FLAG_DDR4 | MEM_FLAG_RDDR4 |
  236. MEM_FLAG_LRDDR4 | MEM_FLAG_NVDIMM;
  237. mci->edac_ctl_cap = EDAC_FLAG_SECDED;
  238. mci->mod_name = DRIVER_NAME;
  239. mci->ctl_name = "BlueField_Memory_Controller";
  240. mci->dev_name = dev_name(dev);
  241. mci->edac_check = bluefield_edac_check;
  242. /* Initialize mci with the actual populated DIMM information. */
  243. bluefield_edac_init_dimms(mci);
  244. platform_set_drvdata(pdev, mci);
  245. /* Register with EDAC core */
  246. rc = edac_mc_add_mc(mci);
  247. if (rc) {
  248. dev_err(dev, "failed to register with EDAC core\n");
  249. ret = rc;
  250. goto err;
  251. }
  252. /* Only POLL mode supported so far. */
  253. edac_op_state = EDAC_OPSTATE_POLL;
  254. return 0;
  255. err:
  256. edac_mc_free(mci);
  257. return ret;
  258. }
  259. static int bluefield_edac_mc_remove(struct platform_device *pdev)
  260. {
  261. struct mem_ctl_info *mci = platform_get_drvdata(pdev);
  262. edac_mc_del_mc(&pdev->dev);
  263. edac_mc_free(mci);
  264. return 0;
  265. }
  266. static const struct acpi_device_id bluefield_mc_acpi_ids[] = {
  267. {"MLNXBF08", 0},
  268. {}
  269. };
  270. MODULE_DEVICE_TABLE(acpi, bluefield_mc_acpi_ids);
  271. static struct platform_driver bluefield_edac_mc_driver = {
  272. .driver = {
  273. .name = DRIVER_NAME,
  274. .acpi_match_table = bluefield_mc_acpi_ids,
  275. },
  276. .probe = bluefield_edac_mc_probe,
  277. .remove = bluefield_edac_mc_remove,
  278. };
  279. module_platform_driver(bluefield_edac_mc_driver);
  280. MODULE_DESCRIPTION("Mellanox BlueField memory edac driver");
  281. MODULE_AUTHOR("Mellanox Technologies");
  282. MODULE_LICENSE("GPL v2");