aspeed_edac.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018, 2019 Cisco Systems
  4. */
  5. #include <linux/edac.h>
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/stop_machine.h>
  11. #include <linux/io.h>
  12. #include <linux/of_address.h>
  13. #include <linux/regmap.h>
  14. #include "edac_module.h"
  15. #define DRV_NAME "aspeed-edac"
  16. #define ASPEED_MCR_PROT 0x00 /* protection key register */
  17. #define ASPEED_MCR_CONF 0x04 /* configuration register */
  18. #define ASPEED_MCR_INTR_CTRL 0x50 /* interrupt control/status register */
  19. #define ASPEED_MCR_ADDR_UNREC 0x58 /* address of first un-recoverable error */
  20. #define ASPEED_MCR_ADDR_REC 0x5c /* address of last recoverable error */
  21. #define ASPEED_MCR_LAST ASPEED_MCR_ADDR_REC
  22. #define ASPEED_MCR_PROT_PASSWD 0xfc600309
  23. #define ASPEED_MCR_CONF_DRAM_TYPE BIT(4)
  24. #define ASPEED_MCR_CONF_ECC BIT(7)
  25. #define ASPEED_MCR_INTR_CTRL_CLEAR BIT(31)
  26. #define ASPEED_MCR_INTR_CTRL_CNT_REC GENMASK(23, 16)
  27. #define ASPEED_MCR_INTR_CTRL_CNT_UNREC GENMASK(15, 12)
  28. #define ASPEED_MCR_INTR_CTRL_ENABLE (BIT(0) | BIT(1))
  29. static struct regmap *aspeed_regmap;
  30. static int regmap_reg_write(void *context, unsigned int reg, unsigned int val)
  31. {
  32. void __iomem *regs = (void __iomem *)context;
  33. /* enable write to MCR register set */
  34. writel(ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
  35. writel(val, regs + reg);
  36. /* disable write to MCR register set */
  37. writel(~ASPEED_MCR_PROT_PASSWD, regs + ASPEED_MCR_PROT);
  38. return 0;
  39. }
  40. static int regmap_reg_read(void *context, unsigned int reg, unsigned int *val)
  41. {
  42. void __iomem *regs = (void __iomem *)context;
  43. *val = readl(regs + reg);
  44. return 0;
  45. }
  46. static bool regmap_is_volatile(struct device *dev, unsigned int reg)
  47. {
  48. switch (reg) {
  49. case ASPEED_MCR_PROT:
  50. case ASPEED_MCR_INTR_CTRL:
  51. case ASPEED_MCR_ADDR_UNREC:
  52. case ASPEED_MCR_ADDR_REC:
  53. return true;
  54. default:
  55. return false;
  56. }
  57. }
  58. static const struct regmap_config aspeed_regmap_config = {
  59. .reg_bits = 32,
  60. .val_bits = 32,
  61. .reg_stride = 4,
  62. .max_register = ASPEED_MCR_LAST,
  63. .reg_write = regmap_reg_write,
  64. .reg_read = regmap_reg_read,
  65. .volatile_reg = regmap_is_volatile,
  66. .fast_io = true,
  67. };
  68. static void count_rec(struct mem_ctl_info *mci, u8 rec_cnt, u32 rec_addr)
  69. {
  70. struct csrow_info *csrow = mci->csrows[0];
  71. u32 page, offset, syndrome;
  72. if (!rec_cnt)
  73. return;
  74. /* report first few errors (if there are) */
  75. /* note: no addresses are recorded */
  76. if (rec_cnt > 1) {
  77. /* page, offset and syndrome are not available */
  78. page = 0;
  79. offset = 0;
  80. syndrome = 0;
  81. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, rec_cnt-1,
  82. page, offset, syndrome, 0, 0, -1,
  83. "address(es) not available", "");
  84. }
  85. /* report last error */
  86. /* note: rec_addr is the last recoverable error addr */
  87. page = rec_addr >> PAGE_SHIFT;
  88. offset = rec_addr & ~PAGE_MASK;
  89. /* syndrome is not available */
  90. syndrome = 0;
  91. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
  92. csrow->first_page + page, offset, syndrome,
  93. 0, 0, -1, "", "");
  94. }
  95. static void count_un_rec(struct mem_ctl_info *mci, u8 un_rec_cnt,
  96. u32 un_rec_addr)
  97. {
  98. struct csrow_info *csrow = mci->csrows[0];
  99. u32 page, offset, syndrome;
  100. if (!un_rec_cnt)
  101. return;
  102. /* report 1. error */
  103. /* note: un_rec_addr is the first unrecoverable error addr */
  104. page = un_rec_addr >> PAGE_SHIFT;
  105. offset = un_rec_addr & ~PAGE_MASK;
  106. /* syndrome is not available */
  107. syndrome = 0;
  108. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
  109. csrow->first_page + page, offset, syndrome,
  110. 0, 0, -1, "", "");
  111. /* report further errors (if there are) */
  112. /* note: no addresses are recorded */
  113. if (un_rec_cnt > 1) {
  114. /* page, offset and syndrome are not available */
  115. page = 0;
  116. offset = 0;
  117. syndrome = 0;
  118. edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, un_rec_cnt-1,
  119. page, offset, syndrome, 0, 0, -1,
  120. "address(es) not available", "");
  121. }
  122. }
  123. static irqreturn_t mcr_isr(int irq, void *arg)
  124. {
  125. struct mem_ctl_info *mci = arg;
  126. u32 rec_addr, un_rec_addr;
  127. u32 reg50, reg5c, reg58;
  128. u8 rec_cnt, un_rec_cnt;
  129. regmap_read(aspeed_regmap, ASPEED_MCR_INTR_CTRL, &reg50);
  130. dev_dbg(mci->pdev, "received edac interrupt w/ mcr register 50: 0x%x\n",
  131. reg50);
  132. /* collect data about recoverable and unrecoverable errors */
  133. rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_REC) >> 16;
  134. un_rec_cnt = (reg50 & ASPEED_MCR_INTR_CTRL_CNT_UNREC) >> 12;
  135. dev_dbg(mci->pdev, "%d recoverable interrupts and %d unrecoverable interrupts\n",
  136. rec_cnt, un_rec_cnt);
  137. regmap_read(aspeed_regmap, ASPEED_MCR_ADDR_UNREC, &reg58);
  138. un_rec_addr = reg58;
  139. regmap_read(aspeed_regmap, ASPEED_MCR_ADDR_REC, &reg5c);
  140. rec_addr = reg5c;
  141. /* clear interrupt flags and error counters: */
  142. regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL,
  143. ASPEED_MCR_INTR_CTRL_CLEAR,
  144. ASPEED_MCR_INTR_CTRL_CLEAR);
  145. regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL,
  146. ASPEED_MCR_INTR_CTRL_CLEAR, 0);
  147. /* process recoverable and unrecoverable errors */
  148. count_rec(mci, rec_cnt, rec_addr);
  149. count_un_rec(mci, un_rec_cnt, un_rec_addr);
  150. if (!rec_cnt && !un_rec_cnt)
  151. dev_dbg(mci->pdev, "received edac interrupt, but did not find any ECC counters\n");
  152. regmap_read(aspeed_regmap, ASPEED_MCR_INTR_CTRL, &reg50);
  153. dev_dbg(mci->pdev, "edac interrupt handled. mcr reg 50 is now: 0x%x\n",
  154. reg50);
  155. return IRQ_HANDLED;
  156. }
  157. static int config_irq(void *ctx, struct platform_device *pdev)
  158. {
  159. int irq;
  160. int rc;
  161. /* register interrupt handler */
  162. irq = platform_get_irq(pdev, 0);
  163. dev_dbg(&pdev->dev, "got irq %d\n", irq);
  164. if (irq < 0)
  165. return irq;
  166. rc = devm_request_irq(&pdev->dev, irq, mcr_isr, IRQF_TRIGGER_HIGH,
  167. DRV_NAME, ctx);
  168. if (rc) {
  169. dev_err(&pdev->dev, "unable to request irq %d\n", irq);
  170. return rc;
  171. }
  172. /* enable interrupts */
  173. regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL,
  174. ASPEED_MCR_INTR_CTRL_ENABLE,
  175. ASPEED_MCR_INTR_CTRL_ENABLE);
  176. return 0;
  177. }
  178. static int init_csrows(struct mem_ctl_info *mci)
  179. {
  180. struct csrow_info *csrow = mci->csrows[0];
  181. u32 nr_pages, dram_type;
  182. struct dimm_info *dimm;
  183. struct device_node *np;
  184. struct resource r;
  185. u32 reg04;
  186. int rc;
  187. /* retrieve info about physical memory from device tree */
  188. np = of_find_node_by_path("/memory");
  189. if (!np) {
  190. dev_err(mci->pdev, "dt: missing /memory node\n");
  191. return -ENODEV;
  192. }
  193. rc = of_address_to_resource(np, 0, &r);
  194. of_node_put(np);
  195. if (rc) {
  196. dev_err(mci->pdev, "dt: failed requesting resource for /memory node\n");
  197. return rc;
  198. }
  199. dev_dbg(mci->pdev, "dt: /memory node resources: first page r.start=0x%x, resource_size=0x%x, PAGE_SHIFT macro=0x%x\n",
  200. r.start, resource_size(&r), PAGE_SHIFT);
  201. csrow->first_page = r.start >> PAGE_SHIFT;
  202. nr_pages = resource_size(&r) >> PAGE_SHIFT;
  203. csrow->last_page = csrow->first_page + nr_pages - 1;
  204. regmap_read(aspeed_regmap, ASPEED_MCR_CONF, &reg04);
  205. dram_type = (reg04 & ASPEED_MCR_CONF_DRAM_TYPE) ? MEM_DDR4 : MEM_DDR3;
  206. dimm = csrow->channels[0]->dimm;
  207. dimm->mtype = dram_type;
  208. dimm->edac_mode = EDAC_SECDED;
  209. dimm->nr_pages = nr_pages / csrow->nr_channels;
  210. dev_dbg(mci->pdev, "initialized dimm with first_page=0x%lx and nr_pages=0x%x\n",
  211. csrow->first_page, nr_pages);
  212. return 0;
  213. }
  214. static int aspeed_probe(struct platform_device *pdev)
  215. {
  216. struct device *dev = &pdev->dev;
  217. struct edac_mc_layer layers[2];
  218. struct mem_ctl_info *mci;
  219. void __iomem *regs;
  220. u32 reg04;
  221. int rc;
  222. regs = devm_platform_ioremap_resource(pdev, 0);
  223. if (IS_ERR(regs))
  224. return PTR_ERR(regs);
  225. aspeed_regmap = devm_regmap_init(dev, NULL, (__force void *)regs,
  226. &aspeed_regmap_config);
  227. if (IS_ERR(aspeed_regmap))
  228. return PTR_ERR(aspeed_regmap);
  229. /* bail out if ECC mode is not configured */
  230. regmap_read(aspeed_regmap, ASPEED_MCR_CONF, &reg04);
  231. if (!(reg04 & ASPEED_MCR_CONF_ECC)) {
  232. dev_err(&pdev->dev, "ECC mode is not configured in u-boot\n");
  233. return -EPERM;
  234. }
  235. edac_op_state = EDAC_OPSTATE_INT;
  236. /* allocate & init EDAC MC data structure */
  237. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  238. layers[0].size = 1;
  239. layers[0].is_virt_csrow = true;
  240. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  241. layers[1].size = 1;
  242. layers[1].is_virt_csrow = false;
  243. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
  244. if (!mci)
  245. return -ENOMEM;
  246. mci->pdev = &pdev->dev;
  247. mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR4;
  248. mci->edac_ctl_cap = EDAC_FLAG_SECDED;
  249. mci->edac_cap = EDAC_FLAG_SECDED;
  250. mci->scrub_cap = SCRUB_FLAG_HW_SRC;
  251. mci->scrub_mode = SCRUB_HW_SRC;
  252. mci->mod_name = DRV_NAME;
  253. mci->ctl_name = "MIC";
  254. mci->dev_name = dev_name(&pdev->dev);
  255. rc = init_csrows(mci);
  256. if (rc) {
  257. dev_err(&pdev->dev, "failed to init csrows\n");
  258. goto probe_exit02;
  259. }
  260. platform_set_drvdata(pdev, mci);
  261. /* register with edac core */
  262. rc = edac_mc_add_mc(mci);
  263. if (rc) {
  264. dev_err(&pdev->dev, "failed to register with EDAC core\n");
  265. goto probe_exit02;
  266. }
  267. /* register interrupt handler and enable interrupts */
  268. rc = config_irq(mci, pdev);
  269. if (rc) {
  270. dev_err(&pdev->dev, "failed setting up irq\n");
  271. goto probe_exit01;
  272. }
  273. return 0;
  274. probe_exit01:
  275. edac_mc_del_mc(&pdev->dev);
  276. probe_exit02:
  277. edac_mc_free(mci);
  278. return rc;
  279. }
  280. static int aspeed_remove(struct platform_device *pdev)
  281. {
  282. struct mem_ctl_info *mci;
  283. /* disable interrupts */
  284. regmap_update_bits(aspeed_regmap, ASPEED_MCR_INTR_CTRL,
  285. ASPEED_MCR_INTR_CTRL_ENABLE, 0);
  286. /* free resources */
  287. mci = edac_mc_del_mc(&pdev->dev);
  288. if (mci)
  289. edac_mc_free(mci);
  290. return 0;
  291. }
  292. static const struct of_device_id aspeed_of_match[] = {
  293. { .compatible = "aspeed,ast2500-sdram-edac" },
  294. {},
  295. };
  296. static struct platform_driver aspeed_driver = {
  297. .driver = {
  298. .name = DRV_NAME,
  299. .of_match_table = aspeed_of_match
  300. },
  301. .probe = aspeed_probe,
  302. .remove = aspeed_remove
  303. };
  304. module_platform_driver(aspeed_driver);
  305. MODULE_LICENSE("GPL");
  306. MODULE_AUTHOR("Stefan Schaeckeler <sschaeck@cisco.com>");
  307. MODULE_DESCRIPTION("Aspeed AST2500 EDAC driver");
  308. MODULE_VERSION("1.0");