amd8131_edac.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip
  4. *
  5. * Copyright (c) 2008 Wind River Systems, Inc.
  6. *
  7. * Authors: Cao Qingtao <qingtao.cao@windriver.com>
  8. * Benjamin Walsh <benjamin.walsh@windriver.com>
  9. * Hu Yongqi <yongqi.hu@windriver.com>
  10. */
  11. #ifndef _AMD8131_EDAC_H_
  12. #define _AMD8131_EDAC_H_
  13. #define DEVFN_PCIX_BRIDGE_NORTH_A 8
  14. #define DEVFN_PCIX_BRIDGE_NORTH_B 16
  15. #define DEVFN_PCIX_BRIDGE_SOUTH_A 24
  16. #define DEVFN_PCIX_BRIDGE_SOUTH_B 32
  17. /************************************************************
  18. * PCI-X Bridge Status and Command Register, DevA:0x04
  19. ************************************************************/
  20. #define REG_STS_CMD 0x04
  21. enum sts_cmd_bits {
  22. STS_CMD_SSE = BIT(30),
  23. STS_CMD_SERREN = BIT(8)
  24. };
  25. /************************************************************
  26. * PCI-X Bridge Interrupt and Bridge Control Register,
  27. ************************************************************/
  28. #define REG_INT_CTLR 0x3c
  29. enum int_ctlr_bits {
  30. INT_CTLR_DTSE = BIT(27),
  31. INT_CTLR_DTS = BIT(26),
  32. INT_CTLR_SERR = BIT(17),
  33. INT_CTLR_PERR = BIT(16)
  34. };
  35. /************************************************************
  36. * PCI-X Bridge Memory Base-Limit Register, DevA:0x1C
  37. ************************************************************/
  38. #define REG_MEM_LIM 0x1c
  39. enum mem_limit_bits {
  40. MEM_LIMIT_DPE = BIT(31),
  41. MEM_LIMIT_RSE = BIT(30),
  42. MEM_LIMIT_RMA = BIT(29),
  43. MEM_LIMIT_RTA = BIT(28),
  44. MEM_LIMIT_STA = BIT(27),
  45. MEM_LIMIT_MDPE = BIT(24),
  46. MEM_LIMIT_MASK = MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA|
  47. MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE
  48. };
  49. /************************************************************
  50. * Link Configuration And Control Register, side A
  51. ************************************************************/
  52. #define REG_LNK_CTRL_A 0xc4
  53. /************************************************************
  54. * Link Configuration And Control Register, side B
  55. ************************************************************/
  56. #define REG_LNK_CTRL_B 0xc8
  57. enum lnk_ctrl_bits {
  58. LNK_CTRL_CRCERR_A = BIT(9),
  59. LNK_CTRL_CRCERR_B = BIT(8),
  60. LNK_CTRL_CRCFEN = BIT(1)
  61. };
  62. enum pcix_bridge_inst {
  63. NORTH_A = 0,
  64. NORTH_B = 1,
  65. SOUTH_A = 2,
  66. SOUTH_B = 3,
  67. NO_BRIDGE = 4
  68. };
  69. struct amd8131_dev_info {
  70. int devfn;
  71. enum pcix_bridge_inst inst;
  72. struct pci_dev *dev;
  73. int edac_idx; /* pci device index */
  74. char *ctl_name;
  75. struct edac_pci_ctl_info *edac_dev;
  76. };
  77. /*
  78. * AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC
  79. * Controller, and ATCA-6101 has two AMD8131 chipsets, so there are
  80. * four PCIX Bridges on ATCA-6101 altogether.
  81. *
  82. * These PCIX Bridges share the same PCI Device ID and are all of
  83. * Function Zero, they could be discrimated by their pci_dev->devfn.
  84. * They share the same set of init/check/exit methods, and their
  85. * private structures are collected in the devices[] array.
  86. */
  87. struct amd8131_info {
  88. u16 err_dev; /* PCI Device ID for AMD8131 APIC*/
  89. struct amd8131_dev_info *devices;
  90. void (*init)(struct amd8131_dev_info *dev_info);
  91. void (*exit)(struct amd8131_dev_info *dev_info);
  92. void (*check)(struct edac_pci_ctl_info *edac_dev);
  93. };
  94. #endif /* _AMD8131_EDAC_H_ */