amd8131_edac.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * amd8131_edac.c, AMD8131 hypertransport chip EDAC kernel module
  4. *
  5. * Copyright (c) 2008 Wind River Systems, Inc.
  6. *
  7. * Authors: Cao Qingtao <qingtao.cao@windriver.com>
  8. * Benjamin Walsh <benjamin.walsh@windriver.com>
  9. * Hu Yongqi <yongqi.hu@windriver.com>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/io.h>
  15. #include <linux/bitops.h>
  16. #include <linux/edac.h>
  17. #include <linux/pci_ids.h>
  18. #include "edac_module.h"
  19. #include "amd8131_edac.h"
  20. #define AMD8131_EDAC_REVISION " Ver: 1.0.0"
  21. #define AMD8131_EDAC_MOD_STR "amd8131_edac"
  22. /* Wrapper functions for accessing PCI configuration space */
  23. static void edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
  24. {
  25. int ret;
  26. ret = pci_read_config_dword(dev, reg, val32);
  27. if (ret != 0)
  28. printk(KERN_ERR AMD8131_EDAC_MOD_STR
  29. " PCI Access Read Error at 0x%x\n", reg);
  30. }
  31. static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
  32. {
  33. int ret;
  34. ret = pci_write_config_dword(dev, reg, val32);
  35. if (ret != 0)
  36. printk(KERN_ERR AMD8131_EDAC_MOD_STR
  37. " PCI Access Write Error at 0x%x\n", reg);
  38. }
  39. /* Support up to two AMD8131 chipsets on a platform */
  40. static struct amd8131_dev_info amd8131_devices[] = {
  41. {
  42. .inst = NORTH_A,
  43. .devfn = DEVFN_PCIX_BRIDGE_NORTH_A,
  44. .ctl_name = "AMD8131_PCIX_NORTH_A",
  45. },
  46. {
  47. .inst = NORTH_B,
  48. .devfn = DEVFN_PCIX_BRIDGE_NORTH_B,
  49. .ctl_name = "AMD8131_PCIX_NORTH_B",
  50. },
  51. {
  52. .inst = SOUTH_A,
  53. .devfn = DEVFN_PCIX_BRIDGE_SOUTH_A,
  54. .ctl_name = "AMD8131_PCIX_SOUTH_A",
  55. },
  56. {
  57. .inst = SOUTH_B,
  58. .devfn = DEVFN_PCIX_BRIDGE_SOUTH_B,
  59. .ctl_name = "AMD8131_PCIX_SOUTH_B",
  60. },
  61. {.inst = NO_BRIDGE,},
  62. };
  63. static void amd8131_pcix_init(struct amd8131_dev_info *dev_info)
  64. {
  65. u32 val32;
  66. struct pci_dev *dev = dev_info->dev;
  67. /* First clear error detection flags */
  68. edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
  69. if (val32 & MEM_LIMIT_MASK)
  70. edac_pci_write_dword(dev, REG_MEM_LIM, val32);
  71. /* Clear Discard Timer Timedout flag */
  72. edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
  73. if (val32 & INT_CTLR_DTS)
  74. edac_pci_write_dword(dev, REG_INT_CTLR, val32);
  75. /* Clear CRC Error flag on link side A */
  76. edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
  77. if (val32 & LNK_CTRL_CRCERR_A)
  78. edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
  79. /* Clear CRC Error flag on link side B */
  80. edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
  81. if (val32 & LNK_CTRL_CRCERR_B)
  82. edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
  83. /*
  84. * Then enable all error detections.
  85. *
  86. * Setup Discard Timer Sync Flood Enable,
  87. * System Error Enable and Parity Error Enable.
  88. */
  89. edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
  90. val32 |= INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE;
  91. edac_pci_write_dword(dev, REG_INT_CTLR, val32);
  92. /* Enable overall SERR Error detection */
  93. edac_pci_read_dword(dev, REG_STS_CMD, &val32);
  94. val32 |= STS_CMD_SERREN;
  95. edac_pci_write_dword(dev, REG_STS_CMD, val32);
  96. /* Setup CRC Flood Enable for link side A */
  97. edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
  98. val32 |= LNK_CTRL_CRCFEN;
  99. edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
  100. /* Setup CRC Flood Enable for link side B */
  101. edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
  102. val32 |= LNK_CTRL_CRCFEN;
  103. edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
  104. }
  105. static void amd8131_pcix_exit(struct amd8131_dev_info *dev_info)
  106. {
  107. u32 val32;
  108. struct pci_dev *dev = dev_info->dev;
  109. /* Disable SERR, PERR and DTSE Error detection */
  110. edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
  111. val32 &= ~(INT_CTLR_PERR | INT_CTLR_SERR | INT_CTLR_DTSE);
  112. edac_pci_write_dword(dev, REG_INT_CTLR, val32);
  113. /* Disable overall System Error detection */
  114. edac_pci_read_dword(dev, REG_STS_CMD, &val32);
  115. val32 &= ~STS_CMD_SERREN;
  116. edac_pci_write_dword(dev, REG_STS_CMD, val32);
  117. /* Disable CRC Sync Flood on link side A */
  118. edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
  119. val32 &= ~LNK_CTRL_CRCFEN;
  120. edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
  121. /* Disable CRC Sync Flood on link side B */
  122. edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
  123. val32 &= ~LNK_CTRL_CRCFEN;
  124. edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
  125. }
  126. static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev)
  127. {
  128. struct amd8131_dev_info *dev_info = edac_dev->pvt_info;
  129. struct pci_dev *dev = dev_info->dev;
  130. u32 val32;
  131. /* Check PCI-X Bridge Memory Base-Limit Register for errors */
  132. edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
  133. if (val32 & MEM_LIMIT_MASK) {
  134. printk(KERN_INFO "Error(s) in mem limit register "
  135. "on %s bridge\n", dev_info->ctl_name);
  136. printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
  137. "RTA: %d, STA: %d, MDPE: %d\n",
  138. val32 & MEM_LIMIT_DPE,
  139. val32 & MEM_LIMIT_RSE,
  140. val32 & MEM_LIMIT_RMA,
  141. val32 & MEM_LIMIT_RTA,
  142. val32 & MEM_LIMIT_STA,
  143. val32 & MEM_LIMIT_MDPE);
  144. val32 |= MEM_LIMIT_MASK;
  145. edac_pci_write_dword(dev, REG_MEM_LIM, val32);
  146. edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
  147. }
  148. /* Check if Discard Timer timed out */
  149. edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
  150. if (val32 & INT_CTLR_DTS) {
  151. printk(KERN_INFO "Error(s) in interrupt and control register "
  152. "on %s bridge\n", dev_info->ctl_name);
  153. printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);
  154. val32 |= INT_CTLR_DTS;
  155. edac_pci_write_dword(dev, REG_INT_CTLR, val32);
  156. edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
  157. }
  158. /* Check if CRC error happens on link side A */
  159. edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
  160. if (val32 & LNK_CTRL_CRCERR_A) {
  161. printk(KERN_INFO "Error(s) in link conf and control register "
  162. "on %s bridge\n", dev_info->ctl_name);
  163. printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);
  164. val32 |= LNK_CTRL_CRCERR_A;
  165. edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);
  166. edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
  167. }
  168. /* Check if CRC error happens on link side B */
  169. edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
  170. if (val32 & LNK_CTRL_CRCERR_B) {
  171. printk(KERN_INFO "Error(s) in link conf and control register "
  172. "on %s bridge\n", dev_info->ctl_name);
  173. printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);
  174. val32 |= LNK_CTRL_CRCERR_B;
  175. edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);
  176. edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
  177. }
  178. }
  179. static struct amd8131_info amd8131_chipset = {
  180. .err_dev = PCI_DEVICE_ID_AMD_8131_APIC,
  181. .devices = amd8131_devices,
  182. .init = amd8131_pcix_init,
  183. .exit = amd8131_pcix_exit,
  184. .check = amd8131_pcix_check,
  185. };
  186. /*
  187. * There are 4 PCIX Bridges on ATCA-6101 that share the same PCI Device ID,
  188. * so amd8131_probe() would be called by kernel 4 times, with different
  189. * address of pci_dev for each of them each time.
  190. */
  191. static int amd8131_probe(struct pci_dev *dev, const struct pci_device_id *id)
  192. {
  193. struct amd8131_dev_info *dev_info;
  194. for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
  195. dev_info++)
  196. if (dev_info->devfn == dev->devfn)
  197. break;
  198. if (dev_info->inst == NO_BRIDGE) /* should never happen */
  199. return -ENODEV;
  200. /*
  201. * We can't call pci_get_device() as we are used to do because
  202. * there are 4 of them but pci_dev_get() instead.
  203. */
  204. dev_info->dev = pci_dev_get(dev);
  205. if (pci_enable_device(dev_info->dev)) {
  206. pci_dev_put(dev_info->dev);
  207. printk(KERN_ERR "failed to enable:"
  208. "vendor %x, device %x, devfn %x, name %s\n",
  209. PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
  210. dev_info->devfn, dev_info->ctl_name);
  211. return -ENODEV;
  212. }
  213. /*
  214. * we do not allocate extra private structure for
  215. * edac_pci_ctl_info, but make use of existing
  216. * one instead.
  217. */
  218. dev_info->edac_idx = edac_pci_alloc_index();
  219. dev_info->edac_dev = edac_pci_alloc_ctl_info(0, dev_info->ctl_name);
  220. if (!dev_info->edac_dev)
  221. return -ENOMEM;
  222. dev_info->edac_dev->pvt_info = dev_info;
  223. dev_info->edac_dev->dev = &dev_info->dev->dev;
  224. dev_info->edac_dev->mod_name = AMD8131_EDAC_MOD_STR;
  225. dev_info->edac_dev->ctl_name = dev_info->ctl_name;
  226. dev_info->edac_dev->dev_name = dev_name(&dev_info->dev->dev);
  227. if (edac_op_state == EDAC_OPSTATE_POLL)
  228. dev_info->edac_dev->edac_check = amd8131_chipset.check;
  229. if (amd8131_chipset.init)
  230. amd8131_chipset.init(dev_info);
  231. if (edac_pci_add_device(dev_info->edac_dev, dev_info->edac_idx) > 0) {
  232. printk(KERN_ERR "failed edac_pci_add_device() for %s\n",
  233. dev_info->ctl_name);
  234. edac_pci_free_ctl_info(dev_info->edac_dev);
  235. return -ENODEV;
  236. }
  237. printk(KERN_INFO "added one device on AMD8131 "
  238. "vendor %x, device %x, devfn %x, name %s\n",
  239. PCI_VENDOR_ID_AMD, amd8131_chipset.err_dev,
  240. dev_info->devfn, dev_info->ctl_name);
  241. return 0;
  242. }
  243. static void amd8131_remove(struct pci_dev *dev)
  244. {
  245. struct amd8131_dev_info *dev_info;
  246. for (dev_info = amd8131_chipset.devices; dev_info->inst != NO_BRIDGE;
  247. dev_info++)
  248. if (dev_info->devfn == dev->devfn)
  249. break;
  250. if (dev_info->inst == NO_BRIDGE) /* should never happen */
  251. return;
  252. if (dev_info->edac_dev) {
  253. edac_pci_del_device(dev_info->edac_dev->dev);
  254. edac_pci_free_ctl_info(dev_info->edac_dev);
  255. }
  256. if (amd8131_chipset.exit)
  257. amd8131_chipset.exit(dev_info);
  258. pci_dev_put(dev_info->dev);
  259. }
  260. static const struct pci_device_id amd8131_edac_pci_tbl[] = {
  261. {
  262. PCI_VEND_DEV(AMD, 8131_BRIDGE),
  263. .subvendor = PCI_ANY_ID,
  264. .subdevice = PCI_ANY_ID,
  265. .class = 0,
  266. .class_mask = 0,
  267. .driver_data = 0,
  268. },
  269. {
  270. 0,
  271. } /* table is NULL-terminated */
  272. };
  273. MODULE_DEVICE_TABLE(pci, amd8131_edac_pci_tbl);
  274. static struct pci_driver amd8131_edac_driver = {
  275. .name = AMD8131_EDAC_MOD_STR,
  276. .probe = amd8131_probe,
  277. .remove = amd8131_remove,
  278. .id_table = amd8131_edac_pci_tbl,
  279. };
  280. static int __init amd8131_edac_init(void)
  281. {
  282. printk(KERN_INFO "AMD8131 EDAC driver " AMD8131_EDAC_REVISION "\n");
  283. printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
  284. /* Only POLL mode supported so far */
  285. edac_op_state = EDAC_OPSTATE_POLL;
  286. return pci_register_driver(&amd8131_edac_driver);
  287. }
  288. static void __exit amd8131_edac_exit(void)
  289. {
  290. pci_unregister_driver(&amd8131_edac_driver);
  291. }
  292. module_init(amd8131_edac_init);
  293. module_exit(amd8131_edac_exit);
  294. MODULE_LICENSE("GPL");
  295. MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
  296. MODULE_DESCRIPTION("AMD8131 HyperTransport PCI-X Tunnel EDAC kernel module");