altera_edac.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2017-2018, Intel Corporation
  4. * Copyright (C) 2015 Altera Corporation
  5. */
  6. #ifndef _ALTERA_EDAC_H
  7. #define _ALTERA_EDAC_H
  8. #include <linux/arm-smccc.h>
  9. #include <linux/edac.h>
  10. #include <linux/types.h>
  11. /* SDRAM Controller CtrlCfg Register */
  12. #define CV_CTLCFG_OFST 0x00
  13. /* SDRAM Controller CtrlCfg Register Bit Masks */
  14. #define CV_CTLCFG_ECC_EN 0x400
  15. #define CV_CTLCFG_ECC_CORR_EN 0x800
  16. #define CV_CTLCFG_GEN_SB_ERR 0x2000
  17. #define CV_CTLCFG_GEN_DB_ERR 0x4000
  18. #define CV_CTLCFG_ECC_AUTO_EN (CV_CTLCFG_ECC_EN)
  19. /* SDRAM Controller Address Width Register */
  20. #define CV_DRAMADDRW_OFST 0x2C
  21. /* SDRAM Controller Address Widths Field Register */
  22. #define DRAMADDRW_COLBIT_MASK 0x001F
  23. #define DRAMADDRW_COLBIT_SHIFT 0
  24. #define DRAMADDRW_ROWBIT_MASK 0x03E0
  25. #define DRAMADDRW_ROWBIT_SHIFT 5
  26. #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
  27. #define CV_DRAMADDRW_BANKBIT_SHIFT 10
  28. #define CV_DRAMADDRW_CSBIT_MASK 0xE000
  29. #define CV_DRAMADDRW_CSBIT_SHIFT 13
  30. /* SDRAM Controller Interface Data Width Register */
  31. #define CV_DRAMIFWIDTH_OFST 0x30
  32. /* SDRAM Controller Interface Data Width Defines */
  33. #define CV_DRAMIFWIDTH_16B_ECC 24
  34. #define CV_DRAMIFWIDTH_32B_ECC 40
  35. /* SDRAM Controller DRAM Status Register */
  36. #define CV_DRAMSTS_OFST 0x38
  37. /* SDRAM Controller DRAM Status Register Bit Masks */
  38. #define CV_DRAMSTS_SBEERR 0x04
  39. #define CV_DRAMSTS_DBEERR 0x08
  40. #define CV_DRAMSTS_CORR_DROP 0x10
  41. /* SDRAM Controller DRAM IRQ Register */
  42. #define CV_DRAMINTR_OFST 0x3C
  43. /* SDRAM Controller DRAM IRQ Register Bit Masks */
  44. #define CV_DRAMINTR_INTREN 0x01
  45. #define CV_DRAMINTR_SBEMASK 0x02
  46. #define CV_DRAMINTR_DBEMASK 0x04
  47. #define CV_DRAMINTR_CORRDROPMASK 0x08
  48. #define CV_DRAMINTR_INTRCLR 0x10
  49. /* SDRAM Controller Single Bit Error Count Register */
  50. #define CV_SBECOUNT_OFST 0x40
  51. /* SDRAM Controller Double Bit Error Count Register */
  52. #define CV_DBECOUNT_OFST 0x44
  53. /* SDRAM Controller ECC Error Address Register */
  54. #define CV_ERRADDR_OFST 0x48
  55. /*-----------------------------------------*/
  56. /* SDRAM Controller EccCtrl Register */
  57. #define A10_ECCCTRL1_OFST 0x00
  58. /* SDRAM Controller EccCtrl Register Bit Masks */
  59. #define A10_ECCCTRL1_ECC_EN 0x001
  60. #define A10_ECCCTRL1_CNT_RST 0x010
  61. #define A10_ECCCTRL1_AWB_CNT_RST 0x100
  62. #define A10_ECC_CNT_RESET_MASK (A10_ECCCTRL1_CNT_RST | \
  63. A10_ECCCTRL1_AWB_CNT_RST)
  64. /* SDRAM Controller Address Width Register */
  65. #define CV_DRAMADDRW 0xFFC2502C
  66. #define A10_DRAMADDRW 0xFFCFA0A8
  67. #define S10_DRAMADDRW 0xF80110E0
  68. /* SDRAM Controller Address Widths Field Register */
  69. #define DRAMADDRW_COLBIT_MASK 0x001F
  70. #define DRAMADDRW_COLBIT_SHIFT 0
  71. #define DRAMADDRW_ROWBIT_MASK 0x03E0
  72. #define DRAMADDRW_ROWBIT_SHIFT 5
  73. #define CV_DRAMADDRW_BANKBIT_MASK 0x1C00
  74. #define CV_DRAMADDRW_BANKBIT_SHIFT 10
  75. #define CV_DRAMADDRW_CSBIT_MASK 0xE000
  76. #define CV_DRAMADDRW_CSBIT_SHIFT 13
  77. #define A10_DRAMADDRW_BANKBIT_MASK 0x3C00
  78. #define A10_DRAMADDRW_BANKBIT_SHIFT 10
  79. #define A10_DRAMADDRW_GRPBIT_MASK 0xC000
  80. #define A10_DRAMADDRW_GRPBIT_SHIFT 14
  81. #define A10_DRAMADDRW_CSBIT_MASK 0x70000
  82. #define A10_DRAMADDRW_CSBIT_SHIFT 16
  83. /* SDRAM Controller Interface Data Width Register */
  84. #define CV_DRAMIFWIDTH 0xFFC25030
  85. #define A10_DRAMIFWIDTH 0xFFCFB008
  86. #define S10_DRAMIFWIDTH 0xF8011008
  87. /* SDRAM Controller Interface Data Width Defines */
  88. #define CV_DRAMIFWIDTH_16B_ECC 24
  89. #define CV_DRAMIFWIDTH_32B_ECC 40
  90. #define A10_DRAMIFWIDTH_16B 0x0
  91. #define A10_DRAMIFWIDTH_32B 0x1
  92. #define A10_DRAMIFWIDTH_64B 0x2
  93. /* SDRAM Controller DRAM IRQ Register */
  94. #define A10_ERRINTEN_OFST 0x10
  95. /* SDRAM Controller DRAM IRQ Register Bit Masks */
  96. #define A10_ERRINTEN_SERRINTEN 0x01
  97. #define A10_ERRINTEN_DERRINTEN 0x02
  98. #define A10_ECC_IRQ_EN_MASK (A10_ERRINTEN_SERRINTEN | \
  99. A10_ERRINTEN_DERRINTEN)
  100. /* SDRAM Interrupt Mode Register */
  101. #define A10_INTMODE_OFST 0x1C
  102. #define A10_INTMODE_SB_INT 1
  103. /* SDRAM Controller Error Status Register */
  104. #define A10_INTSTAT_OFST 0x20
  105. /* SDRAM Controller Error Status Register Bit Masks */
  106. #define A10_INTSTAT_SBEERR 0x01
  107. #define A10_INTSTAT_DBEERR 0x02
  108. /* SDRAM Controller ECC Error Address Register */
  109. #define A10_DERRADDR_OFST 0x2C
  110. #define A10_SERRADDR_OFST 0x30
  111. /* SDRAM Controller ECC Diagnostic Register */
  112. #define A10_DIAGINTTEST_OFST 0x24
  113. #define A10_DIAGINT_TSERRA_MASK 0x0001
  114. #define A10_DIAGINT_TDERRA_MASK 0x0100
  115. #define A10_SBERR_IRQ 34
  116. #define A10_DBERR_IRQ 32
  117. /* SDRAM Single Bit Error Count Compare Set Register */
  118. #define A10_SERRCNTREG_OFST 0x3C
  119. #define A10_SYMAN_INTMASK_CLR 0xFFD06098
  120. #define A10_INTMASK_CLR_OFST 0x10
  121. #define A10_DDR0_IRQ_MASK BIT(17)
  122. struct altr_sdram_prv_data {
  123. int ecc_ctrl_offset;
  124. int ecc_ctl_en_mask;
  125. int ecc_cecnt_offset;
  126. int ecc_uecnt_offset;
  127. int ecc_stat_offset;
  128. int ecc_stat_ce_mask;
  129. int ecc_stat_ue_mask;
  130. int ecc_saddr_offset;
  131. int ecc_daddr_offset;
  132. int ecc_irq_en_offset;
  133. int ecc_irq_en_mask;
  134. int ecc_irq_clr_offset;
  135. int ecc_irq_clr_mask;
  136. int ecc_cnt_rst_offset;
  137. int ecc_cnt_rst_mask;
  138. struct edac_dev_sysfs_attribute *eccmgr_sysfs_attr;
  139. int ecc_enable_mask;
  140. int ce_set_mask;
  141. int ue_set_mask;
  142. int ce_ue_trgr_offset;
  143. };
  144. /* Altera SDRAM Memory Controller data */
  145. struct altr_sdram_mc_data {
  146. struct regmap *mc_vbase;
  147. int sb_irq;
  148. int db_irq;
  149. const struct altr_sdram_prv_data *data;
  150. };
  151. /************************** EDAC Device Defines **************************/
  152. /***** General Device Trigger Defines *****/
  153. #define ALTR_UE_TRIGGER_CHAR 'U' /* Trigger for UE */
  154. #define ALTR_TRIGGER_READ_WRD_CNT 32 /* Line size x 4 */
  155. #define ALTR_TRIG_OCRAM_BYTE_SIZE 128 /* Line size x 4 */
  156. #define ALTR_TRIG_L2C_BYTE_SIZE 4096 /* Full Page */
  157. /******* Cyclone5 and Arria5 Defines *******/
  158. /* OCRAM ECC Management Group Defines */
  159. #define ALTR_MAN_GRP_OCRAM_ECC_OFFSET 0x04
  160. #define ALTR_OCR_ECC_REG_OFFSET 0x00
  161. #define ALTR_OCR_ECC_EN BIT(0)
  162. #define ALTR_OCR_ECC_INJS BIT(1)
  163. #define ALTR_OCR_ECC_INJD BIT(2)
  164. #define ALTR_OCR_ECC_SERR BIT(3)
  165. #define ALTR_OCR_ECC_DERR BIT(4)
  166. /* L2 ECC Management Group Defines */
  167. #define ALTR_MAN_GRP_L2_ECC_OFFSET 0x00
  168. #define ALTR_L2_ECC_REG_OFFSET 0x00
  169. #define ALTR_L2_ECC_EN BIT(0)
  170. #define ALTR_L2_ECC_INJS BIT(1)
  171. #define ALTR_L2_ECC_INJD BIT(2)
  172. /* Arria10 General ECC Block Module Defines */
  173. #define ALTR_A10_ECC_CTRL_OFST 0x08
  174. #define ALTR_A10_ECC_EN BIT(0)
  175. #define ALTR_A10_ECC_INITA BIT(16)
  176. #define ALTR_A10_ECC_INITB BIT(24)
  177. #define ALTR_A10_ECC_INITSTAT_OFST 0x0C
  178. #define ALTR_A10_ECC_INITCOMPLETEA BIT(0)
  179. #define ALTR_A10_ECC_INITCOMPLETEB BIT(8)
  180. #define ALTR_A10_ECC_ERRINTEN_OFST 0x10
  181. #define ALTR_A10_ECC_ERRINTENS_OFST 0x14
  182. #define ALTR_A10_ECC_ERRINTENR_OFST 0x18
  183. #define ALTR_A10_ECC_SERRINTEN BIT(0)
  184. #define ALTR_A10_ECC_INTMODE_OFST 0x1C
  185. #define ALTR_A10_ECC_INTMODE BIT(0)
  186. #define ALTR_A10_ECC_INTSTAT_OFST 0x20
  187. #define ALTR_A10_ECC_SERRPENA BIT(0)
  188. #define ALTR_A10_ECC_DERRPENA BIT(8)
  189. #define ALTR_A10_ECC_ERRPENA_MASK (ALTR_A10_ECC_SERRPENA | \
  190. ALTR_A10_ECC_DERRPENA)
  191. #define ALTR_A10_ECC_SERRPENB BIT(16)
  192. #define ALTR_A10_ECC_DERRPENB BIT(24)
  193. #define ALTR_A10_ECC_ERRPENB_MASK (ALTR_A10_ECC_SERRPENB | \
  194. ALTR_A10_ECC_DERRPENB)
  195. #define ALTR_A10_ECC_INTTEST_OFST 0x24
  196. #define ALTR_A10_ECC_TSERRA BIT(0)
  197. #define ALTR_A10_ECC_TDERRA BIT(8)
  198. #define ALTR_A10_ECC_TSERRB BIT(16)
  199. #define ALTR_A10_ECC_TDERRB BIT(24)
  200. /* ECC Manager Defines */
  201. #define A10_SYSMGR_ECC_INTMASK_SET_OFST 0x94
  202. #define A10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
  203. #define A10_SYSMGR_ECC_INTMASK_OCRAM BIT(1)
  204. #define A10_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9C
  205. #define A10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
  206. #define A10_SYSMGR_ECC_INTSTAT_L2 BIT(0)
  207. #define A10_SYSMGR_ECC_INTSTAT_OCRAM BIT(1)
  208. #define A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST 0xA8
  209. #define A10_SYSGMR_MPU_CLEAR_L2_ECC_SB BIT(15)
  210. #define A10_SYSGMR_MPU_CLEAR_L2_ECC_MB BIT(31)
  211. /* Arria 10 L2 ECC Management Group Defines */
  212. #define ALTR_A10_L2_ECC_CTL_OFST 0x0
  213. #define ALTR_A10_L2_ECC_EN_CTL BIT(0)
  214. #define ALTR_A10_L2_ECC_STATUS 0xFFD060A4
  215. #define ALTR_A10_L2_ECC_STAT_OFST 0xA4
  216. #define ALTR_A10_L2_ECC_SERR_PEND BIT(0)
  217. #define ALTR_A10_L2_ECC_MERR_PEND BIT(0)
  218. #define ALTR_A10_L2_ECC_CLR_OFST 0x4
  219. #define ALTR_A10_L2_ECC_SERR_CLR BIT(15)
  220. #define ALTR_A10_L2_ECC_MERR_CLR BIT(31)
  221. #define ALTR_A10_L2_ECC_INJ_OFST ALTR_A10_L2_ECC_CTL_OFST
  222. #define ALTR_A10_L2_ECC_CE_INJ_MASK 0x00000101
  223. #define ALTR_A10_L2_ECC_UE_INJ_MASK 0x00010101
  224. /* Arria 10 OCRAM ECC Management Group Defines */
  225. #define ALTR_A10_OCRAM_ECC_EN_CTL (BIT(1) | BIT(0))
  226. /* Arria 10 Ethernet ECC Management Group Defines */
  227. #define ALTR_A10_COMMON_ECC_EN_CTL BIT(0)
  228. /* Arria 10 SDMMC ECC Management Group Defines */
  229. #define ALTR_A10_SDMMC_IRQ_MASK (BIT(16) | BIT(15))
  230. /* A10 ECC Controller memory initialization timeout */
  231. #define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
  232. /************* Stratix10 Defines **************/
  233. #define ALTR_S10_ECC_CTRL_SDRAM_OFST 0x00
  234. #define ALTR_S10_ECC_EN BIT(0)
  235. #define ALTR_S10_ECC_ERRINTEN_OFST 0x10
  236. #define ALTR_S10_ECC_ERRINTENS_OFST 0x14
  237. #define ALTR_S10_ECC_ERRINTENR_OFST 0x18
  238. #define ALTR_S10_ECC_SERRINTEN BIT(0)
  239. #define ALTR_S10_ECC_INTMODE_OFST 0x1C
  240. #define ALTR_S10_ECC_INTMODE BIT(0)
  241. #define ALTR_S10_ECC_INTSTAT_OFST 0x20
  242. #define ALTR_S10_ECC_SERRPENA BIT(0)
  243. #define ALTR_S10_ECC_DERRPENA BIT(8)
  244. #define ALTR_S10_ECC_ERRPENA_MASK (ALTR_S10_ECC_SERRPENA | \
  245. ALTR_S10_ECC_DERRPENA)
  246. #define ALTR_S10_ECC_INTTEST_OFST 0x24
  247. #define ALTR_S10_ECC_TSERRA BIT(0)
  248. #define ALTR_S10_ECC_TDERRA BIT(8)
  249. #define ALTR_S10_ECC_TSERRB BIT(16)
  250. #define ALTR_S10_ECC_TDERRB BIT(24)
  251. #define ALTR_S10_DERR_ADDRA_OFST 0x2C
  252. /* Stratix10 ECC Manager Defines */
  253. #define S10_SYSMGR_ECC_INTMASK_CLR_OFST 0x98
  254. #define S10_SYSMGR_ECC_INTSTAT_DERR_OFST 0xA0
  255. /* Sticky registers for Uncorrected Errors */
  256. #define S10_SYSMGR_UE_VAL_OFST 0x220
  257. #define S10_SYSMGR_UE_ADDR_OFST 0x224
  258. #define S10_DDR0_IRQ_MASK BIT(16)
  259. #define S10_DBE_IRQ_MASK 0x3FFFE
  260. /* Define ECC Block Offsets for peripherals */
  261. #define ECC_BLK_ADDRESS_OFST 0x40
  262. #define ECC_BLK_RDATA0_OFST 0x44
  263. #define ECC_BLK_RDATA1_OFST 0x48
  264. #define ECC_BLK_RDATA2_OFST 0x4C
  265. #define ECC_BLK_RDATA3_OFST 0x50
  266. #define ECC_BLK_WDATA0_OFST 0x54
  267. #define ECC_BLK_WDATA1_OFST 0x58
  268. #define ECC_BLK_WDATA2_OFST 0x5C
  269. #define ECC_BLK_WDATA3_OFST 0x60
  270. #define ECC_BLK_RECC0_OFST 0x64
  271. #define ECC_BLK_RECC1_OFST 0x68
  272. #define ECC_BLK_WECC0_OFST 0x6C
  273. #define ECC_BLK_WECC1_OFST 0x70
  274. #define ECC_BLK_DBYTECTRL_OFST 0x74
  275. #define ECC_BLK_ACCCTRL_OFST 0x78
  276. #define ECC_BLK_STARTACC_OFST 0x7C
  277. #define ECC_XACT_KICK 0x10000
  278. #define ECC_WORD_WRITE 0xFF
  279. #define ECC_WRITE_DOVR 0x101
  280. #define ECC_WRITE_EDOVR 0x103
  281. #define ECC_READ_EOVR 0x2
  282. #define ECC_READ_EDOVR 0x3
  283. struct altr_edac_device_dev;
  284. struct edac_device_prv_data {
  285. int (*setup)(struct altr_edac_device_dev *device);
  286. int ce_clear_mask;
  287. int ue_clear_mask;
  288. int irq_status_mask;
  289. void * (*alloc_mem)(size_t size, void **other);
  290. void (*free_mem)(void *p, size_t size, void *other);
  291. int ecc_enable_mask;
  292. int ecc_en_ofst;
  293. int ce_set_mask;
  294. int ue_set_mask;
  295. int set_err_ofst;
  296. irqreturn_t (*ecc_irq_handler)(int irq, void *dev_id);
  297. int trig_alloc_sz;
  298. const struct file_operations *inject_fops;
  299. bool panic;
  300. };
  301. struct altr_edac_device_dev {
  302. struct list_head next;
  303. void __iomem *base;
  304. int sb_irq;
  305. int db_irq;
  306. const struct edac_device_prv_data *data;
  307. struct dentry *debugfs_dir;
  308. char *edac_dev_name;
  309. struct altr_arria10_edac *edac;
  310. struct edac_device_ctl_info *edac_dev;
  311. struct device ddev;
  312. int edac_idx;
  313. };
  314. struct altr_arria10_edac {
  315. struct device *dev;
  316. struct regmap *ecc_mgr_map;
  317. int sb_irq;
  318. int db_irq;
  319. struct irq_domain *domain;
  320. struct irq_chip irq_chip;
  321. struct list_head a10_ecc_devices;
  322. struct notifier_block panic_notifier;
  323. };
  324. #endif /* #ifndef _ALTERA_EDAC_H */