altera_edac.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
  4. * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
  5. * Copyright 2011-2012 Calxeda, Inc.
  6. */
  7. #include <asm/cacheflush.h>
  8. #include <linux/ctype.h>
  9. #include <linux/delay.h>
  10. #include <linux/edac.h>
  11. #include <linux/firmware/intel/stratix10-smc.h>
  12. #include <linux/genalloc.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/irqchip/chained_irq.h>
  15. #include <linux/kernel.h>
  16. #include <linux/mfd/altera-sysmgr.h>
  17. #include <linux/mfd/syscon.h>
  18. #include <linux/notifier.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_irq.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/regmap.h>
  24. #include <linux/types.h>
  25. #include <linux/uaccess.h>
  26. #include "altera_edac.h"
  27. #include "edac_module.h"
  28. #define EDAC_MOD_STR "altera_edac"
  29. #define EDAC_DEVICE "Altera"
  30. #ifdef CONFIG_EDAC_ALTERA_SDRAM
  31. static const struct altr_sdram_prv_data c5_data = {
  32. .ecc_ctrl_offset = CV_CTLCFG_OFST,
  33. .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
  34. .ecc_stat_offset = CV_DRAMSTS_OFST,
  35. .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
  36. .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
  37. .ecc_saddr_offset = CV_ERRADDR_OFST,
  38. .ecc_daddr_offset = CV_ERRADDR_OFST,
  39. .ecc_cecnt_offset = CV_SBECOUNT_OFST,
  40. .ecc_uecnt_offset = CV_DBECOUNT_OFST,
  41. .ecc_irq_en_offset = CV_DRAMINTR_OFST,
  42. .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
  43. .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
  44. .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
  45. .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
  46. .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
  47. .ce_ue_trgr_offset = CV_CTLCFG_OFST,
  48. .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
  49. .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
  50. };
  51. static const struct altr_sdram_prv_data a10_data = {
  52. .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
  53. .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
  54. .ecc_stat_offset = A10_INTSTAT_OFST,
  55. .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
  56. .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
  57. .ecc_saddr_offset = A10_SERRADDR_OFST,
  58. .ecc_daddr_offset = A10_DERRADDR_OFST,
  59. .ecc_irq_en_offset = A10_ERRINTEN_OFST,
  60. .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
  61. .ecc_irq_clr_offset = A10_INTSTAT_OFST,
  62. .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
  63. .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
  64. .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
  65. .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
  66. .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
  67. .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
  68. };
  69. /*********************** EDAC Memory Controller Functions ****************/
  70. /* The SDRAM controller uses the EDAC Memory Controller framework. */
  71. static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
  72. {
  73. struct mem_ctl_info *mci = dev_id;
  74. struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  75. const struct altr_sdram_prv_data *priv = drvdata->data;
  76. u32 status, err_count = 1, err_addr;
  77. regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
  78. if (status & priv->ecc_stat_ue_mask) {
  79. regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
  80. &err_addr);
  81. if (priv->ecc_uecnt_offset)
  82. regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
  83. &err_count);
  84. panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
  85. err_count, err_addr);
  86. }
  87. if (status & priv->ecc_stat_ce_mask) {
  88. regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
  89. &err_addr);
  90. if (priv->ecc_uecnt_offset)
  91. regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
  92. &err_count);
  93. edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
  94. err_addr >> PAGE_SHIFT,
  95. err_addr & ~PAGE_MASK, 0,
  96. 0, 0, -1, mci->ctl_name, "");
  97. /* Clear IRQ to resume */
  98. regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
  99. priv->ecc_irq_clr_mask);
  100. return IRQ_HANDLED;
  101. }
  102. return IRQ_NONE;
  103. }
  104. static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
  105. const char __user *data,
  106. size_t count, loff_t *ppos)
  107. {
  108. struct mem_ctl_info *mci = file->private_data;
  109. struct altr_sdram_mc_data *drvdata = mci->pvt_info;
  110. const struct altr_sdram_prv_data *priv = drvdata->data;
  111. u32 *ptemp;
  112. dma_addr_t dma_handle;
  113. u32 reg, read_reg;
  114. ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
  115. if (!ptemp) {
  116. dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
  117. edac_printk(KERN_ERR, EDAC_MC,
  118. "Inject: Buffer Allocation error\n");
  119. return -ENOMEM;
  120. }
  121. regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
  122. &read_reg);
  123. read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
  124. /* Error are injected by writing a word while the SBE or DBE
  125. * bit in the CTLCFG register is set. Reading the word will
  126. * trigger the SBE or DBE error and the corresponding IRQ.
  127. */
  128. if (count == 3) {
  129. edac_printk(KERN_ALERT, EDAC_MC,
  130. "Inject Double bit error\n");
  131. local_irq_disable();
  132. regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
  133. (read_reg | priv->ue_set_mask));
  134. local_irq_enable();
  135. } else {
  136. edac_printk(KERN_ALERT, EDAC_MC,
  137. "Inject Single bit error\n");
  138. local_irq_disable();
  139. regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
  140. (read_reg | priv->ce_set_mask));
  141. local_irq_enable();
  142. }
  143. ptemp[0] = 0x5A5A5A5A;
  144. ptemp[1] = 0xA5A5A5A5;
  145. /* Clear the error injection bits */
  146. regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
  147. /* Ensure it has been written out */
  148. wmb();
  149. /*
  150. * To trigger the error, we need to read the data back
  151. * (the data was written with errors above).
  152. * The READ_ONCE macros and printk are used to prevent the
  153. * the compiler optimizing these reads out.
  154. */
  155. reg = READ_ONCE(ptemp[0]);
  156. read_reg = READ_ONCE(ptemp[1]);
  157. /* Force Read */
  158. rmb();
  159. edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
  160. reg, read_reg);
  161. dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
  162. return count;
  163. }
  164. static const struct file_operations altr_sdr_mc_debug_inject_fops = {
  165. .open = simple_open,
  166. .write = altr_sdr_mc_err_inject_write,
  167. .llseek = generic_file_llseek,
  168. };
  169. static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
  170. {
  171. if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
  172. return;
  173. if (!mci->debugfs)
  174. return;
  175. edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
  176. &altr_sdr_mc_debug_inject_fops);
  177. }
  178. /* Get total memory size from Open Firmware DTB */
  179. static unsigned long get_total_mem(void)
  180. {
  181. struct device_node *np = NULL;
  182. struct resource res;
  183. int ret;
  184. unsigned long total_mem = 0;
  185. for_each_node_by_type(np, "memory") {
  186. ret = of_address_to_resource(np, 0, &res);
  187. if (ret)
  188. continue;
  189. total_mem += resource_size(&res);
  190. }
  191. edac_dbg(0, "total_mem 0x%lx\n", total_mem);
  192. return total_mem;
  193. }
  194. static const struct of_device_id altr_sdram_ctrl_of_match[] = {
  195. { .compatible = "altr,sdram-edac", .data = &c5_data},
  196. { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
  197. {},
  198. };
  199. MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
  200. static int a10_init(struct regmap *mc_vbase)
  201. {
  202. if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
  203. A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
  204. edac_printk(KERN_ERR, EDAC_MC,
  205. "Error setting SB IRQ mode\n");
  206. return -ENODEV;
  207. }
  208. if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
  209. edac_printk(KERN_ERR, EDAC_MC,
  210. "Error setting trigger count\n");
  211. return -ENODEV;
  212. }
  213. return 0;
  214. }
  215. static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
  216. {
  217. void __iomem *sm_base;
  218. int ret = 0;
  219. if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
  220. dev_name(&pdev->dev))) {
  221. edac_printk(KERN_ERR, EDAC_MC,
  222. "Unable to request mem region\n");
  223. return -EBUSY;
  224. }
  225. sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
  226. if (!sm_base) {
  227. edac_printk(KERN_ERR, EDAC_MC,
  228. "Unable to ioremap device\n");
  229. ret = -ENOMEM;
  230. goto release;
  231. }
  232. iowrite32(mask, sm_base);
  233. iounmap(sm_base);
  234. release:
  235. release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
  236. return ret;
  237. }
  238. static int altr_sdram_probe(struct platform_device *pdev)
  239. {
  240. const struct of_device_id *id;
  241. struct edac_mc_layer layers[2];
  242. struct mem_ctl_info *mci;
  243. struct altr_sdram_mc_data *drvdata;
  244. const struct altr_sdram_prv_data *priv;
  245. struct regmap *mc_vbase;
  246. struct dimm_info *dimm;
  247. u32 read_reg;
  248. int irq, irq2, res = 0;
  249. unsigned long mem_size, irqflags = 0;
  250. id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
  251. if (!id)
  252. return -ENODEV;
  253. /* Grab the register range from the sdr controller in device tree */
  254. mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  255. "altr,sdr-syscon");
  256. if (IS_ERR(mc_vbase)) {
  257. edac_printk(KERN_ERR, EDAC_MC,
  258. "regmap for altr,sdr-syscon lookup failed.\n");
  259. return -ENODEV;
  260. }
  261. /* Check specific dependencies for the module */
  262. priv = of_match_node(altr_sdram_ctrl_of_match,
  263. pdev->dev.of_node)->data;
  264. /* Validate the SDRAM controller has ECC enabled */
  265. if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
  266. ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
  267. edac_printk(KERN_ERR, EDAC_MC,
  268. "No ECC/ECC disabled [0x%08X]\n", read_reg);
  269. return -ENODEV;
  270. }
  271. /* Grab memory size from device tree. */
  272. mem_size = get_total_mem();
  273. if (!mem_size) {
  274. edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
  275. return -ENODEV;
  276. }
  277. /* Ensure the SDRAM Interrupt is disabled */
  278. if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
  279. priv->ecc_irq_en_mask, 0)) {
  280. edac_printk(KERN_ERR, EDAC_MC,
  281. "Error disabling SDRAM ECC IRQ\n");
  282. return -ENODEV;
  283. }
  284. /* Toggle to clear the SDRAM Error count */
  285. if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
  286. priv->ecc_cnt_rst_mask,
  287. priv->ecc_cnt_rst_mask)) {
  288. edac_printk(KERN_ERR, EDAC_MC,
  289. "Error clearing SDRAM ECC count\n");
  290. return -ENODEV;
  291. }
  292. if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
  293. priv->ecc_cnt_rst_mask, 0)) {
  294. edac_printk(KERN_ERR, EDAC_MC,
  295. "Error clearing SDRAM ECC count\n");
  296. return -ENODEV;
  297. }
  298. irq = platform_get_irq(pdev, 0);
  299. if (irq < 0) {
  300. edac_printk(KERN_ERR, EDAC_MC,
  301. "No irq %d in DT\n", irq);
  302. return irq;
  303. }
  304. /* Arria10 has a 2nd IRQ */
  305. irq2 = platform_get_irq(pdev, 1);
  306. layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
  307. layers[0].size = 1;
  308. layers[0].is_virt_csrow = true;
  309. layers[1].type = EDAC_MC_LAYER_CHANNEL;
  310. layers[1].size = 1;
  311. layers[1].is_virt_csrow = false;
  312. mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
  313. sizeof(struct altr_sdram_mc_data));
  314. if (!mci)
  315. return -ENOMEM;
  316. mci->pdev = &pdev->dev;
  317. drvdata = mci->pvt_info;
  318. drvdata->mc_vbase = mc_vbase;
  319. drvdata->data = priv;
  320. platform_set_drvdata(pdev, mci);
  321. if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
  322. edac_printk(KERN_ERR, EDAC_MC,
  323. "Unable to get managed device resource\n");
  324. res = -ENOMEM;
  325. goto free;
  326. }
  327. mci->mtype_cap = MEM_FLAG_DDR3;
  328. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
  329. mci->edac_cap = EDAC_FLAG_SECDED;
  330. mci->mod_name = EDAC_MOD_STR;
  331. mci->ctl_name = dev_name(&pdev->dev);
  332. mci->scrub_mode = SCRUB_SW_SRC;
  333. mci->dev_name = dev_name(&pdev->dev);
  334. dimm = *mci->dimms;
  335. dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
  336. dimm->grain = 8;
  337. dimm->dtype = DEV_X8;
  338. dimm->mtype = MEM_DDR3;
  339. dimm->edac_mode = EDAC_SECDED;
  340. res = edac_mc_add_mc(mci);
  341. if (res < 0)
  342. goto err;
  343. /* Only the Arria10 has separate IRQs */
  344. if (of_machine_is_compatible("altr,socfpga-arria10")) {
  345. /* Arria10 specific initialization */
  346. res = a10_init(mc_vbase);
  347. if (res < 0)
  348. goto err2;
  349. res = devm_request_irq(&pdev->dev, irq2,
  350. altr_sdram_mc_err_handler,
  351. IRQF_SHARED, dev_name(&pdev->dev), mci);
  352. if (res < 0) {
  353. edac_mc_printk(mci, KERN_ERR,
  354. "Unable to request irq %d\n", irq2);
  355. res = -ENODEV;
  356. goto err2;
  357. }
  358. res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
  359. if (res < 0)
  360. goto err2;
  361. irqflags = IRQF_SHARED;
  362. }
  363. res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
  364. irqflags, dev_name(&pdev->dev), mci);
  365. if (res < 0) {
  366. edac_mc_printk(mci, KERN_ERR,
  367. "Unable to request irq %d\n", irq);
  368. res = -ENODEV;
  369. goto err2;
  370. }
  371. /* Infrastructure ready - enable the IRQ */
  372. if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
  373. priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
  374. edac_mc_printk(mci, KERN_ERR,
  375. "Error enabling SDRAM ECC IRQ\n");
  376. res = -ENODEV;
  377. goto err2;
  378. }
  379. altr_sdr_mc_create_debugfs_nodes(mci);
  380. devres_close_group(&pdev->dev, NULL);
  381. return 0;
  382. err2:
  383. edac_mc_del_mc(&pdev->dev);
  384. err:
  385. devres_release_group(&pdev->dev, NULL);
  386. free:
  387. edac_mc_free(mci);
  388. edac_printk(KERN_ERR, EDAC_MC,
  389. "EDAC Probe Failed; Error %d\n", res);
  390. return res;
  391. }
  392. static int altr_sdram_remove(struct platform_device *pdev)
  393. {
  394. struct mem_ctl_info *mci = platform_get_drvdata(pdev);
  395. edac_mc_del_mc(&pdev->dev);
  396. edac_mc_free(mci);
  397. platform_set_drvdata(pdev, NULL);
  398. return 0;
  399. }
  400. /*
  401. * If you want to suspend, need to disable EDAC by removing it
  402. * from the device tree or defconfig.
  403. */
  404. #ifdef CONFIG_PM
  405. static int altr_sdram_prepare(struct device *dev)
  406. {
  407. pr_err("Suspend not allowed when EDAC is enabled.\n");
  408. return -EPERM;
  409. }
  410. static const struct dev_pm_ops altr_sdram_pm_ops = {
  411. .prepare = altr_sdram_prepare,
  412. };
  413. #endif
  414. static struct platform_driver altr_sdram_edac_driver = {
  415. .probe = altr_sdram_probe,
  416. .remove = altr_sdram_remove,
  417. .driver = {
  418. .name = "altr_sdram_edac",
  419. #ifdef CONFIG_PM
  420. .pm = &altr_sdram_pm_ops,
  421. #endif
  422. .of_match_table = altr_sdram_ctrl_of_match,
  423. },
  424. };
  425. module_platform_driver(altr_sdram_edac_driver);
  426. #endif /* CONFIG_EDAC_ALTERA_SDRAM */
  427. /************************* EDAC Parent Probe *************************/
  428. static const struct of_device_id altr_edac_device_of_match[];
  429. static const struct of_device_id altr_edac_of_match[] = {
  430. { .compatible = "altr,socfpga-ecc-manager" },
  431. {},
  432. };
  433. MODULE_DEVICE_TABLE(of, altr_edac_of_match);
  434. static int altr_edac_probe(struct platform_device *pdev)
  435. {
  436. of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
  437. NULL, &pdev->dev);
  438. return 0;
  439. }
  440. static struct platform_driver altr_edac_driver = {
  441. .probe = altr_edac_probe,
  442. .driver = {
  443. .name = "socfpga_ecc_manager",
  444. .of_match_table = altr_edac_of_match,
  445. },
  446. };
  447. module_platform_driver(altr_edac_driver);
  448. /************************* EDAC Device Functions *************************/
  449. /*
  450. * EDAC Device Functions (shared between various IPs).
  451. * The discrete memories use the EDAC Device framework. The probe
  452. * and error handling functions are very similar between memories
  453. * so they are shared. The memory allocation and freeing for EDAC
  454. * trigger testing are different for each memory.
  455. */
  456. static const struct edac_device_prv_data ocramecc_data;
  457. static const struct edac_device_prv_data l2ecc_data;
  458. static const struct edac_device_prv_data a10_ocramecc_data;
  459. static const struct edac_device_prv_data a10_l2ecc_data;
  460. static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
  461. {
  462. irqreturn_t ret_value = IRQ_NONE;
  463. struct edac_device_ctl_info *dci = dev_id;
  464. struct altr_edac_device_dev *drvdata = dci->pvt_info;
  465. const struct edac_device_prv_data *priv = drvdata->data;
  466. if (irq == drvdata->sb_irq) {
  467. if (priv->ce_clear_mask)
  468. writel(priv->ce_clear_mask, drvdata->base);
  469. edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
  470. ret_value = IRQ_HANDLED;
  471. } else if (irq == drvdata->db_irq) {
  472. if (priv->ue_clear_mask)
  473. writel(priv->ue_clear_mask, drvdata->base);
  474. edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
  475. panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
  476. ret_value = IRQ_HANDLED;
  477. } else {
  478. WARN_ON(1);
  479. }
  480. return ret_value;
  481. }
  482. static ssize_t altr_edac_device_trig(struct file *file,
  483. const char __user *user_buf,
  484. size_t count, loff_t *ppos)
  485. {
  486. u32 *ptemp, i, error_mask;
  487. int result = 0;
  488. u8 trig_type;
  489. unsigned long flags;
  490. struct edac_device_ctl_info *edac_dci = file->private_data;
  491. struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
  492. const struct edac_device_prv_data *priv = drvdata->data;
  493. void *generic_ptr = edac_dci->dev;
  494. if (!user_buf || get_user(trig_type, user_buf))
  495. return -EFAULT;
  496. if (!priv->alloc_mem)
  497. return -ENOMEM;
  498. /*
  499. * Note that generic_ptr is initialized to the device * but in
  500. * some alloc_functions, this is overridden and returns data.
  501. */
  502. ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
  503. if (!ptemp) {
  504. edac_printk(KERN_ERR, EDAC_DEVICE,
  505. "Inject: Buffer Allocation error\n");
  506. return -ENOMEM;
  507. }
  508. if (trig_type == ALTR_UE_TRIGGER_CHAR)
  509. error_mask = priv->ue_set_mask;
  510. else
  511. error_mask = priv->ce_set_mask;
  512. edac_printk(KERN_ALERT, EDAC_DEVICE,
  513. "Trigger Error Mask (0x%X)\n", error_mask);
  514. local_irq_save(flags);
  515. /* write ECC corrupted data out. */
  516. for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
  517. /* Read data so we're in the correct state */
  518. rmb();
  519. if (READ_ONCE(ptemp[i]))
  520. result = -1;
  521. /* Toggle Error bit (it is latched), leave ECC enabled */
  522. writel(error_mask, (drvdata->base + priv->set_err_ofst));
  523. writel(priv->ecc_enable_mask, (drvdata->base +
  524. priv->set_err_ofst));
  525. ptemp[i] = i;
  526. }
  527. /* Ensure it has been written out */
  528. wmb();
  529. local_irq_restore(flags);
  530. if (result)
  531. edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
  532. /* Read out written data. ECC error caused here */
  533. for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
  534. if (READ_ONCE(ptemp[i]) != i)
  535. edac_printk(KERN_ERR, EDAC_DEVICE,
  536. "Read doesn't match written data\n");
  537. if (priv->free_mem)
  538. priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
  539. return count;
  540. }
  541. static const struct file_operations altr_edac_device_inject_fops = {
  542. .open = simple_open,
  543. .write = altr_edac_device_trig,
  544. .llseek = generic_file_llseek,
  545. };
  546. static ssize_t altr_edac_a10_device_trig(struct file *file,
  547. const char __user *user_buf,
  548. size_t count, loff_t *ppos);
  549. static const struct file_operations altr_edac_a10_device_inject_fops = {
  550. .open = simple_open,
  551. .write = altr_edac_a10_device_trig,
  552. .llseek = generic_file_llseek,
  553. };
  554. static ssize_t altr_edac_a10_device_trig2(struct file *file,
  555. const char __user *user_buf,
  556. size_t count, loff_t *ppos);
  557. static const struct file_operations altr_edac_a10_device_inject2_fops = {
  558. .open = simple_open,
  559. .write = altr_edac_a10_device_trig2,
  560. .llseek = generic_file_llseek,
  561. };
  562. static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
  563. const struct edac_device_prv_data *priv)
  564. {
  565. struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
  566. if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
  567. return;
  568. drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
  569. if (!drvdata->debugfs_dir)
  570. return;
  571. if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
  572. drvdata->debugfs_dir, edac_dci,
  573. priv->inject_fops))
  574. debugfs_remove_recursive(drvdata->debugfs_dir);
  575. }
  576. static const struct of_device_id altr_edac_device_of_match[] = {
  577. #ifdef CONFIG_EDAC_ALTERA_L2C
  578. { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
  579. #endif
  580. #ifdef CONFIG_EDAC_ALTERA_OCRAM
  581. { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
  582. #endif
  583. {},
  584. };
  585. MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
  586. /*
  587. * altr_edac_device_probe()
  588. * This is a generic EDAC device driver that will support
  589. * various Altera memory devices such as the L2 cache ECC and
  590. * OCRAM ECC as well as the memories for other peripherals.
  591. * Module specific initialization is done by passing the
  592. * function index in the device tree.
  593. */
  594. static int altr_edac_device_probe(struct platform_device *pdev)
  595. {
  596. struct edac_device_ctl_info *dci;
  597. struct altr_edac_device_dev *drvdata;
  598. struct resource *r;
  599. int res = 0;
  600. struct device_node *np = pdev->dev.of_node;
  601. char *ecc_name = (char *)np->name;
  602. static int dev_instance;
  603. if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
  604. edac_printk(KERN_ERR, EDAC_DEVICE,
  605. "Unable to open devm\n");
  606. return -ENOMEM;
  607. }
  608. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  609. if (!r) {
  610. edac_printk(KERN_ERR, EDAC_DEVICE,
  611. "Unable to get mem resource\n");
  612. res = -ENODEV;
  613. goto fail;
  614. }
  615. if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
  616. dev_name(&pdev->dev))) {
  617. edac_printk(KERN_ERR, EDAC_DEVICE,
  618. "%s:Error requesting mem region\n", ecc_name);
  619. res = -EBUSY;
  620. goto fail;
  621. }
  622. dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
  623. 1, ecc_name, 1, 0, NULL, 0,
  624. dev_instance++);
  625. if (!dci) {
  626. edac_printk(KERN_ERR, EDAC_DEVICE,
  627. "%s: Unable to allocate EDAC device\n", ecc_name);
  628. res = -ENOMEM;
  629. goto fail;
  630. }
  631. drvdata = dci->pvt_info;
  632. dci->dev = &pdev->dev;
  633. platform_set_drvdata(pdev, dci);
  634. drvdata->edac_dev_name = ecc_name;
  635. drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
  636. if (!drvdata->base) {
  637. res = -ENOMEM;
  638. goto fail1;
  639. }
  640. /* Get driver specific data for this EDAC device */
  641. drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
  642. /* Check specific dependencies for the module */
  643. if (drvdata->data->setup) {
  644. res = drvdata->data->setup(drvdata);
  645. if (res)
  646. goto fail1;
  647. }
  648. drvdata->sb_irq = platform_get_irq(pdev, 0);
  649. res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
  650. altr_edac_device_handler,
  651. 0, dev_name(&pdev->dev), dci);
  652. if (res)
  653. goto fail1;
  654. drvdata->db_irq = platform_get_irq(pdev, 1);
  655. res = devm_request_irq(&pdev->dev, drvdata->db_irq,
  656. altr_edac_device_handler,
  657. 0, dev_name(&pdev->dev), dci);
  658. if (res)
  659. goto fail1;
  660. dci->mod_name = "Altera ECC Manager";
  661. dci->dev_name = drvdata->edac_dev_name;
  662. res = edac_device_add_device(dci);
  663. if (res)
  664. goto fail1;
  665. altr_create_edacdev_dbgfs(dci, drvdata->data);
  666. devres_close_group(&pdev->dev, NULL);
  667. return 0;
  668. fail1:
  669. edac_device_free_ctl_info(dci);
  670. fail:
  671. devres_release_group(&pdev->dev, NULL);
  672. edac_printk(KERN_ERR, EDAC_DEVICE,
  673. "%s:Error setting up EDAC device: %d\n", ecc_name, res);
  674. return res;
  675. }
  676. static int altr_edac_device_remove(struct platform_device *pdev)
  677. {
  678. struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
  679. struct altr_edac_device_dev *drvdata = dci->pvt_info;
  680. debugfs_remove_recursive(drvdata->debugfs_dir);
  681. edac_device_del_device(&pdev->dev);
  682. edac_device_free_ctl_info(dci);
  683. return 0;
  684. }
  685. static struct platform_driver altr_edac_device_driver = {
  686. .probe = altr_edac_device_probe,
  687. .remove = altr_edac_device_remove,
  688. .driver = {
  689. .name = "altr_edac_device",
  690. .of_match_table = altr_edac_device_of_match,
  691. },
  692. };
  693. module_platform_driver(altr_edac_device_driver);
  694. /******************* Arria10 Device ECC Shared Functions *****************/
  695. /*
  696. * Test for memory's ECC dependencies upon entry because platform specific
  697. * startup should have initialized the memory and enabled the ECC.
  698. * Can't turn on ECC here because accessing un-initialized memory will
  699. * cause CE/UE errors possibly causing an ABORT.
  700. */
  701. static int __maybe_unused
  702. altr_check_ecc_deps(struct altr_edac_device_dev *device)
  703. {
  704. void __iomem *base = device->base;
  705. const struct edac_device_prv_data *prv = device->data;
  706. if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
  707. return 0;
  708. edac_printk(KERN_ERR, EDAC_DEVICE,
  709. "%s: No ECC present or ECC disabled.\n",
  710. device->edac_dev_name);
  711. return -ENODEV;
  712. }
  713. static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
  714. {
  715. struct altr_edac_device_dev *dci = dev_id;
  716. void __iomem *base = dci->base;
  717. if (irq == dci->sb_irq) {
  718. writel(ALTR_A10_ECC_SERRPENA,
  719. base + ALTR_A10_ECC_INTSTAT_OFST);
  720. edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
  721. return IRQ_HANDLED;
  722. } else if (irq == dci->db_irq) {
  723. writel(ALTR_A10_ECC_DERRPENA,
  724. base + ALTR_A10_ECC_INTSTAT_OFST);
  725. edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
  726. if (dci->data->panic)
  727. panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
  728. return IRQ_HANDLED;
  729. }
  730. WARN_ON(1);
  731. return IRQ_NONE;
  732. }
  733. /******************* Arria10 Memory Buffer Functions *********************/
  734. static inline int a10_get_irq_mask(struct device_node *np)
  735. {
  736. int irq;
  737. const u32 *handle = of_get_property(np, "interrupts", NULL);
  738. if (!handle)
  739. return -ENODEV;
  740. irq = be32_to_cpup(handle);
  741. return irq;
  742. }
  743. static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
  744. {
  745. u32 value = readl(ioaddr);
  746. value |= bit_mask;
  747. writel(value, ioaddr);
  748. }
  749. static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
  750. {
  751. u32 value = readl(ioaddr);
  752. value &= ~bit_mask;
  753. writel(value, ioaddr);
  754. }
  755. static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
  756. {
  757. u32 value = readl(ioaddr);
  758. return (value & bit_mask) ? 1 : 0;
  759. }
  760. /*
  761. * This function uses the memory initialization block in the Arria10 ECC
  762. * controller to initialize/clear the entire memory data and ECC data.
  763. */
  764. static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
  765. {
  766. int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
  767. u32 init_mask, stat_mask, clear_mask;
  768. int ret = 0;
  769. if (port) {
  770. init_mask = ALTR_A10_ECC_INITB;
  771. stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
  772. clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
  773. } else {
  774. init_mask = ALTR_A10_ECC_INITA;
  775. stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
  776. clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
  777. }
  778. ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
  779. while (limit--) {
  780. if (ecc_test_bits(stat_mask,
  781. (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
  782. break;
  783. udelay(1);
  784. }
  785. if (limit < 0)
  786. ret = -EBUSY;
  787. /* Clear any pending ECC interrupts */
  788. writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
  789. return ret;
  790. }
  791. static __init int __maybe_unused
  792. altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
  793. u32 ecc_ctrl_en_mask, bool dual_port)
  794. {
  795. int ret = 0;
  796. void __iomem *ecc_block_base;
  797. struct regmap *ecc_mgr_map;
  798. char *ecc_name;
  799. struct device_node *np_eccmgr;
  800. ecc_name = (char *)np->name;
  801. /* Get the ECC Manager - parent of the device EDACs */
  802. np_eccmgr = of_get_parent(np);
  803. ecc_mgr_map =
  804. altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
  805. "altr,sysmgr-syscon");
  806. of_node_put(np_eccmgr);
  807. if (IS_ERR(ecc_mgr_map)) {
  808. edac_printk(KERN_ERR, EDAC_DEVICE,
  809. "Unable to get syscon altr,sysmgr-syscon\n");
  810. return -ENODEV;
  811. }
  812. /* Map the ECC Block */
  813. ecc_block_base = of_iomap(np, 0);
  814. if (!ecc_block_base) {
  815. edac_printk(KERN_ERR, EDAC_DEVICE,
  816. "Unable to map %s ECC block\n", ecc_name);
  817. return -ENODEV;
  818. }
  819. /* Disable ECC */
  820. regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
  821. writel(ALTR_A10_ECC_SERRINTEN,
  822. (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
  823. ecc_clear_bits(ecc_ctrl_en_mask,
  824. (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
  825. /* Ensure all writes complete */
  826. wmb();
  827. /* Use HW initialization block to initialize memory for ECC */
  828. ret = altr_init_memory_port(ecc_block_base, 0);
  829. if (ret) {
  830. edac_printk(KERN_ERR, EDAC_DEVICE,
  831. "ECC: cannot init %s PORTA memory\n", ecc_name);
  832. goto out;
  833. }
  834. if (dual_port) {
  835. ret = altr_init_memory_port(ecc_block_base, 1);
  836. if (ret) {
  837. edac_printk(KERN_ERR, EDAC_DEVICE,
  838. "ECC: cannot init %s PORTB memory\n",
  839. ecc_name);
  840. goto out;
  841. }
  842. }
  843. /* Interrupt mode set to every SBERR */
  844. regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
  845. ALTR_A10_ECC_INTMODE);
  846. /* Enable ECC */
  847. ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
  848. ALTR_A10_ECC_CTRL_OFST));
  849. writel(ALTR_A10_ECC_SERRINTEN,
  850. (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
  851. regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
  852. /* Ensure all writes complete */
  853. wmb();
  854. out:
  855. iounmap(ecc_block_base);
  856. return ret;
  857. }
  858. static int validate_parent_available(struct device_node *np);
  859. static const struct of_device_id altr_edac_a10_device_of_match[];
  860. static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
  861. {
  862. int irq;
  863. struct device_node *child, *np;
  864. np = of_find_compatible_node(NULL, NULL,
  865. "altr,socfpga-a10-ecc-manager");
  866. if (!np) {
  867. edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
  868. return -ENODEV;
  869. }
  870. for_each_child_of_node(np, child) {
  871. const struct of_device_id *pdev_id;
  872. const struct edac_device_prv_data *prv;
  873. if (!of_device_is_available(child))
  874. continue;
  875. if (!of_device_is_compatible(child, compat))
  876. continue;
  877. if (validate_parent_available(child))
  878. continue;
  879. irq = a10_get_irq_mask(child);
  880. if (irq < 0)
  881. continue;
  882. /* Get matching node and check for valid result */
  883. pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
  884. if (IS_ERR_OR_NULL(pdev_id))
  885. continue;
  886. /* Validate private data pointer before dereferencing */
  887. prv = pdev_id->data;
  888. if (!prv)
  889. continue;
  890. altr_init_a10_ecc_block(child, BIT(irq),
  891. prv->ecc_enable_mask, 0);
  892. }
  893. of_node_put(np);
  894. return 0;
  895. }
  896. /*********************** SDRAM EDAC Device Functions *********************/
  897. #ifdef CONFIG_EDAC_ALTERA_SDRAM
  898. static const struct edac_device_prv_data s10_sdramecc_data = {
  899. .setup = altr_check_ecc_deps,
  900. .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
  901. .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
  902. .ecc_enable_mask = ALTR_S10_ECC_EN,
  903. .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
  904. .ce_set_mask = ALTR_S10_ECC_TSERRA,
  905. .ue_set_mask = ALTR_S10_ECC_TDERRA,
  906. .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
  907. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  908. .inject_fops = &altr_edac_a10_device_inject_fops,
  909. };
  910. #endif /* CONFIG_EDAC_ALTERA_SDRAM */
  911. /*********************** OCRAM EDAC Device Functions *********************/
  912. #ifdef CONFIG_EDAC_ALTERA_OCRAM
  913. static void *ocram_alloc_mem(size_t size, void **other)
  914. {
  915. struct device_node *np;
  916. struct gen_pool *gp;
  917. void *sram_addr;
  918. np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
  919. if (!np)
  920. return NULL;
  921. gp = of_gen_pool_get(np, "iram", 0);
  922. of_node_put(np);
  923. if (!gp)
  924. return NULL;
  925. sram_addr = (void *)gen_pool_alloc(gp, size);
  926. if (!sram_addr)
  927. return NULL;
  928. memset(sram_addr, 0, size);
  929. /* Ensure data is written out */
  930. wmb();
  931. /* Remember this handle for freeing later */
  932. *other = gp;
  933. return sram_addr;
  934. }
  935. static void ocram_free_mem(void *p, size_t size, void *other)
  936. {
  937. gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
  938. }
  939. static const struct edac_device_prv_data ocramecc_data = {
  940. .setup = altr_check_ecc_deps,
  941. .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
  942. .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
  943. .alloc_mem = ocram_alloc_mem,
  944. .free_mem = ocram_free_mem,
  945. .ecc_enable_mask = ALTR_OCR_ECC_EN,
  946. .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
  947. .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
  948. .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
  949. .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
  950. .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
  951. .inject_fops = &altr_edac_device_inject_fops,
  952. };
  953. static int __maybe_unused
  954. altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
  955. {
  956. void __iomem *base = device->base;
  957. int ret;
  958. ret = altr_check_ecc_deps(device);
  959. if (ret)
  960. return ret;
  961. /* Verify OCRAM has been initialized */
  962. if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
  963. (base + ALTR_A10_ECC_INITSTAT_OFST)))
  964. return -ENODEV;
  965. /* Enable IRQ on Single Bit Error */
  966. writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
  967. /* Ensure all writes complete */
  968. wmb();
  969. return 0;
  970. }
  971. static const struct edac_device_prv_data a10_ocramecc_data = {
  972. .setup = altr_check_ocram_deps_init,
  973. .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
  974. .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
  975. .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
  976. .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
  977. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  978. .ce_set_mask = ALTR_A10_ECC_TSERRA,
  979. .ue_set_mask = ALTR_A10_ECC_TDERRA,
  980. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  981. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  982. .inject_fops = &altr_edac_a10_device_inject2_fops,
  983. /*
  984. * OCRAM panic on uncorrectable error because sleep/resume
  985. * functions and FPGA contents are stored in OCRAM. Prefer
  986. * a kernel panic over executing/loading corrupted data.
  987. */
  988. .panic = true,
  989. };
  990. #endif /* CONFIG_EDAC_ALTERA_OCRAM */
  991. /********************* L2 Cache EDAC Device Functions ********************/
  992. #ifdef CONFIG_EDAC_ALTERA_L2C
  993. static void *l2_alloc_mem(size_t size, void **other)
  994. {
  995. struct device *dev = *other;
  996. void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
  997. if (!ptemp)
  998. return NULL;
  999. /* Make sure everything is written out */
  1000. wmb();
  1001. /*
  1002. * Clean all cache levels up to LoC (includes L2)
  1003. * This ensures the corrupted data is written into
  1004. * L2 cache for readback test (which causes ECC error).
  1005. */
  1006. flush_cache_all();
  1007. return ptemp;
  1008. }
  1009. static void l2_free_mem(void *p, size_t size, void *other)
  1010. {
  1011. struct device *dev = other;
  1012. if (dev && p)
  1013. devm_kfree(dev, p);
  1014. }
  1015. /*
  1016. * altr_l2_check_deps()
  1017. * Test for L2 cache ECC dependencies upon entry because
  1018. * platform specific startup should have initialized the L2
  1019. * memory and enabled the ECC.
  1020. * Bail if ECC is not enabled.
  1021. * Note that L2 Cache Enable is forced at build time.
  1022. */
  1023. static int altr_l2_check_deps(struct altr_edac_device_dev *device)
  1024. {
  1025. void __iomem *base = device->base;
  1026. const struct edac_device_prv_data *prv = device->data;
  1027. if ((readl(base) & prv->ecc_enable_mask) ==
  1028. prv->ecc_enable_mask)
  1029. return 0;
  1030. edac_printk(KERN_ERR, EDAC_DEVICE,
  1031. "L2: No ECC present, or ECC disabled\n");
  1032. return -ENODEV;
  1033. }
  1034. static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
  1035. {
  1036. struct altr_edac_device_dev *dci = dev_id;
  1037. if (irq == dci->sb_irq) {
  1038. regmap_write(dci->edac->ecc_mgr_map,
  1039. A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
  1040. A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
  1041. edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
  1042. return IRQ_HANDLED;
  1043. } else if (irq == dci->db_irq) {
  1044. regmap_write(dci->edac->ecc_mgr_map,
  1045. A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
  1046. A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
  1047. edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
  1048. panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
  1049. return IRQ_HANDLED;
  1050. }
  1051. WARN_ON(1);
  1052. return IRQ_NONE;
  1053. }
  1054. static const struct edac_device_prv_data l2ecc_data = {
  1055. .setup = altr_l2_check_deps,
  1056. .ce_clear_mask = 0,
  1057. .ue_clear_mask = 0,
  1058. .alloc_mem = l2_alloc_mem,
  1059. .free_mem = l2_free_mem,
  1060. .ecc_enable_mask = ALTR_L2_ECC_EN,
  1061. .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
  1062. .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
  1063. .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
  1064. .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
  1065. .inject_fops = &altr_edac_device_inject_fops,
  1066. };
  1067. static const struct edac_device_prv_data a10_l2ecc_data = {
  1068. .setup = altr_l2_check_deps,
  1069. .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
  1070. .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
  1071. .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
  1072. .alloc_mem = l2_alloc_mem,
  1073. .free_mem = l2_free_mem,
  1074. .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
  1075. .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
  1076. .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
  1077. .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
  1078. .ecc_irq_handler = altr_edac_a10_l2_irq,
  1079. .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
  1080. .inject_fops = &altr_edac_device_inject_fops,
  1081. };
  1082. #endif /* CONFIG_EDAC_ALTERA_L2C */
  1083. /********************* Ethernet Device Functions ********************/
  1084. #ifdef CONFIG_EDAC_ALTERA_ETHERNET
  1085. static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
  1086. {
  1087. int ret;
  1088. ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
  1089. if (ret)
  1090. return ret;
  1091. return altr_check_ecc_deps(dev);
  1092. }
  1093. static const struct edac_device_prv_data a10_enetecc_data = {
  1094. .setup = socfpga_init_ethernet_ecc,
  1095. .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
  1096. .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
  1097. .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
  1098. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  1099. .ce_set_mask = ALTR_A10_ECC_TSERRA,
  1100. .ue_set_mask = ALTR_A10_ECC_TDERRA,
  1101. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  1102. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  1103. .inject_fops = &altr_edac_a10_device_inject2_fops,
  1104. };
  1105. #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
  1106. /********************** NAND Device Functions **********************/
  1107. #ifdef CONFIG_EDAC_ALTERA_NAND
  1108. static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
  1109. {
  1110. int ret;
  1111. ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
  1112. if (ret)
  1113. return ret;
  1114. return altr_check_ecc_deps(device);
  1115. }
  1116. static const struct edac_device_prv_data a10_nandecc_data = {
  1117. .setup = socfpga_init_nand_ecc,
  1118. .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
  1119. .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
  1120. .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
  1121. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  1122. .ce_set_mask = ALTR_A10_ECC_TSERRA,
  1123. .ue_set_mask = ALTR_A10_ECC_TDERRA,
  1124. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  1125. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  1126. .inject_fops = &altr_edac_a10_device_inject_fops,
  1127. };
  1128. #endif /* CONFIG_EDAC_ALTERA_NAND */
  1129. /********************** DMA Device Functions **********************/
  1130. #ifdef CONFIG_EDAC_ALTERA_DMA
  1131. static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
  1132. {
  1133. int ret;
  1134. ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
  1135. if (ret)
  1136. return ret;
  1137. return altr_check_ecc_deps(device);
  1138. }
  1139. static const struct edac_device_prv_data a10_dmaecc_data = {
  1140. .setup = socfpga_init_dma_ecc,
  1141. .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
  1142. .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
  1143. .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
  1144. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  1145. .ce_set_mask = ALTR_A10_ECC_TSERRA,
  1146. .ue_set_mask = ALTR_A10_ECC_TDERRA,
  1147. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  1148. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  1149. .inject_fops = &altr_edac_a10_device_inject_fops,
  1150. };
  1151. #endif /* CONFIG_EDAC_ALTERA_DMA */
  1152. /********************** USB Device Functions **********************/
  1153. #ifdef CONFIG_EDAC_ALTERA_USB
  1154. static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
  1155. {
  1156. int ret;
  1157. ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
  1158. if (ret)
  1159. return ret;
  1160. return altr_check_ecc_deps(device);
  1161. }
  1162. static const struct edac_device_prv_data a10_usbecc_data = {
  1163. .setup = socfpga_init_usb_ecc,
  1164. .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
  1165. .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
  1166. .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
  1167. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  1168. .ce_set_mask = ALTR_A10_ECC_TSERRA,
  1169. .ue_set_mask = ALTR_A10_ECC_TDERRA,
  1170. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  1171. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  1172. .inject_fops = &altr_edac_a10_device_inject2_fops,
  1173. };
  1174. #endif /* CONFIG_EDAC_ALTERA_USB */
  1175. /********************** QSPI Device Functions **********************/
  1176. #ifdef CONFIG_EDAC_ALTERA_QSPI
  1177. static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
  1178. {
  1179. int ret;
  1180. ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
  1181. if (ret)
  1182. return ret;
  1183. return altr_check_ecc_deps(device);
  1184. }
  1185. static const struct edac_device_prv_data a10_qspiecc_data = {
  1186. .setup = socfpga_init_qspi_ecc,
  1187. .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
  1188. .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
  1189. .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
  1190. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  1191. .ce_set_mask = ALTR_A10_ECC_TSERRA,
  1192. .ue_set_mask = ALTR_A10_ECC_TDERRA,
  1193. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  1194. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  1195. .inject_fops = &altr_edac_a10_device_inject_fops,
  1196. };
  1197. #endif /* CONFIG_EDAC_ALTERA_QSPI */
  1198. /********************* SDMMC Device Functions **********************/
  1199. #ifdef CONFIG_EDAC_ALTERA_SDMMC
  1200. static const struct edac_device_prv_data a10_sdmmceccb_data;
  1201. static int altr_portb_setup(struct altr_edac_device_dev *device)
  1202. {
  1203. struct edac_device_ctl_info *dci;
  1204. struct altr_edac_device_dev *altdev;
  1205. char *ecc_name = "sdmmcb-ecc";
  1206. int edac_idx, rc;
  1207. struct device_node *np;
  1208. const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
  1209. rc = altr_check_ecc_deps(device);
  1210. if (rc)
  1211. return rc;
  1212. np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
  1213. if (!np) {
  1214. edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
  1215. return -ENODEV;
  1216. }
  1217. /* Create the PortB EDAC device */
  1218. edac_idx = edac_device_alloc_index();
  1219. dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
  1220. ecc_name, 1, 0, NULL, 0, edac_idx);
  1221. if (!dci) {
  1222. edac_printk(KERN_ERR, EDAC_DEVICE,
  1223. "%s: Unable to allocate PortB EDAC device\n",
  1224. ecc_name);
  1225. return -ENOMEM;
  1226. }
  1227. /* Initialize the PortB EDAC device structure from PortA structure */
  1228. altdev = dci->pvt_info;
  1229. *altdev = *device;
  1230. if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
  1231. return -ENOMEM;
  1232. /* Update PortB specific values */
  1233. altdev->edac_dev_name = ecc_name;
  1234. altdev->edac_idx = edac_idx;
  1235. altdev->edac_dev = dci;
  1236. altdev->data = prv;
  1237. dci->dev = &altdev->ddev;
  1238. dci->ctl_name = "Altera ECC Manager";
  1239. dci->mod_name = ecc_name;
  1240. dci->dev_name = ecc_name;
  1241. /* Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly */
  1242. #ifdef CONFIG_ARCH_STRATIX10
  1243. altdev->sb_irq = irq_of_parse_and_map(np, 1);
  1244. #else
  1245. altdev->sb_irq = irq_of_parse_and_map(np, 2);
  1246. #endif
  1247. if (!altdev->sb_irq) {
  1248. edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
  1249. rc = -ENODEV;
  1250. goto err_release_group_1;
  1251. }
  1252. rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
  1253. prv->ecc_irq_handler,
  1254. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  1255. ecc_name, altdev);
  1256. if (rc) {
  1257. edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
  1258. goto err_release_group_1;
  1259. }
  1260. #ifdef CONFIG_ARCH_STRATIX10
  1261. /* Use IRQ to determine SError origin instead of assigning IRQ */
  1262. rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
  1263. if (rc) {
  1264. edac_printk(KERN_ERR, EDAC_DEVICE,
  1265. "Error PortB DBIRQ alloc\n");
  1266. goto err_release_group_1;
  1267. }
  1268. #else
  1269. altdev->db_irq = irq_of_parse_and_map(np, 3);
  1270. if (!altdev->db_irq) {
  1271. edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
  1272. rc = -ENODEV;
  1273. goto err_release_group_1;
  1274. }
  1275. rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
  1276. prv->ecc_irq_handler,
  1277. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  1278. ecc_name, altdev);
  1279. if (rc) {
  1280. edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
  1281. goto err_release_group_1;
  1282. }
  1283. #endif
  1284. rc = edac_device_add_device(dci);
  1285. if (rc) {
  1286. edac_printk(KERN_ERR, EDAC_DEVICE,
  1287. "edac_device_add_device portB failed\n");
  1288. rc = -ENOMEM;
  1289. goto err_release_group_1;
  1290. }
  1291. altr_create_edacdev_dbgfs(dci, prv);
  1292. list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
  1293. devres_remove_group(&altdev->ddev, altr_portb_setup);
  1294. return 0;
  1295. err_release_group_1:
  1296. edac_device_free_ctl_info(dci);
  1297. devres_release_group(&altdev->ddev, altr_portb_setup);
  1298. edac_printk(KERN_ERR, EDAC_DEVICE,
  1299. "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
  1300. return rc;
  1301. }
  1302. static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
  1303. {
  1304. int rc = -ENODEV;
  1305. struct device_node *child;
  1306. child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
  1307. if (!child)
  1308. return -ENODEV;
  1309. if (!of_device_is_available(child))
  1310. goto exit;
  1311. if (validate_parent_available(child))
  1312. goto exit;
  1313. /* Init portB */
  1314. rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
  1315. a10_sdmmceccb_data.ecc_enable_mask, 1);
  1316. if (rc)
  1317. goto exit;
  1318. /* Setup portB */
  1319. return altr_portb_setup(device);
  1320. exit:
  1321. of_node_put(child);
  1322. return rc;
  1323. }
  1324. static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
  1325. {
  1326. struct altr_edac_device_dev *ad = dev_id;
  1327. void __iomem *base = ad->base;
  1328. const struct edac_device_prv_data *priv = ad->data;
  1329. if (irq == ad->sb_irq) {
  1330. writel(priv->ce_clear_mask,
  1331. base + ALTR_A10_ECC_INTSTAT_OFST);
  1332. edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
  1333. return IRQ_HANDLED;
  1334. } else if (irq == ad->db_irq) {
  1335. writel(priv->ue_clear_mask,
  1336. base + ALTR_A10_ECC_INTSTAT_OFST);
  1337. edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
  1338. return IRQ_HANDLED;
  1339. }
  1340. WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
  1341. return IRQ_NONE;
  1342. }
  1343. static const struct edac_device_prv_data a10_sdmmcecca_data = {
  1344. .setup = socfpga_init_sdmmc_ecc,
  1345. .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
  1346. .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
  1347. .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
  1348. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  1349. .ce_set_mask = ALTR_A10_ECC_SERRPENA,
  1350. .ue_set_mask = ALTR_A10_ECC_DERRPENA,
  1351. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  1352. .ecc_irq_handler = altr_edac_a10_ecc_irq,
  1353. .inject_fops = &altr_edac_a10_device_inject_fops,
  1354. };
  1355. static const struct edac_device_prv_data a10_sdmmceccb_data = {
  1356. .setup = socfpga_init_sdmmc_ecc,
  1357. .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
  1358. .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
  1359. .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
  1360. .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
  1361. .ce_set_mask = ALTR_A10_ECC_TSERRB,
  1362. .ue_set_mask = ALTR_A10_ECC_TDERRB,
  1363. .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
  1364. .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
  1365. .inject_fops = &altr_edac_a10_device_inject_fops,
  1366. };
  1367. #endif /* CONFIG_EDAC_ALTERA_SDMMC */
  1368. /********************* Arria10 EDAC Device Functions *************************/
  1369. static const struct of_device_id altr_edac_a10_device_of_match[] = {
  1370. #ifdef CONFIG_EDAC_ALTERA_L2C
  1371. { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
  1372. #endif
  1373. #ifdef CONFIG_EDAC_ALTERA_OCRAM
  1374. { .compatible = "altr,socfpga-a10-ocram-ecc",
  1375. .data = &a10_ocramecc_data },
  1376. #endif
  1377. #ifdef CONFIG_EDAC_ALTERA_ETHERNET
  1378. { .compatible = "altr,socfpga-eth-mac-ecc",
  1379. .data = &a10_enetecc_data },
  1380. #endif
  1381. #ifdef CONFIG_EDAC_ALTERA_NAND
  1382. { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
  1383. #endif
  1384. #ifdef CONFIG_EDAC_ALTERA_DMA
  1385. { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
  1386. #endif
  1387. #ifdef CONFIG_EDAC_ALTERA_USB
  1388. { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
  1389. #endif
  1390. #ifdef CONFIG_EDAC_ALTERA_QSPI
  1391. { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
  1392. #endif
  1393. #ifdef CONFIG_EDAC_ALTERA_SDMMC
  1394. { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
  1395. #endif
  1396. #ifdef CONFIG_EDAC_ALTERA_SDRAM
  1397. { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
  1398. #endif
  1399. {},
  1400. };
  1401. MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
  1402. /*
  1403. * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
  1404. * because 2 IRQs are shared among the all ECC peripherals. The ECC
  1405. * manager manages the IRQs and the children.
  1406. * Based on xgene_edac.c peripheral code.
  1407. */
  1408. static ssize_t altr_edac_a10_device_trig(struct file *file,
  1409. const char __user *user_buf,
  1410. size_t count, loff_t *ppos)
  1411. {
  1412. struct edac_device_ctl_info *edac_dci = file->private_data;
  1413. struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
  1414. const struct edac_device_prv_data *priv = drvdata->data;
  1415. void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
  1416. unsigned long flags;
  1417. u8 trig_type;
  1418. if (!user_buf || get_user(trig_type, user_buf))
  1419. return -EFAULT;
  1420. local_irq_save(flags);
  1421. if (trig_type == ALTR_UE_TRIGGER_CHAR)
  1422. writel(priv->ue_set_mask, set_addr);
  1423. else
  1424. writel(priv->ce_set_mask, set_addr);
  1425. /* Ensure the interrupt test bits are set */
  1426. wmb();
  1427. local_irq_restore(flags);
  1428. return count;
  1429. }
  1430. /*
  1431. * The Stratix10 EDAC Error Injection Functions differ from Arria10
  1432. * slightly. A few Arria10 peripherals can use this injection function.
  1433. * Inject the error into the memory and then readback to trigger the IRQ.
  1434. */
  1435. static ssize_t altr_edac_a10_device_trig2(struct file *file,
  1436. const char __user *user_buf,
  1437. size_t count, loff_t *ppos)
  1438. {
  1439. struct edac_device_ctl_info *edac_dci = file->private_data;
  1440. struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
  1441. const struct edac_device_prv_data *priv = drvdata->data;
  1442. void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
  1443. unsigned long flags;
  1444. u8 trig_type;
  1445. if (!user_buf || get_user(trig_type, user_buf))
  1446. return -EFAULT;
  1447. local_irq_save(flags);
  1448. if (trig_type == ALTR_UE_TRIGGER_CHAR) {
  1449. writel(priv->ue_set_mask, set_addr);
  1450. } else {
  1451. /* Setup read/write of 4 bytes */
  1452. writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
  1453. /* Setup Address to 0 */
  1454. writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
  1455. /* Setup accctrl to read & ecc & data override */
  1456. writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
  1457. /* Kick it. */
  1458. writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
  1459. /* Setup write for single bit change */
  1460. writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
  1461. drvdata->base + ECC_BLK_WDATA0_OFST);
  1462. writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
  1463. drvdata->base + ECC_BLK_WDATA1_OFST);
  1464. writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
  1465. drvdata->base + ECC_BLK_WDATA2_OFST);
  1466. writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
  1467. drvdata->base + ECC_BLK_WDATA3_OFST);
  1468. /* Copy Read ECC to Write ECC */
  1469. writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
  1470. drvdata->base + ECC_BLK_WECC0_OFST);
  1471. writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
  1472. drvdata->base + ECC_BLK_WECC1_OFST);
  1473. /* Setup accctrl to write & ecc override & data override */
  1474. writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
  1475. /* Kick it. */
  1476. writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
  1477. /* Setup accctrl to read & ecc overwrite & data overwrite */
  1478. writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
  1479. /* Kick it. */
  1480. writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
  1481. }
  1482. /* Ensure the interrupt test bits are set */
  1483. wmb();
  1484. local_irq_restore(flags);
  1485. return count;
  1486. }
  1487. static void altr_edac_a10_irq_handler(struct irq_desc *desc)
  1488. {
  1489. int dberr, bit, sm_offset, irq_status;
  1490. struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
  1491. struct irq_chip *chip = irq_desc_get_chip(desc);
  1492. int irq = irq_desc_get_irq(desc);
  1493. unsigned long bits;
  1494. dberr = (irq == edac->db_irq) ? 1 : 0;
  1495. sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
  1496. A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
  1497. chained_irq_enter(chip, desc);
  1498. regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
  1499. bits = irq_status;
  1500. for_each_set_bit(bit, &bits, 32) {
  1501. irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
  1502. if (irq)
  1503. generic_handle_irq(irq);
  1504. }
  1505. chained_irq_exit(chip, desc);
  1506. }
  1507. static int validate_parent_available(struct device_node *np)
  1508. {
  1509. struct device_node *parent;
  1510. int ret = 0;
  1511. /* SDRAM must be present for Linux (implied parent) */
  1512. if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
  1513. return 0;
  1514. /* Ensure parent device is enabled if parent node exists */
  1515. parent = of_parse_phandle(np, "altr,ecc-parent", 0);
  1516. if (parent && !of_device_is_available(parent))
  1517. ret = -ENODEV;
  1518. of_node_put(parent);
  1519. return ret;
  1520. }
  1521. static int get_s10_sdram_edac_resource(struct device_node *np,
  1522. struct resource *res)
  1523. {
  1524. struct device_node *parent;
  1525. int ret;
  1526. parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
  1527. if (!parent)
  1528. return -ENODEV;
  1529. ret = of_address_to_resource(parent, 0, res);
  1530. of_node_put(parent);
  1531. return ret;
  1532. }
  1533. static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
  1534. struct device_node *np)
  1535. {
  1536. struct edac_device_ctl_info *dci;
  1537. struct altr_edac_device_dev *altdev;
  1538. char *ecc_name = (char *)np->name;
  1539. struct resource res;
  1540. int edac_idx;
  1541. int rc = 0;
  1542. const struct edac_device_prv_data *prv;
  1543. /* Get matching node and check for valid result */
  1544. const struct of_device_id *pdev_id =
  1545. of_match_node(altr_edac_a10_device_of_match, np);
  1546. if (IS_ERR_OR_NULL(pdev_id))
  1547. return -ENODEV;
  1548. /* Get driver specific data for this EDAC device */
  1549. prv = pdev_id->data;
  1550. if (IS_ERR_OR_NULL(prv))
  1551. return -ENODEV;
  1552. if (validate_parent_available(np))
  1553. return -ENODEV;
  1554. if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
  1555. return -ENOMEM;
  1556. if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
  1557. rc = get_s10_sdram_edac_resource(np, &res);
  1558. else
  1559. rc = of_address_to_resource(np, 0, &res);
  1560. if (rc < 0) {
  1561. edac_printk(KERN_ERR, EDAC_DEVICE,
  1562. "%s: no resource address\n", ecc_name);
  1563. goto err_release_group;
  1564. }
  1565. edac_idx = edac_device_alloc_index();
  1566. dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
  1567. 1, ecc_name, 1, 0, NULL, 0,
  1568. edac_idx);
  1569. if (!dci) {
  1570. edac_printk(KERN_ERR, EDAC_DEVICE,
  1571. "%s: Unable to allocate EDAC device\n", ecc_name);
  1572. rc = -ENOMEM;
  1573. goto err_release_group;
  1574. }
  1575. altdev = dci->pvt_info;
  1576. dci->dev = edac->dev;
  1577. altdev->edac_dev_name = ecc_name;
  1578. altdev->edac_idx = edac_idx;
  1579. altdev->edac = edac;
  1580. altdev->edac_dev = dci;
  1581. altdev->data = prv;
  1582. altdev->ddev = *edac->dev;
  1583. dci->dev = &altdev->ddev;
  1584. dci->ctl_name = "Altera ECC Manager";
  1585. dci->mod_name = ecc_name;
  1586. dci->dev_name = ecc_name;
  1587. altdev->base = devm_ioremap_resource(edac->dev, &res);
  1588. if (IS_ERR(altdev->base)) {
  1589. rc = PTR_ERR(altdev->base);
  1590. goto err_release_group1;
  1591. }
  1592. /* Check specific dependencies for the module */
  1593. if (altdev->data->setup) {
  1594. rc = altdev->data->setup(altdev);
  1595. if (rc)
  1596. goto err_release_group1;
  1597. }
  1598. altdev->sb_irq = irq_of_parse_and_map(np, 0);
  1599. if (!altdev->sb_irq) {
  1600. edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
  1601. rc = -ENODEV;
  1602. goto err_release_group1;
  1603. }
  1604. rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
  1605. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  1606. ecc_name, altdev);
  1607. if (rc) {
  1608. edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
  1609. goto err_release_group1;
  1610. }
  1611. #ifdef CONFIG_ARCH_STRATIX10
  1612. /* Use IRQ to determine SError origin instead of assigning IRQ */
  1613. rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
  1614. if (rc) {
  1615. edac_printk(KERN_ERR, EDAC_DEVICE,
  1616. "Unable to parse DB IRQ index\n");
  1617. goto err_release_group1;
  1618. }
  1619. #else
  1620. altdev->db_irq = irq_of_parse_and_map(np, 1);
  1621. if (!altdev->db_irq) {
  1622. edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
  1623. rc = -ENODEV;
  1624. goto err_release_group1;
  1625. }
  1626. rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
  1627. IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
  1628. ecc_name, altdev);
  1629. if (rc) {
  1630. edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
  1631. goto err_release_group1;
  1632. }
  1633. #endif
  1634. rc = edac_device_add_device(dci);
  1635. if (rc) {
  1636. dev_err(edac->dev, "edac_device_add_device failed\n");
  1637. rc = -ENOMEM;
  1638. goto err_release_group1;
  1639. }
  1640. altr_create_edacdev_dbgfs(dci, prv);
  1641. list_add(&altdev->next, &edac->a10_ecc_devices);
  1642. devres_remove_group(edac->dev, altr_edac_a10_device_add);
  1643. return 0;
  1644. err_release_group1:
  1645. edac_device_free_ctl_info(dci);
  1646. err_release_group:
  1647. devres_release_group(edac->dev, NULL);
  1648. edac_printk(KERN_ERR, EDAC_DEVICE,
  1649. "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
  1650. return rc;
  1651. }
  1652. static void a10_eccmgr_irq_mask(struct irq_data *d)
  1653. {
  1654. struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
  1655. regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
  1656. BIT(d->hwirq));
  1657. }
  1658. static void a10_eccmgr_irq_unmask(struct irq_data *d)
  1659. {
  1660. struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
  1661. regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
  1662. BIT(d->hwirq));
  1663. }
  1664. static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
  1665. irq_hw_number_t hwirq)
  1666. {
  1667. struct altr_arria10_edac *edac = d->host_data;
  1668. irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
  1669. irq_set_chip_data(irq, edac);
  1670. irq_set_noprobe(irq);
  1671. return 0;
  1672. }
  1673. static const struct irq_domain_ops a10_eccmgr_ic_ops = {
  1674. .map = a10_eccmgr_irqdomain_map,
  1675. .xlate = irq_domain_xlate_twocell,
  1676. };
  1677. /************** Stratix 10 EDAC Double Bit Error Handler ************/
  1678. #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
  1679. #ifdef CONFIG_ARCH_STRATIX10
  1680. /* panic routine issues reboot on non-zero panic_timeout */
  1681. extern int panic_timeout;
  1682. /*
  1683. * The double bit error is handled through SError which is fatal. This is
  1684. * called as a panic notifier to printout ECC error info as part of the panic.
  1685. */
  1686. static int s10_edac_dberr_handler(struct notifier_block *this,
  1687. unsigned long event, void *ptr)
  1688. {
  1689. struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
  1690. int err_addr, dberror;
  1691. regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
  1692. &dberror);
  1693. regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
  1694. if (dberror & S10_DBE_IRQ_MASK) {
  1695. struct list_head *position;
  1696. struct altr_edac_device_dev *ed;
  1697. struct arm_smccc_res result;
  1698. /* Find the matching DBE in the list of devices */
  1699. list_for_each(position, &edac->a10_ecc_devices) {
  1700. ed = list_entry(position, struct altr_edac_device_dev,
  1701. next);
  1702. if (!(BIT(ed->db_irq) & dberror))
  1703. continue;
  1704. writel(ALTR_A10_ECC_DERRPENA,
  1705. ed->base + ALTR_A10_ECC_INTSTAT_OFST);
  1706. err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
  1707. regmap_write(edac->ecc_mgr_map,
  1708. S10_SYSMGR_UE_ADDR_OFST, err_addr);
  1709. edac_printk(KERN_ERR, EDAC_DEVICE,
  1710. "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
  1711. ed->edac_dev_name, err_addr);
  1712. break;
  1713. }
  1714. /* Notify the System through SMC. Reboot delay = 1 second */
  1715. panic_timeout = 1;
  1716. arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
  1717. 0, 0, &result);
  1718. }
  1719. return NOTIFY_DONE;
  1720. }
  1721. #endif
  1722. /****************** Arria 10 EDAC Probe Function *********************/
  1723. static int altr_edac_a10_probe(struct platform_device *pdev)
  1724. {
  1725. struct altr_arria10_edac *edac;
  1726. struct device_node *child;
  1727. edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
  1728. if (!edac)
  1729. return -ENOMEM;
  1730. edac->dev = &pdev->dev;
  1731. platform_set_drvdata(pdev, edac);
  1732. INIT_LIST_HEAD(&edac->a10_ecc_devices);
  1733. edac->ecc_mgr_map =
  1734. altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
  1735. "altr,sysmgr-syscon");
  1736. if (IS_ERR(edac->ecc_mgr_map)) {
  1737. edac_printk(KERN_ERR, EDAC_DEVICE,
  1738. "Unable to get syscon altr,sysmgr-syscon\n");
  1739. return PTR_ERR(edac->ecc_mgr_map);
  1740. }
  1741. edac->irq_chip.name = pdev->dev.of_node->name;
  1742. edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
  1743. edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
  1744. edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
  1745. &a10_eccmgr_ic_ops, edac);
  1746. if (!edac->domain) {
  1747. dev_err(&pdev->dev, "Error adding IRQ domain\n");
  1748. return -ENOMEM;
  1749. }
  1750. edac->sb_irq = platform_get_irq(pdev, 0);
  1751. if (edac->sb_irq < 0) {
  1752. dev_err(&pdev->dev, "No SBERR IRQ resource\n");
  1753. return edac->sb_irq;
  1754. }
  1755. irq_set_chained_handler_and_data(edac->sb_irq,
  1756. altr_edac_a10_irq_handler,
  1757. edac);
  1758. #ifdef CONFIG_ARCH_STRATIX10
  1759. {
  1760. int dberror, err_addr;
  1761. edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
  1762. atomic_notifier_chain_register(&panic_notifier_list,
  1763. &edac->panic_notifier);
  1764. /* Printout a message if uncorrectable error previously. */
  1765. regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
  1766. &dberror);
  1767. if (dberror) {
  1768. regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
  1769. &err_addr);
  1770. edac_printk(KERN_ERR, EDAC_DEVICE,
  1771. "Previous Boot UE detected[0x%X] @ 0x%X\n",
  1772. dberror, err_addr);
  1773. /* Reset the sticky registers */
  1774. regmap_write(edac->ecc_mgr_map,
  1775. S10_SYSMGR_UE_VAL_OFST, 0);
  1776. regmap_write(edac->ecc_mgr_map,
  1777. S10_SYSMGR_UE_ADDR_OFST, 0);
  1778. }
  1779. }
  1780. #else
  1781. edac->db_irq = platform_get_irq(pdev, 1);
  1782. if (edac->db_irq < 0) {
  1783. dev_err(&pdev->dev, "No DBERR IRQ resource\n");
  1784. return edac->db_irq;
  1785. }
  1786. irq_set_chained_handler_and_data(edac->db_irq,
  1787. altr_edac_a10_irq_handler, edac);
  1788. #endif
  1789. for_each_child_of_node(pdev->dev.of_node, child) {
  1790. if (!of_device_is_available(child))
  1791. continue;
  1792. if (of_match_node(altr_edac_a10_device_of_match, child))
  1793. altr_edac_a10_device_add(edac, child);
  1794. #ifdef CONFIG_EDAC_ALTERA_SDRAM
  1795. else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
  1796. of_platform_populate(pdev->dev.of_node,
  1797. altr_sdram_ctrl_of_match,
  1798. NULL, &pdev->dev);
  1799. #endif
  1800. }
  1801. return 0;
  1802. }
  1803. static const struct of_device_id altr_edac_a10_of_match[] = {
  1804. { .compatible = "altr,socfpga-a10-ecc-manager" },
  1805. { .compatible = "altr,socfpga-s10-ecc-manager" },
  1806. {},
  1807. };
  1808. MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
  1809. static struct platform_driver altr_edac_a10_driver = {
  1810. .probe = altr_edac_a10_probe,
  1811. .driver = {
  1812. .name = "socfpga_a10_ecc_manager",
  1813. .of_match_table = altr_edac_a10_of_match,
  1814. },
  1815. };
  1816. module_platform_driver(altr_edac_a10_driver);
  1817. MODULE_LICENSE("GPL v2");
  1818. MODULE_AUTHOR("Thor Thayer");
  1819. MODULE_DESCRIPTION("EDAC Driver for Altera Memories");