Kconfig 16 KB

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  1. #
  2. # EDAC Kconfig
  3. # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com
  4. # Licensed and distributed under the GPL
  5. config EDAC_ATOMIC_SCRUB
  6. bool
  7. config EDAC_SUPPORT
  8. bool
  9. menuconfig EDAC
  10. tristate "EDAC (Error Detection And Correction) reporting"
  11. depends on HAS_IOMEM && EDAC_SUPPORT && RAS
  12. help
  13. EDAC is a subsystem along with hardware-specific drivers designed to
  14. report hardware errors. These are low-level errors that are reported
  15. in the CPU or supporting chipset or other subsystems:
  16. memory errors, cache errors, PCI errors, thermal throttling, etc..
  17. If unsure, select 'Y'.
  18. The mailing list for the EDAC project is linux-edac@vger.kernel.org.
  19. if EDAC
  20. config EDAC_LEGACY_SYSFS
  21. bool "EDAC legacy sysfs"
  22. default y
  23. help
  24. Enable the compatibility sysfs nodes.
  25. Use 'Y' if your edac utilities aren't ported to work with the newer
  26. structures.
  27. config EDAC_DEBUG
  28. bool "Debugging"
  29. select DEBUG_FS
  30. help
  31. This turns on debugging information for the entire EDAC subsystem.
  32. You do so by inserting edac_module with "edac_debug_level=x." Valid
  33. levels are 0-4 (from low to high) and by default it is set to 2.
  34. Usually you should select 'N' here.
  35. config EDAC_DECODE_MCE
  36. tristate "Decode MCEs in human-readable form (only on AMD for now)"
  37. depends on CPU_SUP_AMD && X86_MCE_AMD
  38. default y
  39. help
  40. Enable this option if you want to decode Machine Check Exceptions
  41. occurring on your machine in human-readable form.
  42. You should definitely say Y here in case you want to decode MCEs
  43. which occur really early upon boot, before the module infrastructure
  44. has been initialized.
  45. config EDAC_GHES
  46. bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
  47. depends on ACPI_APEI_GHES && (EDAC=y)
  48. help
  49. Not all machines support hardware-driven error report. Some of those
  50. provide a BIOS-driven error report mechanism via ACPI, using the
  51. APEI/GHES driver. By enabling this option, the error reports provided
  52. by GHES are sent to userspace via the EDAC API.
  53. When this option is enabled, it will disable the hardware-driven
  54. mechanisms, if a GHES BIOS is detected, entering into the
  55. "Firmware First" mode.
  56. It should be noticed that keeping both GHES and a hardware-driven
  57. error mechanism won't work well, as BIOS will race with OS, while
  58. reading the error registers. So, if you want to not use "Firmware
  59. first" GHES error mechanism, you should disable GHES either at
  60. compilation time or by passing "ghes.disable=1" Kernel parameter
  61. at boot time.
  62. In doubt, say 'Y'.
  63. config EDAC_AMD64
  64. tristate "AMD64 (Opteron, Athlon64)"
  65. depends on AMD_NB && EDAC_DECODE_MCE
  66. help
  67. Support for error detection and correction of DRAM ECC errors on
  68. the AMD64 families (>= K8) of memory controllers.
  69. config EDAC_AMD64_ERROR_INJECTION
  70. bool "Sysfs HW Error injection facilities"
  71. depends on EDAC_AMD64
  72. help
  73. Recent Opterons (Family 10h and later) provide for Memory Error
  74. Injection into the ECC detection circuits. The amd64_edac module
  75. allows the operator/user to inject Uncorrectable and Correctable
  76. errors into DRAM.
  77. When enabled, in each of the respective memory controller directories
  78. (/sys/devices/system/edac/mc/mcX), there are 3 input files:
  79. - inject_section (0..3, 16-byte section of 64-byte cacheline),
  80. - inject_word (0..8, 16-bit word of 16-byte section),
  81. - inject_ecc_vector (hex ecc vector: select bits of inject word)
  82. In addition, there are two control files, inject_read and inject_write,
  83. which trigger the DRAM ECC Read and Write respectively.
  84. config EDAC_AL_MC
  85. tristate "Amazon's Annapurna Lab Memory Controller"
  86. depends on (ARCH_ALPINE || COMPILE_TEST)
  87. help
  88. Support for error detection and correction for Amazon's Annapurna
  89. Labs Alpine chips which allow 1 bit correction and 2 bits detection.
  90. config EDAC_AMD76X
  91. tristate "AMD 76x (760, 762, 768)"
  92. depends on PCI && X86_32
  93. help
  94. Support for error detection and correction on the AMD 76x
  95. series of chipsets used with the Athlon processor.
  96. config EDAC_E7XXX
  97. tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
  98. depends on PCI && X86_32
  99. help
  100. Support for error detection and correction on the Intel
  101. E7205, E7500, E7501 and E7505 server chipsets.
  102. config EDAC_E752X
  103. tristate "Intel e752x (e7520, e7525, e7320) and 3100"
  104. depends on PCI && X86
  105. help
  106. Support for error detection and correction on the Intel
  107. E7520, E7525, E7320 server chipsets.
  108. config EDAC_I82443BXGX
  109. tristate "Intel 82443BX/GX (440BX/GX)"
  110. depends on PCI && X86_32
  111. depends on BROKEN
  112. help
  113. Support for error detection and correction on the Intel
  114. 82443BX/GX memory controllers (440BX/GX chipsets).
  115. config EDAC_I82875P
  116. tristate "Intel 82875p (D82875P, E7210)"
  117. depends on PCI && X86_32
  118. help
  119. Support for error detection and correction on the Intel
  120. DP82785P and E7210 server chipsets.
  121. config EDAC_I82975X
  122. tristate "Intel 82975x (D82975x)"
  123. depends on PCI && X86
  124. help
  125. Support for error detection and correction on the Intel
  126. DP82975x server chipsets.
  127. config EDAC_I3000
  128. tristate "Intel 3000/3010"
  129. depends on PCI && X86
  130. help
  131. Support for error detection and correction on the Intel
  132. 3000 and 3010 server chipsets.
  133. config EDAC_I3200
  134. tristate "Intel 3200"
  135. depends on PCI && X86
  136. help
  137. Support for error detection and correction on the Intel
  138. 3200 and 3210 server chipsets.
  139. config EDAC_IE31200
  140. tristate "Intel e312xx"
  141. depends on PCI && X86
  142. help
  143. Support for error detection and correction on the Intel
  144. E3-1200 based DRAM controllers.
  145. config EDAC_X38
  146. tristate "Intel X38"
  147. depends on PCI && X86
  148. help
  149. Support for error detection and correction on the Intel
  150. X38 server chipsets.
  151. config EDAC_I5400
  152. tristate "Intel 5400 (Seaburg) chipsets"
  153. depends on PCI && X86
  154. help
  155. Support for error detection and correction the Intel
  156. i5400 MCH chipset (Seaburg).
  157. config EDAC_I7CORE
  158. tristate "Intel i7 Core (Nehalem) processors"
  159. depends on PCI && X86 && X86_MCE_INTEL
  160. help
  161. Support for error detection and correction the Intel
  162. i7 Core (Nehalem) Integrated Memory Controller that exists on
  163. newer processors like i7 Core, i7 Core Extreme, Xeon 35xx
  164. and Xeon 55xx processors.
  165. config EDAC_I82860
  166. tristate "Intel 82860"
  167. depends on PCI && X86_32
  168. help
  169. Support for error detection and correction on the Intel
  170. 82860 chipset.
  171. config EDAC_R82600
  172. tristate "Radisys 82600 embedded chipset"
  173. depends on PCI && X86_32
  174. help
  175. Support for error detection and correction on the Radisys
  176. 82600 embedded chipset.
  177. config EDAC_I5000
  178. tristate "Intel Greencreek/Blackford chipset"
  179. depends on X86 && PCI
  180. help
  181. Support for error detection and correction the Intel
  182. Greekcreek/Blackford chipsets.
  183. config EDAC_I5100
  184. tristate "Intel San Clemente MCH"
  185. depends on X86 && PCI
  186. help
  187. Support for error detection and correction the Intel
  188. San Clemente MCH.
  189. config EDAC_I7300
  190. tristate "Intel Clarksboro MCH"
  191. depends on X86 && PCI
  192. help
  193. Support for error detection and correction the Intel
  194. Clarksboro MCH (Intel 7300 chipset).
  195. config EDAC_SBRIDGE
  196. tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
  197. depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
  198. help
  199. Support for error detection and correction the Intel
  200. Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
  201. config EDAC_SKX
  202. tristate "Intel Skylake server Integrated MC"
  203. depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
  204. depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y
  205. select DMI
  206. select ACPI_ADXL
  207. help
  208. Support for error detection and correction the Intel
  209. Skylake server Integrated Memory Controllers. If your
  210. system has non-volatile DIMMs you should also manually
  211. select CONFIG_ACPI_NFIT.
  212. config EDAC_I10NM
  213. tristate "Intel 10nm server Integrated MC"
  214. depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI
  215. depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y
  216. select DMI
  217. select ACPI_ADXL
  218. help
  219. Support for error detection and correction the Intel
  220. 10nm server Integrated Memory Controllers. If your
  221. system has non-volatile DIMMs you should also manually
  222. select CONFIG_ACPI_NFIT.
  223. config EDAC_PND2
  224. tristate "Intel Pondicherry2"
  225. depends on PCI && X86_64 && X86_MCE_INTEL
  226. help
  227. Support for error detection and correction on the Intel
  228. Pondicherry2 Integrated Memory Controller. This SoC IP is
  229. first used on the Apollo Lake platform and Denverton
  230. micro-server but may appear on others in the future.
  231. config EDAC_MPC85XX
  232. bool "Freescale MPC83xx / MPC85xx"
  233. depends on FSL_SOC && EDAC=y
  234. help
  235. Support for error detection and correction on the Freescale
  236. MPC8349, MPC8560, MPC8540, MPC8548, T4240
  237. config EDAC_LAYERSCAPE
  238. tristate "Freescale Layerscape DDR"
  239. depends on ARCH_LAYERSCAPE || SOC_LS1021A
  240. help
  241. Support for error detection and correction on Freescale memory
  242. controllers on Layerscape SoCs.
  243. config EDAC_MV64X60
  244. tristate "Marvell MV64x60"
  245. depends on MV64X60
  246. help
  247. Support for error detection and correction on the Marvell
  248. MV64360 and MV64460 chipsets.
  249. config EDAC_PASEMI
  250. tristate "PA Semi PWRficient"
  251. depends on PPC_PASEMI && PCI
  252. help
  253. Support for error detection and correction on PA Semi
  254. PWRficient.
  255. config EDAC_CELL
  256. tristate "Cell Broadband Engine memory controller"
  257. depends on PPC_CELL_COMMON
  258. help
  259. Support for error detection and correction on the
  260. Cell Broadband Engine internal memory controller
  261. on platform without a hypervisor
  262. config EDAC_PPC4XX
  263. tristate "PPC4xx IBM DDR2 Memory Controller"
  264. depends on 4xx
  265. help
  266. This enables support for EDAC on the ECC memory used
  267. with the IBM DDR2 memory controller found in various
  268. PowerPC 4xx embedded processors such as the 405EX[r],
  269. 440SP, 440SPe, 460EX, 460GT and 460SX.
  270. config EDAC_AMD8131
  271. tristate "AMD8131 HyperTransport PCI-X Tunnel"
  272. depends on PCI && PPC_MAPLE
  273. help
  274. Support for error detection and correction on the
  275. AMD8131 HyperTransport PCI-X Tunnel chip.
  276. Note, add more Kconfig dependency if it's adopted
  277. on some machine other than Maple.
  278. config EDAC_AMD8111
  279. tristate "AMD8111 HyperTransport I/O Hub"
  280. depends on PCI && PPC_MAPLE
  281. help
  282. Support for error detection and correction on the
  283. AMD8111 HyperTransport I/O Hub chip.
  284. Note, add more Kconfig dependency if it's adopted
  285. on some machine other than Maple.
  286. config EDAC_CPC925
  287. tristate "IBM CPC925 Memory Controller (PPC970FX)"
  288. depends on PPC64
  289. help
  290. Support for error detection and correction on the
  291. IBM CPC925 Bridge and Memory Controller, which is
  292. a companion chip to the PowerPC 970 family of
  293. processors.
  294. config EDAC_HIGHBANK_MC
  295. tristate "Highbank Memory Controller"
  296. depends on ARCH_HIGHBANK
  297. help
  298. Support for error detection and correction on the
  299. Calxeda Highbank memory controller.
  300. config EDAC_HIGHBANK_L2
  301. tristate "Highbank L2 Cache"
  302. depends on ARCH_HIGHBANK
  303. help
  304. Support for error detection and correction on the
  305. Calxeda Highbank memory controller.
  306. config EDAC_OCTEON_PC
  307. tristate "Cavium Octeon Primary Caches"
  308. depends on CPU_CAVIUM_OCTEON
  309. help
  310. Support for error detection and correction on the primary caches of
  311. the cnMIPS cores of Cavium Octeon family SOCs.
  312. config EDAC_OCTEON_L2C
  313. tristate "Cavium Octeon Secondary Caches (L2C)"
  314. depends on CAVIUM_OCTEON_SOC
  315. help
  316. Support for error detection and correction on the
  317. Cavium Octeon family of SOCs.
  318. config EDAC_OCTEON_LMC
  319. tristate "Cavium Octeon DRAM Memory Controller (LMC)"
  320. depends on CAVIUM_OCTEON_SOC
  321. help
  322. Support for error detection and correction on the
  323. Cavium Octeon family of SOCs.
  324. config EDAC_OCTEON_PCI
  325. tristate "Cavium Octeon PCI Controller"
  326. depends on PCI && CAVIUM_OCTEON_SOC
  327. help
  328. Support for error detection and correction on the
  329. Cavium Octeon family of SOCs.
  330. config EDAC_THUNDERX
  331. tristate "Cavium ThunderX EDAC"
  332. depends on ARM64
  333. depends on PCI
  334. help
  335. Support for error detection and correction on the
  336. Cavium ThunderX memory controllers (LMC), Cache
  337. Coherent Processor Interconnect (CCPI) and L2 cache
  338. blocks (TAD, CBC, MCI).
  339. config EDAC_ALTERA
  340. bool "Altera SOCFPGA ECC"
  341. depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
  342. help
  343. Support for error detection and correction on the
  344. Altera SOCs. This is the global enable for the
  345. various Altera peripherals.
  346. config EDAC_ALTERA_SDRAM
  347. bool "Altera SDRAM ECC"
  348. depends on EDAC_ALTERA=y
  349. help
  350. Support for error detection and correction on the
  351. Altera SDRAM Memory for Altera SoCs. Note that the
  352. preloader must initialize the SDRAM before loading
  353. the kernel.
  354. config EDAC_ALTERA_L2C
  355. bool "Altera L2 Cache ECC"
  356. depends on EDAC_ALTERA=y && CACHE_L2X0
  357. help
  358. Support for error detection and correction on the
  359. Altera L2 cache Memory for Altera SoCs. This option
  360. requires L2 cache.
  361. config EDAC_ALTERA_OCRAM
  362. bool "Altera On-Chip RAM ECC"
  363. depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR
  364. help
  365. Support for error detection and correction on the
  366. Altera On-Chip RAM Memory for Altera SoCs.
  367. config EDAC_ALTERA_ETHERNET
  368. bool "Altera Ethernet FIFO ECC"
  369. depends on EDAC_ALTERA=y
  370. help
  371. Support for error detection and correction on the
  372. Altera Ethernet FIFO Memory for Altera SoCs.
  373. config EDAC_ALTERA_NAND
  374. bool "Altera NAND FIFO ECC"
  375. depends on EDAC_ALTERA=y && MTD_NAND_DENALI
  376. help
  377. Support for error detection and correction on the
  378. Altera NAND FIFO Memory for Altera SoCs.
  379. config EDAC_ALTERA_DMA
  380. bool "Altera DMA FIFO ECC"
  381. depends on EDAC_ALTERA=y && PL330_DMA=y
  382. help
  383. Support for error detection and correction on the
  384. Altera DMA FIFO Memory for Altera SoCs.
  385. config EDAC_ALTERA_USB
  386. bool "Altera USB FIFO ECC"
  387. depends on EDAC_ALTERA=y && USB_DWC2
  388. help
  389. Support for error detection and correction on the
  390. Altera USB FIFO Memory for Altera SoCs.
  391. config EDAC_ALTERA_QSPI
  392. bool "Altera QSPI FIFO ECC"
  393. depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI
  394. help
  395. Support for error detection and correction on the
  396. Altera QSPI FIFO Memory for Altera SoCs.
  397. config EDAC_ALTERA_SDMMC
  398. bool "Altera SDMMC FIFO ECC"
  399. depends on EDAC_ALTERA=y && MMC_DW
  400. help
  401. Support for error detection and correction on the
  402. Altera SDMMC FIFO Memory for Altera SoCs.
  403. config EDAC_SIFIVE
  404. bool "Sifive platform EDAC driver"
  405. depends on EDAC=y && SIFIVE_L2
  406. help
  407. Support for error detection and correction on the SiFive SoCs.
  408. config EDAC_ARMADA_XP
  409. bool "Marvell Armada XP DDR and L2 Cache ECC"
  410. depends on MACH_MVEBU_V7
  411. help
  412. Support for error correction and detection on the Marvell Aramada XP
  413. DDR RAM and L2 cache controllers.
  414. config EDAC_SYNOPSYS
  415. tristate "Synopsys DDR Memory Controller"
  416. depends on ARCH_ZYNQ || ARCH_ZYNQMP
  417. help
  418. Support for error detection and correction on the Synopsys DDR
  419. memory controller.
  420. config EDAC_XGENE
  421. tristate "APM X-Gene SoC"
  422. depends on (ARM64 || COMPILE_TEST)
  423. help
  424. Support for error detection and correction on the
  425. APM X-Gene family of SOCs.
  426. config EDAC_TI
  427. tristate "Texas Instruments DDR3 ECC Controller"
  428. depends on ARCH_KEYSTONE || SOC_DRA7XX
  429. help
  430. Support for error detection and correction on the TI SoCs.
  431. config EDAC_QCOM
  432. tristate "QCOM EDAC Controller"
  433. depends on ARCH_QCOM && QCOM_LLCC
  434. help
  435. Support for error detection and correction on the
  436. Qualcomm Technologies, Inc. SoCs.
  437. This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
  438. As of now, it supports error reporting for Last Level Cache Controller (LLCC)
  439. of Tag RAM and Data RAM.
  440. For debugging issues having to do with stability and overall system
  441. health, you should probably say 'Y' here.
  442. config EDAC_ASPEED
  443. tristate "Aspeed AST 2500 SoC"
  444. depends on MACH_ASPEED_G5
  445. help
  446. Support for error detection and correction on the Aspeed AST 2500 SoC.
  447. First, ECC must be configured in the bootloader. Then, this driver
  448. will expose error counters via the EDAC kernel framework.
  449. config EDAC_BLUEFIELD
  450. tristate "Mellanox BlueField Memory ECC"
  451. depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST)
  452. help
  453. Support for error detection and correction on the
  454. Mellanox BlueField SoCs.
  455. config EDAC_DMC520
  456. tristate "ARM DMC-520 ECC"
  457. depends on ARM64
  458. help
  459. Support for error detection and correction on the
  460. SoCs with ARM DMC-520 DRAM controller.
  461. endif # EDAC