xgene-dma.c 49 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Applied Micro X-Gene SoC DMA engine Driver
  4. *
  5. * Copyright (c) 2015, Applied Micro Circuits Corporation
  6. * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
  7. * Loc Ho <lho@apm.com>
  8. *
  9. * NOTE: PM support is currently not available.
  10. */
  11. #include <linux/acpi.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/dmaengine.h>
  16. #include <linux/dmapool.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/io.h>
  19. #include <linux/irq.h>
  20. #include <linux/module.h>
  21. #include <linux/of_device.h>
  22. #include "dmaengine.h"
  23. /* X-Gene DMA ring csr registers and bit definations */
  24. #define XGENE_DMA_RING_CONFIG 0x04
  25. #define XGENE_DMA_RING_ENABLE BIT(31)
  26. #define XGENE_DMA_RING_ID 0x08
  27. #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
  28. #define XGENE_DMA_RING_ID_BUF 0x0C
  29. #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
  30. #define XGENE_DMA_RING_THRESLD0_SET1 0x30
  31. #define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
  32. #define XGENE_DMA_RING_THRESLD1_SET1 0x34
  33. #define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8
  34. #define XGENE_DMA_RING_HYSTERESIS 0x68
  35. #define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF
  36. #define XGENE_DMA_RING_STATE 0x6C
  37. #define XGENE_DMA_RING_STATE_WR_BASE 0x70
  38. #define XGENE_DMA_RING_NE_INT_MODE 0x017C
  39. #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
  40. ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
  41. #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
  42. ((m) &= (~BIT(31 - (v))))
  43. #define XGENE_DMA_RING_CLKEN 0xC208
  44. #define XGENE_DMA_RING_SRST 0xC200
  45. #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070
  46. #define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
  47. #define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF
  48. #define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
  49. #define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
  50. #define XGENE_DMA_RING_CMD_OFFSET 0x2C
  51. #define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
  52. #define XGENE_DMA_RING_COHERENT_SET(m) \
  53. (((u32 *)(m))[2] |= BIT(4))
  54. #define XGENE_DMA_RING_ADDRL_SET(m, v) \
  55. (((u32 *)(m))[2] |= (((v) >> 8) << 5))
  56. #define XGENE_DMA_RING_ADDRH_SET(m, v) \
  57. (((u32 *)(m))[3] |= ((v) >> 35))
  58. #define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
  59. (((u32 *)(m))[3] |= BIT(19))
  60. #define XGENE_DMA_RING_SIZE_SET(m, v) \
  61. (((u32 *)(m))[3] |= ((v) << 23))
  62. #define XGENE_DMA_RING_RECOMBBUF_SET(m) \
  63. (((u32 *)(m))[3] |= BIT(27))
  64. #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \
  65. (((u32 *)(m))[3] |= (0x7 << 28))
  66. #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \
  67. (((u32 *)(m))[4] |= 0x3)
  68. #define XGENE_DMA_RING_SELTHRSH_SET(m) \
  69. (((u32 *)(m))[4] |= BIT(3))
  70. #define XGENE_DMA_RING_TYPE_SET(m, v) \
  71. (((u32 *)(m))[4] |= ((v) << 19))
  72. /* X-Gene DMA device csr registers and bit definitions */
  73. #define XGENE_DMA_IPBRR 0x0
  74. #define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
  75. #define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
  76. #define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
  77. #define XGENE_DMA_GCR 0x10
  78. #define XGENE_DMA_CH_SETUP(v) \
  79. ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
  80. #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
  81. #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
  82. #define XGENE_DMA_RAID6_CONT 0x14
  83. #define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
  84. #define XGENE_DMA_INT 0x70
  85. #define XGENE_DMA_INT_MASK 0x74
  86. #define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF
  87. #define XGENE_DMA_INT_ALL_UNMASK 0x0
  88. #define XGENE_DMA_INT_MASK_SHIFT 0x14
  89. #define XGENE_DMA_RING_INT0_MASK 0x90A0
  90. #define XGENE_DMA_RING_INT1_MASK 0x90A8
  91. #define XGENE_DMA_RING_INT2_MASK 0x90B0
  92. #define XGENE_DMA_RING_INT3_MASK 0x90B8
  93. #define XGENE_DMA_RING_INT4_MASK 0x90C0
  94. #define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0
  95. #define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF
  96. #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
  97. #define XGENE_DMA_BLK_MEM_RDY 0xD074
  98. #define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF
  99. #define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000
  100. /* X-Gene SoC EFUSE csr register and bit defination */
  101. #define XGENE_SOC_JTAG1_SHADOW 0x18
  102. #define XGENE_DMA_PQ_DISABLE_MASK BIT(13)
  103. /* X-Gene DMA Descriptor format */
  104. #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
  105. #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
  106. #define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
  107. #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
  108. #define XGENE_DMA_DESC_ELERR_POS 46
  109. #define XGENE_DMA_DESC_RTYPE_POS 56
  110. #define XGENE_DMA_DESC_LERR_POS 60
  111. #define XGENE_DMA_DESC_BUFLEN_POS 48
  112. #define XGENE_DMA_DESC_HOENQ_NUM_POS 48
  113. #define XGENE_DMA_DESC_ELERR_RD(m) \
  114. (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
  115. #define XGENE_DMA_DESC_LERR_RD(m) \
  116. (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
  117. #define XGENE_DMA_DESC_STATUS(elerr, lerr) \
  118. (((elerr) << 4) | (lerr))
  119. /* X-Gene DMA descriptor empty s/w signature */
  120. #define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
  121. /* X-Gene DMA configurable parameters defines */
  122. #define XGENE_DMA_RING_NUM 512
  123. #define XGENE_DMA_BUFNUM 0x0
  124. #define XGENE_DMA_CPU_BUFNUM 0x18
  125. #define XGENE_DMA_RING_OWNER_DMA 0x03
  126. #define XGENE_DMA_RING_OWNER_CPU 0x0F
  127. #define XGENE_DMA_RING_TYPE_REGULAR 0x01
  128. #define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */
  129. #define XGENE_DMA_RING_NUM_CONFIG 5
  130. #define XGENE_DMA_MAX_CHANNEL 4
  131. #define XGENE_DMA_XOR_CHANNEL 0
  132. #define XGENE_DMA_PQ_CHANNEL 1
  133. #define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
  134. #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
  135. #define XGENE_DMA_MAX_XOR_SRC 5
  136. #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
  137. #define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL
  138. /* X-Gene DMA descriptor error codes */
  139. #define ERR_DESC_AXI 0x01
  140. #define ERR_BAD_DESC 0x02
  141. #define ERR_READ_DATA_AXI 0x03
  142. #define ERR_WRITE_DATA_AXI 0x04
  143. #define ERR_FBP_TIMEOUT 0x05
  144. #define ERR_ECC 0x06
  145. #define ERR_DIFF_SIZE 0x08
  146. #define ERR_SCT_GAT_LEN 0x09
  147. #define ERR_CRC_ERR 0x11
  148. #define ERR_CHKSUM 0x12
  149. #define ERR_DIF 0x13
  150. /* X-Gene DMA error interrupt codes */
  151. #define ERR_DIF_SIZE_INT 0x0
  152. #define ERR_GS_ERR_INT 0x1
  153. #define ERR_FPB_TIMEO_INT 0x2
  154. #define ERR_WFIFO_OVF_INT 0x3
  155. #define ERR_RFIFO_OVF_INT 0x4
  156. #define ERR_WR_TIMEO_INT 0x5
  157. #define ERR_RD_TIMEO_INT 0x6
  158. #define ERR_WR_ERR_INT 0x7
  159. #define ERR_RD_ERR_INT 0x8
  160. #define ERR_BAD_DESC_INT 0x9
  161. #define ERR_DESC_DST_INT 0xA
  162. #define ERR_DESC_SRC_INT 0xB
  163. /* X-Gene DMA flyby operation code */
  164. #define FLYBY_2SRC_XOR 0x80
  165. #define FLYBY_3SRC_XOR 0x90
  166. #define FLYBY_4SRC_XOR 0xA0
  167. #define FLYBY_5SRC_XOR 0xB0
  168. /* X-Gene DMA SW descriptor flags */
  169. #define XGENE_DMA_FLAG_64B_DESC BIT(0)
  170. /* Define to dump X-Gene DMA descriptor */
  171. #define XGENE_DMA_DESC_DUMP(desc, m) \
  172. print_hex_dump(KERN_ERR, (m), \
  173. DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
  174. #define to_dma_desc_sw(tx) \
  175. container_of(tx, struct xgene_dma_desc_sw, tx)
  176. #define to_dma_chan(dchan) \
  177. container_of(dchan, struct xgene_dma_chan, dma_chan)
  178. #define chan_dbg(chan, fmt, arg...) \
  179. dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
  180. #define chan_err(chan, fmt, arg...) \
  181. dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
  182. struct xgene_dma_desc_hw {
  183. __le64 m0;
  184. __le64 m1;
  185. __le64 m2;
  186. __le64 m3;
  187. };
  188. enum xgene_dma_ring_cfgsize {
  189. XGENE_DMA_RING_CFG_SIZE_512B,
  190. XGENE_DMA_RING_CFG_SIZE_2KB,
  191. XGENE_DMA_RING_CFG_SIZE_16KB,
  192. XGENE_DMA_RING_CFG_SIZE_64KB,
  193. XGENE_DMA_RING_CFG_SIZE_512KB,
  194. XGENE_DMA_RING_CFG_SIZE_INVALID
  195. };
  196. struct xgene_dma_ring {
  197. struct xgene_dma *pdma;
  198. u8 buf_num;
  199. u16 id;
  200. u16 num;
  201. u16 head;
  202. u16 owner;
  203. u16 slots;
  204. u16 dst_ring_num;
  205. u32 size;
  206. void __iomem *cmd;
  207. void __iomem *cmd_base;
  208. dma_addr_t desc_paddr;
  209. u32 state[XGENE_DMA_RING_NUM_CONFIG];
  210. enum xgene_dma_ring_cfgsize cfgsize;
  211. union {
  212. void *desc_vaddr;
  213. struct xgene_dma_desc_hw *desc_hw;
  214. };
  215. };
  216. struct xgene_dma_desc_sw {
  217. struct xgene_dma_desc_hw desc1;
  218. struct xgene_dma_desc_hw desc2;
  219. u32 flags;
  220. struct list_head node;
  221. struct list_head tx_list;
  222. struct dma_async_tx_descriptor tx;
  223. };
  224. /**
  225. * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
  226. * @dma_chan: dmaengine channel object member
  227. * @pdma: X-Gene DMA device structure reference
  228. * @dev: struct device reference for dma mapping api
  229. * @id: raw id of this channel
  230. * @rx_irq: channel IRQ
  231. * @name: name of X-Gene DMA channel
  232. * @lock: serializes enqueue/dequeue operations to the descriptor pool
  233. * @pending: number of transaction request pushed to DMA controller for
  234. * execution, but still waiting for completion,
  235. * @max_outstanding: max number of outstanding request we can push to channel
  236. * @ld_pending: descriptors which are queued to run, but have not yet been
  237. * submitted to the hardware for execution
  238. * @ld_running: descriptors which are currently being executing by the hardware
  239. * @ld_completed: descriptors which have finished execution by the hardware.
  240. * These descriptors have already had their cleanup actions run. They
  241. * are waiting for the ACK bit to be set by the async tx API.
  242. * @desc_pool: descriptor pool for DMA operations
  243. * @tasklet: bottom half where all completed descriptors cleans
  244. * @tx_ring: transmit ring descriptor that we use to prepare actual
  245. * descriptors for further executions
  246. * @rx_ring: receive ring descriptor that we use to get completed DMA
  247. * descriptors during cleanup time
  248. */
  249. struct xgene_dma_chan {
  250. struct dma_chan dma_chan;
  251. struct xgene_dma *pdma;
  252. struct device *dev;
  253. int id;
  254. int rx_irq;
  255. char name[10];
  256. spinlock_t lock;
  257. int pending;
  258. int max_outstanding;
  259. struct list_head ld_pending;
  260. struct list_head ld_running;
  261. struct list_head ld_completed;
  262. struct dma_pool *desc_pool;
  263. struct tasklet_struct tasklet;
  264. struct xgene_dma_ring tx_ring;
  265. struct xgene_dma_ring rx_ring;
  266. };
  267. /**
  268. * struct xgene_dma - internal representation of an X-Gene DMA device
  269. * @dev: reference to this device's struct device
  270. * @clk: reference to this device's clock
  271. * @err_irq: DMA error irq number
  272. * @ring_num: start id number for DMA ring
  273. * @csr_dma: base for DMA register access
  274. * @csr_ring: base for DMA ring register access
  275. * @csr_ring_cmd: base for DMA ring command register access
  276. * @csr_efuse: base for efuse register access
  277. * @dma_dev: embedded struct dma_device
  278. * @chan: reference to X-Gene DMA channels
  279. */
  280. struct xgene_dma {
  281. struct device *dev;
  282. struct clk *clk;
  283. int err_irq;
  284. int ring_num;
  285. void __iomem *csr_dma;
  286. void __iomem *csr_ring;
  287. void __iomem *csr_ring_cmd;
  288. void __iomem *csr_efuse;
  289. struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
  290. struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
  291. };
  292. static const char * const xgene_dma_desc_err[] = {
  293. [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
  294. [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
  295. [ERR_READ_DATA_AXI] = "AXI error when reading data",
  296. [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
  297. [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
  298. [ERR_ECC] = "ECC double bit error",
  299. [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
  300. [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
  301. [ERR_CRC_ERR] = "CRC error",
  302. [ERR_CHKSUM] = "Checksum error",
  303. [ERR_DIF] = "DIF error",
  304. };
  305. static const char * const xgene_dma_err[] = {
  306. [ERR_DIF_SIZE_INT] = "DIF size error",
  307. [ERR_GS_ERR_INT] = "Gather scatter not same size error",
  308. [ERR_FPB_TIMEO_INT] = "Free pool time out error",
  309. [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
  310. [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
  311. [ERR_WR_TIMEO_INT] = "Write time out error",
  312. [ERR_RD_TIMEO_INT] = "Read time out error",
  313. [ERR_WR_ERR_INT] = "HBF bus write error",
  314. [ERR_RD_ERR_INT] = "HBF bus read error",
  315. [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
  316. [ERR_DESC_DST_INT] = "HFB reading dst link address error",
  317. [ERR_DESC_SRC_INT] = "HFB reading src link address error",
  318. };
  319. static bool is_pq_enabled(struct xgene_dma *pdma)
  320. {
  321. u32 val;
  322. val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
  323. return !(val & XGENE_DMA_PQ_DISABLE_MASK);
  324. }
  325. static u64 xgene_dma_encode_len(size_t len)
  326. {
  327. return (len < XGENE_DMA_MAX_BYTE_CNT) ?
  328. ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
  329. XGENE_DMA_16K_BUFFER_LEN_CODE;
  330. }
  331. static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
  332. {
  333. static u8 flyby_type[] = {
  334. FLYBY_2SRC_XOR, /* Dummy */
  335. FLYBY_2SRC_XOR, /* Dummy */
  336. FLYBY_2SRC_XOR,
  337. FLYBY_3SRC_XOR,
  338. FLYBY_4SRC_XOR,
  339. FLYBY_5SRC_XOR
  340. };
  341. return flyby_type[src_cnt];
  342. }
  343. static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
  344. dma_addr_t *paddr)
  345. {
  346. size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
  347. *len : XGENE_DMA_MAX_BYTE_CNT;
  348. *ext8 |= cpu_to_le64(*paddr);
  349. *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
  350. *len -= nbytes;
  351. *paddr += nbytes;
  352. }
  353. static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
  354. {
  355. switch (idx) {
  356. case 0:
  357. return &desc->m1;
  358. case 1:
  359. return &desc->m0;
  360. case 2:
  361. return &desc->m3;
  362. case 3:
  363. return &desc->m2;
  364. default:
  365. pr_err("Invalid dma descriptor index\n");
  366. }
  367. return NULL;
  368. }
  369. static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
  370. u16 dst_ring_num)
  371. {
  372. desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
  373. desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
  374. XGENE_DMA_DESC_RTYPE_POS);
  375. desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
  376. desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
  377. XGENE_DMA_DESC_HOENQ_NUM_POS);
  378. }
  379. static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
  380. struct xgene_dma_desc_sw *desc_sw,
  381. dma_addr_t *dst, dma_addr_t *src,
  382. u32 src_cnt, size_t *nbytes,
  383. const u8 *scf)
  384. {
  385. struct xgene_dma_desc_hw *desc1, *desc2;
  386. size_t len = *nbytes;
  387. int i;
  388. desc1 = &desc_sw->desc1;
  389. desc2 = &desc_sw->desc2;
  390. /* Initialize DMA descriptor */
  391. xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
  392. /* Set destination address */
  393. desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
  394. desc1->m3 |= cpu_to_le64(*dst);
  395. /* We have multiple source addresses, so need to set NV bit*/
  396. desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
  397. /* Set flyby opcode */
  398. desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
  399. /* Set 1st to 5th source addresses */
  400. for (i = 0; i < src_cnt; i++) {
  401. len = *nbytes;
  402. xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
  403. xgene_dma_lookup_ext8(desc2, i - 1),
  404. &len, &src[i]);
  405. desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
  406. }
  407. /* Update meta data */
  408. *nbytes = len;
  409. *dst += XGENE_DMA_MAX_BYTE_CNT;
  410. /* We need always 64B descriptor to perform xor or pq operations */
  411. desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
  412. }
  413. static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
  414. {
  415. struct xgene_dma_desc_sw *desc;
  416. struct xgene_dma_chan *chan;
  417. dma_cookie_t cookie;
  418. if (unlikely(!tx))
  419. return -EINVAL;
  420. chan = to_dma_chan(tx->chan);
  421. desc = to_dma_desc_sw(tx);
  422. spin_lock_bh(&chan->lock);
  423. cookie = dma_cookie_assign(tx);
  424. /* Add this transaction list onto the tail of the pending queue */
  425. list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
  426. spin_unlock_bh(&chan->lock);
  427. return cookie;
  428. }
  429. static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
  430. struct xgene_dma_desc_sw *desc)
  431. {
  432. list_del(&desc->node);
  433. chan_dbg(chan, "LD %p free\n", desc);
  434. dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
  435. }
  436. static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
  437. struct xgene_dma_chan *chan)
  438. {
  439. struct xgene_dma_desc_sw *desc;
  440. dma_addr_t phys;
  441. desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
  442. if (!desc) {
  443. chan_err(chan, "Failed to allocate LDs\n");
  444. return NULL;
  445. }
  446. INIT_LIST_HEAD(&desc->tx_list);
  447. desc->tx.phys = phys;
  448. desc->tx.tx_submit = xgene_dma_tx_submit;
  449. dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
  450. chan_dbg(chan, "LD %p allocated\n", desc);
  451. return desc;
  452. }
  453. /**
  454. * xgene_dma_clean_completed_descriptor - free all descriptors which
  455. * has been completed and acked
  456. * @chan: X-Gene DMA channel
  457. *
  458. * This function is used on all completed and acked descriptors.
  459. */
  460. static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
  461. {
  462. struct xgene_dma_desc_sw *desc, *_desc;
  463. /* Run the callback for each descriptor, in order */
  464. list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
  465. if (async_tx_test_ack(&desc->tx))
  466. xgene_dma_clean_descriptor(chan, desc);
  467. }
  468. }
  469. /**
  470. * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
  471. * @chan: X-Gene DMA channel
  472. * @desc: descriptor to cleanup and free
  473. *
  474. * This function is used on a descriptor which has been executed by the DMA
  475. * controller. It will run any callbacks, submit any dependencies.
  476. */
  477. static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
  478. struct xgene_dma_desc_sw *desc)
  479. {
  480. struct dma_async_tx_descriptor *tx = &desc->tx;
  481. /*
  482. * If this is not the last transaction in the group,
  483. * then no need to complete cookie and run any callback as
  484. * this is not the tx_descriptor which had been sent to caller
  485. * of this DMA request
  486. */
  487. if (tx->cookie == 0)
  488. return;
  489. dma_cookie_complete(tx);
  490. dma_descriptor_unmap(tx);
  491. /* Run the link descriptor callback function */
  492. dmaengine_desc_get_callback_invoke(tx, NULL);
  493. /* Run any dependencies */
  494. dma_run_dependencies(tx);
  495. }
  496. /**
  497. * xgene_dma_clean_running_descriptor - move the completed descriptor from
  498. * ld_running to ld_completed
  499. * @chan: X-Gene DMA channel
  500. * @desc: the descriptor which is completed
  501. *
  502. * Free the descriptor directly if acked by async_tx api,
  503. * else move it to queue ld_completed.
  504. */
  505. static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
  506. struct xgene_dma_desc_sw *desc)
  507. {
  508. /* Remove from the list of running transactions */
  509. list_del(&desc->node);
  510. /*
  511. * the client is allowed to attach dependent operations
  512. * until 'ack' is set
  513. */
  514. if (!async_tx_test_ack(&desc->tx)) {
  515. /*
  516. * Move this descriptor to the list of descriptors which is
  517. * completed, but still awaiting the 'ack' bit to be set.
  518. */
  519. list_add_tail(&desc->node, &chan->ld_completed);
  520. return;
  521. }
  522. chan_dbg(chan, "LD %p free\n", desc);
  523. dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
  524. }
  525. static void xgene_chan_xfer_request(struct xgene_dma_chan *chan,
  526. struct xgene_dma_desc_sw *desc_sw)
  527. {
  528. struct xgene_dma_ring *ring = &chan->tx_ring;
  529. struct xgene_dma_desc_hw *desc_hw;
  530. /* Get hw descriptor from DMA tx ring */
  531. desc_hw = &ring->desc_hw[ring->head];
  532. /*
  533. * Increment the head count to point next
  534. * descriptor for next time
  535. */
  536. if (++ring->head == ring->slots)
  537. ring->head = 0;
  538. /* Copy prepared sw descriptor data to hw descriptor */
  539. memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
  540. /*
  541. * Check if we have prepared 64B descriptor,
  542. * in this case we need one more hw descriptor
  543. */
  544. if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
  545. desc_hw = &ring->desc_hw[ring->head];
  546. if (++ring->head == ring->slots)
  547. ring->head = 0;
  548. memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
  549. }
  550. /* Increment the pending transaction count */
  551. chan->pending += ((desc_sw->flags &
  552. XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
  553. /* Notify the hw that we have descriptor ready for execution */
  554. iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
  555. 2 : 1, ring->cmd);
  556. }
  557. /**
  558. * xgene_chan_xfer_ld_pending - push any pending transactions to hw
  559. * @chan : X-Gene DMA channel
  560. *
  561. * LOCKING: must hold chan->lock
  562. */
  563. static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
  564. {
  565. struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
  566. /*
  567. * If the list of pending descriptors is empty, then we
  568. * don't need to do any work at all
  569. */
  570. if (list_empty(&chan->ld_pending)) {
  571. chan_dbg(chan, "No pending LDs\n");
  572. return;
  573. }
  574. /*
  575. * Move elements from the queue of pending transactions onto the list
  576. * of running transactions and push it to hw for further executions
  577. */
  578. list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
  579. /*
  580. * Check if have pushed max number of transactions to hw
  581. * as capable, so let's stop here and will push remaining
  582. * elements from pening ld queue after completing some
  583. * descriptors that we have already pushed
  584. */
  585. if (chan->pending >= chan->max_outstanding)
  586. return;
  587. xgene_chan_xfer_request(chan, desc_sw);
  588. /*
  589. * Delete this element from ld pending queue and append it to
  590. * ld running queue
  591. */
  592. list_move_tail(&desc_sw->node, &chan->ld_running);
  593. }
  594. }
  595. /**
  596. * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
  597. * and move them to ld_completed to free until flag 'ack' is set
  598. * @chan: X-Gene DMA channel
  599. *
  600. * This function is used on descriptors which have been executed by the DMA
  601. * controller. It will run any callbacks, submit any dependencies, then
  602. * free these descriptors if flag 'ack' is set.
  603. */
  604. static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
  605. {
  606. struct xgene_dma_ring *ring = &chan->rx_ring;
  607. struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
  608. struct xgene_dma_desc_hw *desc_hw;
  609. struct list_head ld_completed;
  610. u8 status;
  611. INIT_LIST_HEAD(&ld_completed);
  612. spin_lock(&chan->lock);
  613. /* Clean already completed and acked descriptors */
  614. xgene_dma_clean_completed_descriptor(chan);
  615. /* Move all completed descriptors to ld completed queue, in order */
  616. list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
  617. /* Get subsequent hw descriptor from DMA rx ring */
  618. desc_hw = &ring->desc_hw[ring->head];
  619. /* Check if this descriptor has been completed */
  620. if (unlikely(le64_to_cpu(desc_hw->m0) ==
  621. XGENE_DMA_DESC_EMPTY_SIGNATURE))
  622. break;
  623. if (++ring->head == ring->slots)
  624. ring->head = 0;
  625. /* Check if we have any error with DMA transactions */
  626. status = XGENE_DMA_DESC_STATUS(
  627. XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
  628. desc_hw->m0)),
  629. XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
  630. desc_hw->m0)));
  631. if (status) {
  632. /* Print the DMA error type */
  633. chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
  634. /*
  635. * We have DMA transactions error here. Dump DMA Tx
  636. * and Rx descriptors for this request */
  637. XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
  638. "X-Gene DMA TX DESC1: ");
  639. if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
  640. XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
  641. "X-Gene DMA TX DESC2: ");
  642. XGENE_DMA_DESC_DUMP(desc_hw,
  643. "X-Gene DMA RX ERR DESC: ");
  644. }
  645. /* Notify the hw about this completed descriptor */
  646. iowrite32(-1, ring->cmd);
  647. /* Mark this hw descriptor as processed */
  648. desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
  649. /*
  650. * Decrement the pending transaction count
  651. * as we have processed one
  652. */
  653. chan->pending -= ((desc_sw->flags &
  654. XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
  655. /*
  656. * Delete this node from ld running queue and append it to
  657. * ld completed queue for further processing
  658. */
  659. list_move_tail(&desc_sw->node, &ld_completed);
  660. }
  661. /*
  662. * Start any pending transactions automatically
  663. * In the ideal case, we keep the DMA controller busy while we go
  664. * ahead and free the descriptors below.
  665. */
  666. xgene_chan_xfer_ld_pending(chan);
  667. spin_unlock(&chan->lock);
  668. /* Run the callback for each descriptor, in order */
  669. list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
  670. xgene_dma_run_tx_complete_actions(chan, desc_sw);
  671. xgene_dma_clean_running_descriptor(chan, desc_sw);
  672. }
  673. }
  674. static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
  675. {
  676. struct xgene_dma_chan *chan = to_dma_chan(dchan);
  677. /* Has this channel already been allocated? */
  678. if (chan->desc_pool)
  679. return 1;
  680. chan->desc_pool = dma_pool_create(chan->name, chan->dev,
  681. sizeof(struct xgene_dma_desc_sw),
  682. 0, 0);
  683. if (!chan->desc_pool) {
  684. chan_err(chan, "Failed to allocate descriptor pool\n");
  685. return -ENOMEM;
  686. }
  687. chan_dbg(chan, "Allocate descriptor pool\n");
  688. return 1;
  689. }
  690. /**
  691. * xgene_dma_free_desc_list - Free all descriptors in a queue
  692. * @chan: X-Gene DMA channel
  693. * @list: the list to free
  694. *
  695. * LOCKING: must hold chan->lock
  696. */
  697. static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
  698. struct list_head *list)
  699. {
  700. struct xgene_dma_desc_sw *desc, *_desc;
  701. list_for_each_entry_safe(desc, _desc, list, node)
  702. xgene_dma_clean_descriptor(chan, desc);
  703. }
  704. static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
  705. {
  706. struct xgene_dma_chan *chan = to_dma_chan(dchan);
  707. chan_dbg(chan, "Free all resources\n");
  708. if (!chan->desc_pool)
  709. return;
  710. /* Process all running descriptor */
  711. xgene_dma_cleanup_descriptors(chan);
  712. spin_lock_bh(&chan->lock);
  713. /* Clean all link descriptor queues */
  714. xgene_dma_free_desc_list(chan, &chan->ld_pending);
  715. xgene_dma_free_desc_list(chan, &chan->ld_running);
  716. xgene_dma_free_desc_list(chan, &chan->ld_completed);
  717. spin_unlock_bh(&chan->lock);
  718. /* Delete this channel DMA pool */
  719. dma_pool_destroy(chan->desc_pool);
  720. chan->desc_pool = NULL;
  721. }
  722. static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
  723. struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
  724. u32 src_cnt, size_t len, unsigned long flags)
  725. {
  726. struct xgene_dma_desc_sw *first = NULL, *new;
  727. struct xgene_dma_chan *chan;
  728. static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
  729. 0x01, 0x01, 0x01, 0x01, 0x01};
  730. if (unlikely(!dchan || !len))
  731. return NULL;
  732. chan = to_dma_chan(dchan);
  733. do {
  734. /* Allocate the link descriptor from DMA pool */
  735. new = xgene_dma_alloc_descriptor(chan);
  736. if (!new)
  737. goto fail;
  738. /* Prepare xor DMA descriptor */
  739. xgene_dma_prep_xor_desc(chan, new, &dst, src,
  740. src_cnt, &len, multi);
  741. if (!first)
  742. first = new;
  743. new->tx.cookie = 0;
  744. async_tx_ack(&new->tx);
  745. /* Insert the link descriptor to the LD ring */
  746. list_add_tail(&new->node, &first->tx_list);
  747. } while (len);
  748. new->tx.flags = flags; /* client is in control of this ack */
  749. new->tx.cookie = -EBUSY;
  750. list_splice(&first->tx_list, &new->tx_list);
  751. return &new->tx;
  752. fail:
  753. if (!first)
  754. return NULL;
  755. xgene_dma_free_desc_list(chan, &first->tx_list);
  756. return NULL;
  757. }
  758. static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
  759. struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
  760. u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
  761. {
  762. struct xgene_dma_desc_sw *first = NULL, *new;
  763. struct xgene_dma_chan *chan;
  764. size_t _len = len;
  765. dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
  766. static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
  767. if (unlikely(!dchan || !len))
  768. return NULL;
  769. chan = to_dma_chan(dchan);
  770. /*
  771. * Save source addresses on local variable, may be we have to
  772. * prepare two descriptor to generate P and Q if both enabled
  773. * in the flags by client
  774. */
  775. memcpy(_src, src, sizeof(*src) * src_cnt);
  776. if (flags & DMA_PREP_PQ_DISABLE_P)
  777. len = 0;
  778. if (flags & DMA_PREP_PQ_DISABLE_Q)
  779. _len = 0;
  780. do {
  781. /* Allocate the link descriptor from DMA pool */
  782. new = xgene_dma_alloc_descriptor(chan);
  783. if (!new)
  784. goto fail;
  785. if (!first)
  786. first = new;
  787. new->tx.cookie = 0;
  788. async_tx_ack(&new->tx);
  789. /* Insert the link descriptor to the LD ring */
  790. list_add_tail(&new->node, &first->tx_list);
  791. /*
  792. * Prepare DMA descriptor to generate P,
  793. * if DMA_PREP_PQ_DISABLE_P flag is not set
  794. */
  795. if (len) {
  796. xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
  797. src_cnt, &len, multi);
  798. continue;
  799. }
  800. /*
  801. * Prepare DMA descriptor to generate Q,
  802. * if DMA_PREP_PQ_DISABLE_Q flag is not set
  803. */
  804. if (_len) {
  805. xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
  806. src_cnt, &_len, scf);
  807. }
  808. } while (len || _len);
  809. new->tx.flags = flags; /* client is in control of this ack */
  810. new->tx.cookie = -EBUSY;
  811. list_splice(&first->tx_list, &new->tx_list);
  812. return &new->tx;
  813. fail:
  814. if (!first)
  815. return NULL;
  816. xgene_dma_free_desc_list(chan, &first->tx_list);
  817. return NULL;
  818. }
  819. static void xgene_dma_issue_pending(struct dma_chan *dchan)
  820. {
  821. struct xgene_dma_chan *chan = to_dma_chan(dchan);
  822. spin_lock_bh(&chan->lock);
  823. xgene_chan_xfer_ld_pending(chan);
  824. spin_unlock_bh(&chan->lock);
  825. }
  826. static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
  827. dma_cookie_t cookie,
  828. struct dma_tx_state *txstate)
  829. {
  830. return dma_cookie_status(dchan, cookie, txstate);
  831. }
  832. static void xgene_dma_tasklet_cb(struct tasklet_struct *t)
  833. {
  834. struct xgene_dma_chan *chan = from_tasklet(chan, t, tasklet);
  835. /* Run all cleanup for descriptors which have been completed */
  836. xgene_dma_cleanup_descriptors(chan);
  837. /* Re-enable DMA channel IRQ */
  838. enable_irq(chan->rx_irq);
  839. }
  840. static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
  841. {
  842. struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
  843. BUG_ON(!chan);
  844. /*
  845. * Disable DMA channel IRQ until we process completed
  846. * descriptors
  847. */
  848. disable_irq_nosync(chan->rx_irq);
  849. /*
  850. * Schedule the tasklet to handle all cleanup of the current
  851. * transaction. It will start a new transaction if there is
  852. * one pending.
  853. */
  854. tasklet_schedule(&chan->tasklet);
  855. return IRQ_HANDLED;
  856. }
  857. static irqreturn_t xgene_dma_err_isr(int irq, void *id)
  858. {
  859. struct xgene_dma *pdma = (struct xgene_dma *)id;
  860. unsigned long int_mask;
  861. u32 val, i;
  862. val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
  863. /* Clear DMA interrupts */
  864. iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
  865. /* Print DMA error info */
  866. int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
  867. for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
  868. dev_err(pdma->dev,
  869. "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
  870. return IRQ_HANDLED;
  871. }
  872. static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
  873. {
  874. int i;
  875. iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
  876. for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
  877. iowrite32(ring->state[i], ring->pdma->csr_ring +
  878. XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
  879. }
  880. static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
  881. {
  882. memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
  883. xgene_dma_wr_ring_state(ring);
  884. }
  885. static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
  886. {
  887. void *ring_cfg = ring->state;
  888. u64 addr = ring->desc_paddr;
  889. u32 i, val;
  890. ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
  891. /* Clear DMA ring state */
  892. xgene_dma_clr_ring_state(ring);
  893. /* Set DMA ring type */
  894. XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
  895. if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
  896. /* Set recombination buffer and timeout */
  897. XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
  898. XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
  899. XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
  900. }
  901. /* Initialize DMA ring state */
  902. XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
  903. XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
  904. XGENE_DMA_RING_COHERENT_SET(ring_cfg);
  905. XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
  906. XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
  907. XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
  908. /* Write DMA ring configurations */
  909. xgene_dma_wr_ring_state(ring);
  910. /* Set DMA ring id */
  911. iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
  912. ring->pdma->csr_ring + XGENE_DMA_RING_ID);
  913. /* Set DMA ring buffer */
  914. iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
  915. ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
  916. if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
  917. return;
  918. /* Set empty signature to DMA Rx ring descriptors */
  919. for (i = 0; i < ring->slots; i++) {
  920. struct xgene_dma_desc_hw *desc;
  921. desc = &ring->desc_hw[i];
  922. desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
  923. }
  924. /* Enable DMA Rx ring interrupt */
  925. val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
  926. XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
  927. iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
  928. }
  929. static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
  930. {
  931. u32 ring_id, val;
  932. if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
  933. /* Disable DMA Rx ring interrupt */
  934. val = ioread32(ring->pdma->csr_ring +
  935. XGENE_DMA_RING_NE_INT_MODE);
  936. XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
  937. iowrite32(val, ring->pdma->csr_ring +
  938. XGENE_DMA_RING_NE_INT_MODE);
  939. }
  940. /* Clear DMA ring state */
  941. ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
  942. iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
  943. iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
  944. xgene_dma_clr_ring_state(ring);
  945. }
  946. static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
  947. {
  948. ring->cmd_base = ring->pdma->csr_ring_cmd +
  949. XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
  950. XGENE_DMA_RING_NUM));
  951. ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
  952. }
  953. static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
  954. enum xgene_dma_ring_cfgsize cfgsize)
  955. {
  956. int size;
  957. switch (cfgsize) {
  958. case XGENE_DMA_RING_CFG_SIZE_512B:
  959. size = 0x200;
  960. break;
  961. case XGENE_DMA_RING_CFG_SIZE_2KB:
  962. size = 0x800;
  963. break;
  964. case XGENE_DMA_RING_CFG_SIZE_16KB:
  965. size = 0x4000;
  966. break;
  967. case XGENE_DMA_RING_CFG_SIZE_64KB:
  968. size = 0x10000;
  969. break;
  970. case XGENE_DMA_RING_CFG_SIZE_512KB:
  971. size = 0x80000;
  972. break;
  973. default:
  974. chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
  975. return -EINVAL;
  976. }
  977. return size;
  978. }
  979. static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
  980. {
  981. /* Clear DMA ring configurations */
  982. xgene_dma_clear_ring(ring);
  983. /* De-allocate DMA ring descriptor */
  984. if (ring->desc_vaddr) {
  985. dma_free_coherent(ring->pdma->dev, ring->size,
  986. ring->desc_vaddr, ring->desc_paddr);
  987. ring->desc_vaddr = NULL;
  988. }
  989. }
  990. static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
  991. {
  992. xgene_dma_delete_ring_one(&chan->rx_ring);
  993. xgene_dma_delete_ring_one(&chan->tx_ring);
  994. }
  995. static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
  996. struct xgene_dma_ring *ring,
  997. enum xgene_dma_ring_cfgsize cfgsize)
  998. {
  999. int ret;
  1000. /* Setup DMA ring descriptor variables */
  1001. ring->pdma = chan->pdma;
  1002. ring->cfgsize = cfgsize;
  1003. ring->num = chan->pdma->ring_num++;
  1004. ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
  1005. ret = xgene_dma_get_ring_size(chan, cfgsize);
  1006. if (ret <= 0)
  1007. return ret;
  1008. ring->size = ret;
  1009. /* Allocate memory for DMA ring descriptor */
  1010. ring->desc_vaddr = dma_alloc_coherent(chan->dev, ring->size,
  1011. &ring->desc_paddr, GFP_KERNEL);
  1012. if (!ring->desc_vaddr) {
  1013. chan_err(chan, "Failed to allocate ring desc\n");
  1014. return -ENOMEM;
  1015. }
  1016. /* Configure and enable DMA ring */
  1017. xgene_dma_set_ring_cmd(ring);
  1018. xgene_dma_setup_ring(ring);
  1019. return 0;
  1020. }
  1021. static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
  1022. {
  1023. struct xgene_dma_ring *rx_ring = &chan->rx_ring;
  1024. struct xgene_dma_ring *tx_ring = &chan->tx_ring;
  1025. int ret;
  1026. /* Create DMA Rx ring descriptor */
  1027. rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
  1028. rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
  1029. ret = xgene_dma_create_ring_one(chan, rx_ring,
  1030. XGENE_DMA_RING_CFG_SIZE_64KB);
  1031. if (ret)
  1032. return ret;
  1033. chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
  1034. rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
  1035. /* Create DMA Tx ring descriptor */
  1036. tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
  1037. tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
  1038. ret = xgene_dma_create_ring_one(chan, tx_ring,
  1039. XGENE_DMA_RING_CFG_SIZE_64KB);
  1040. if (ret) {
  1041. xgene_dma_delete_ring_one(rx_ring);
  1042. return ret;
  1043. }
  1044. tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
  1045. chan_dbg(chan,
  1046. "Tx ring id 0x%X num %d desc 0x%p\n",
  1047. tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
  1048. /* Set the max outstanding request possible to this channel */
  1049. chan->max_outstanding = tx_ring->slots;
  1050. return ret;
  1051. }
  1052. static int xgene_dma_init_rings(struct xgene_dma *pdma)
  1053. {
  1054. int ret, i, j;
  1055. for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
  1056. ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
  1057. if (ret) {
  1058. for (j = 0; j < i; j++)
  1059. xgene_dma_delete_chan_rings(&pdma->chan[j]);
  1060. return ret;
  1061. }
  1062. }
  1063. return ret;
  1064. }
  1065. static void xgene_dma_enable(struct xgene_dma *pdma)
  1066. {
  1067. u32 val;
  1068. /* Configure and enable DMA engine */
  1069. val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
  1070. XGENE_DMA_CH_SETUP(val);
  1071. XGENE_DMA_ENABLE(val);
  1072. iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
  1073. }
  1074. static void xgene_dma_disable(struct xgene_dma *pdma)
  1075. {
  1076. u32 val;
  1077. val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
  1078. XGENE_DMA_DISABLE(val);
  1079. iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
  1080. }
  1081. static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
  1082. {
  1083. /*
  1084. * Mask DMA ring overflow, underflow and
  1085. * AXI write/read error interrupts
  1086. */
  1087. iowrite32(XGENE_DMA_INT_ALL_MASK,
  1088. pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
  1089. iowrite32(XGENE_DMA_INT_ALL_MASK,
  1090. pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
  1091. iowrite32(XGENE_DMA_INT_ALL_MASK,
  1092. pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
  1093. iowrite32(XGENE_DMA_INT_ALL_MASK,
  1094. pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
  1095. iowrite32(XGENE_DMA_INT_ALL_MASK,
  1096. pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
  1097. /* Mask DMA error interrupts */
  1098. iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
  1099. }
  1100. static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
  1101. {
  1102. /*
  1103. * Unmask DMA ring overflow, underflow and
  1104. * AXI write/read error interrupts
  1105. */
  1106. iowrite32(XGENE_DMA_INT_ALL_UNMASK,
  1107. pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
  1108. iowrite32(XGENE_DMA_INT_ALL_UNMASK,
  1109. pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
  1110. iowrite32(XGENE_DMA_INT_ALL_UNMASK,
  1111. pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
  1112. iowrite32(XGENE_DMA_INT_ALL_UNMASK,
  1113. pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
  1114. iowrite32(XGENE_DMA_INT_ALL_UNMASK,
  1115. pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
  1116. /* Unmask DMA error interrupts */
  1117. iowrite32(XGENE_DMA_INT_ALL_UNMASK,
  1118. pdma->csr_dma + XGENE_DMA_INT_MASK);
  1119. }
  1120. static void xgene_dma_init_hw(struct xgene_dma *pdma)
  1121. {
  1122. u32 val;
  1123. /* Associate DMA ring to corresponding ring HW */
  1124. iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
  1125. pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
  1126. /* Configure RAID6 polynomial control setting */
  1127. if (is_pq_enabled(pdma))
  1128. iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
  1129. pdma->csr_dma + XGENE_DMA_RAID6_CONT);
  1130. else
  1131. dev_info(pdma->dev, "PQ is disabled in HW\n");
  1132. xgene_dma_enable(pdma);
  1133. xgene_dma_unmask_interrupts(pdma);
  1134. /* Get DMA id and version info */
  1135. val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
  1136. /* DMA device info */
  1137. dev_info(pdma->dev,
  1138. "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
  1139. XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
  1140. XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
  1141. }
  1142. static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
  1143. {
  1144. if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
  1145. (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
  1146. return 0;
  1147. iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
  1148. iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
  1149. /* Bring up memory */
  1150. iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
  1151. /* Force a barrier */
  1152. ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
  1153. /* reset may take up to 1ms */
  1154. usleep_range(1000, 1100);
  1155. if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
  1156. != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
  1157. dev_err(pdma->dev,
  1158. "Failed to release ring mngr memory from shutdown\n");
  1159. return -ENODEV;
  1160. }
  1161. /* program threshold set 1 and all hysteresis */
  1162. iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
  1163. pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
  1164. iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
  1165. pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
  1166. iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
  1167. pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
  1168. /* Enable QPcore and assign error queue */
  1169. iowrite32(XGENE_DMA_RING_ENABLE,
  1170. pdma->csr_ring + XGENE_DMA_RING_CONFIG);
  1171. return 0;
  1172. }
  1173. static int xgene_dma_init_mem(struct xgene_dma *pdma)
  1174. {
  1175. int ret;
  1176. ret = xgene_dma_init_ring_mngr(pdma);
  1177. if (ret)
  1178. return ret;
  1179. /* Bring up memory */
  1180. iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
  1181. /* Force a barrier */
  1182. ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
  1183. /* reset may take up to 1ms */
  1184. usleep_range(1000, 1100);
  1185. if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
  1186. != XGENE_DMA_BLK_MEM_RDY_VAL) {
  1187. dev_err(pdma->dev,
  1188. "Failed to release DMA memory from shutdown\n");
  1189. return -ENODEV;
  1190. }
  1191. return 0;
  1192. }
  1193. static int xgene_dma_request_irqs(struct xgene_dma *pdma)
  1194. {
  1195. struct xgene_dma_chan *chan;
  1196. int ret, i, j;
  1197. /* Register DMA error irq */
  1198. ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
  1199. 0, "dma_error", pdma);
  1200. if (ret) {
  1201. dev_err(pdma->dev,
  1202. "Failed to register error IRQ %d\n", pdma->err_irq);
  1203. return ret;
  1204. }
  1205. /* Register DMA channel rx irq */
  1206. for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
  1207. chan = &pdma->chan[i];
  1208. irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
  1209. ret = devm_request_irq(chan->dev, chan->rx_irq,
  1210. xgene_dma_chan_ring_isr,
  1211. 0, chan->name, chan);
  1212. if (ret) {
  1213. chan_err(chan, "Failed to register Rx IRQ %d\n",
  1214. chan->rx_irq);
  1215. devm_free_irq(pdma->dev, pdma->err_irq, pdma);
  1216. for (j = 0; j < i; j++) {
  1217. chan = &pdma->chan[i];
  1218. irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
  1219. devm_free_irq(chan->dev, chan->rx_irq, chan);
  1220. }
  1221. return ret;
  1222. }
  1223. }
  1224. return 0;
  1225. }
  1226. static void xgene_dma_free_irqs(struct xgene_dma *pdma)
  1227. {
  1228. struct xgene_dma_chan *chan;
  1229. int i;
  1230. /* Free DMA device error irq */
  1231. devm_free_irq(pdma->dev, pdma->err_irq, pdma);
  1232. for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
  1233. chan = &pdma->chan[i];
  1234. irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
  1235. devm_free_irq(chan->dev, chan->rx_irq, chan);
  1236. }
  1237. }
  1238. static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
  1239. struct dma_device *dma_dev)
  1240. {
  1241. /* Initialize DMA device capability mask */
  1242. dma_cap_zero(dma_dev->cap_mask);
  1243. /* Set DMA device capability */
  1244. /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
  1245. * and channel 1 supports XOR, PQ both. First thing here is we have
  1246. * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
  1247. * we can make sure this by reading SoC Efuse register.
  1248. * Second thing, we have hw errata that if we run channel 0 and
  1249. * channel 1 simultaneously with executing XOR and PQ request,
  1250. * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
  1251. * if XOR and PQ supports on channel 1 is disabled.
  1252. */
  1253. if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
  1254. is_pq_enabled(chan->pdma)) {
  1255. dma_cap_set(DMA_PQ, dma_dev->cap_mask);
  1256. dma_cap_set(DMA_XOR, dma_dev->cap_mask);
  1257. } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
  1258. !is_pq_enabled(chan->pdma)) {
  1259. dma_cap_set(DMA_XOR, dma_dev->cap_mask);
  1260. }
  1261. /* Set base and prep routines */
  1262. dma_dev->dev = chan->dev;
  1263. dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
  1264. dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
  1265. dma_dev->device_issue_pending = xgene_dma_issue_pending;
  1266. dma_dev->device_tx_status = xgene_dma_tx_status;
  1267. if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
  1268. dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
  1269. dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
  1270. dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES;
  1271. }
  1272. if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
  1273. dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
  1274. dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
  1275. dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES;
  1276. }
  1277. }
  1278. static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
  1279. {
  1280. struct xgene_dma_chan *chan = &pdma->chan[id];
  1281. struct dma_device *dma_dev = &pdma->dma_dev[id];
  1282. int ret;
  1283. chan->dma_chan.device = dma_dev;
  1284. spin_lock_init(&chan->lock);
  1285. INIT_LIST_HEAD(&chan->ld_pending);
  1286. INIT_LIST_HEAD(&chan->ld_running);
  1287. INIT_LIST_HEAD(&chan->ld_completed);
  1288. tasklet_setup(&chan->tasklet, xgene_dma_tasklet_cb);
  1289. chan->pending = 0;
  1290. chan->desc_pool = NULL;
  1291. dma_cookie_init(&chan->dma_chan);
  1292. /* Setup dma device capabilities and prep routines */
  1293. xgene_dma_set_caps(chan, dma_dev);
  1294. /* Initialize DMA device list head */
  1295. INIT_LIST_HEAD(&dma_dev->channels);
  1296. list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
  1297. /* Register with Linux async DMA framework*/
  1298. ret = dma_async_device_register(dma_dev);
  1299. if (ret) {
  1300. chan_err(chan, "Failed to register async device %d", ret);
  1301. tasklet_kill(&chan->tasklet);
  1302. return ret;
  1303. }
  1304. /* DMA capability info */
  1305. dev_info(pdma->dev,
  1306. "%s: CAPABILITY ( %s%s)\n", dma_chan_name(&chan->dma_chan),
  1307. dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
  1308. dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
  1309. return 0;
  1310. }
  1311. static int xgene_dma_init_async(struct xgene_dma *pdma)
  1312. {
  1313. int ret, i, j;
  1314. for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
  1315. ret = xgene_dma_async_register(pdma, i);
  1316. if (ret) {
  1317. for (j = 0; j < i; j++) {
  1318. dma_async_device_unregister(&pdma->dma_dev[j]);
  1319. tasklet_kill(&pdma->chan[j].tasklet);
  1320. }
  1321. return ret;
  1322. }
  1323. }
  1324. return ret;
  1325. }
  1326. static void xgene_dma_async_unregister(struct xgene_dma *pdma)
  1327. {
  1328. int i;
  1329. for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
  1330. dma_async_device_unregister(&pdma->dma_dev[i]);
  1331. }
  1332. static void xgene_dma_init_channels(struct xgene_dma *pdma)
  1333. {
  1334. struct xgene_dma_chan *chan;
  1335. int i;
  1336. pdma->ring_num = XGENE_DMA_RING_NUM;
  1337. for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
  1338. chan = &pdma->chan[i];
  1339. chan->dev = pdma->dev;
  1340. chan->pdma = pdma;
  1341. chan->id = i;
  1342. snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
  1343. }
  1344. }
  1345. static int xgene_dma_get_resources(struct platform_device *pdev,
  1346. struct xgene_dma *pdma)
  1347. {
  1348. struct resource *res;
  1349. int irq, i;
  1350. /* Get DMA csr region */
  1351. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1352. if (!res) {
  1353. dev_err(&pdev->dev, "Failed to get csr region\n");
  1354. return -ENXIO;
  1355. }
  1356. pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
  1357. resource_size(res));
  1358. if (!pdma->csr_dma) {
  1359. dev_err(&pdev->dev, "Failed to ioremap csr region");
  1360. return -ENOMEM;
  1361. }
  1362. /* Get DMA ring csr region */
  1363. res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1364. if (!res) {
  1365. dev_err(&pdev->dev, "Failed to get ring csr region\n");
  1366. return -ENXIO;
  1367. }
  1368. pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
  1369. resource_size(res));
  1370. if (!pdma->csr_ring) {
  1371. dev_err(&pdev->dev, "Failed to ioremap ring csr region");
  1372. return -ENOMEM;
  1373. }
  1374. /* Get DMA ring cmd csr region */
  1375. res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
  1376. if (!res) {
  1377. dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
  1378. return -ENXIO;
  1379. }
  1380. pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
  1381. resource_size(res));
  1382. if (!pdma->csr_ring_cmd) {
  1383. dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
  1384. return -ENOMEM;
  1385. }
  1386. pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
  1387. /* Get efuse csr region */
  1388. res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
  1389. if (!res) {
  1390. dev_err(&pdev->dev, "Failed to get efuse csr region\n");
  1391. return -ENXIO;
  1392. }
  1393. pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
  1394. resource_size(res));
  1395. if (!pdma->csr_efuse) {
  1396. dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
  1397. return -ENOMEM;
  1398. }
  1399. /* Get DMA error interrupt */
  1400. irq = platform_get_irq(pdev, 0);
  1401. if (irq <= 0)
  1402. return -ENXIO;
  1403. pdma->err_irq = irq;
  1404. /* Get DMA Rx ring descriptor interrupts for all DMA channels */
  1405. for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
  1406. irq = platform_get_irq(pdev, i);
  1407. if (irq <= 0)
  1408. return -ENXIO;
  1409. pdma->chan[i - 1].rx_irq = irq;
  1410. }
  1411. return 0;
  1412. }
  1413. static int xgene_dma_probe(struct platform_device *pdev)
  1414. {
  1415. struct xgene_dma *pdma;
  1416. int ret, i;
  1417. pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
  1418. if (!pdma)
  1419. return -ENOMEM;
  1420. pdma->dev = &pdev->dev;
  1421. platform_set_drvdata(pdev, pdma);
  1422. ret = xgene_dma_get_resources(pdev, pdma);
  1423. if (ret)
  1424. return ret;
  1425. pdma->clk = devm_clk_get(&pdev->dev, NULL);
  1426. if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
  1427. dev_err(&pdev->dev, "Failed to get clk\n");
  1428. return PTR_ERR(pdma->clk);
  1429. }
  1430. /* Enable clk before accessing registers */
  1431. if (!IS_ERR(pdma->clk)) {
  1432. ret = clk_prepare_enable(pdma->clk);
  1433. if (ret) {
  1434. dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
  1435. return ret;
  1436. }
  1437. }
  1438. /* Remove DMA RAM out of shutdown */
  1439. ret = xgene_dma_init_mem(pdma);
  1440. if (ret)
  1441. goto err_clk_enable;
  1442. ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
  1443. if (ret) {
  1444. dev_err(&pdev->dev, "No usable DMA configuration\n");
  1445. goto err_dma_mask;
  1446. }
  1447. /* Initialize DMA channels software state */
  1448. xgene_dma_init_channels(pdma);
  1449. /* Configue DMA rings */
  1450. ret = xgene_dma_init_rings(pdma);
  1451. if (ret)
  1452. goto err_clk_enable;
  1453. ret = xgene_dma_request_irqs(pdma);
  1454. if (ret)
  1455. goto err_request_irq;
  1456. /* Configure and enable DMA engine */
  1457. xgene_dma_init_hw(pdma);
  1458. /* Register DMA device with linux async framework */
  1459. ret = xgene_dma_init_async(pdma);
  1460. if (ret)
  1461. goto err_async_init;
  1462. return 0;
  1463. err_async_init:
  1464. xgene_dma_free_irqs(pdma);
  1465. err_request_irq:
  1466. for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
  1467. xgene_dma_delete_chan_rings(&pdma->chan[i]);
  1468. err_dma_mask:
  1469. err_clk_enable:
  1470. if (!IS_ERR(pdma->clk))
  1471. clk_disable_unprepare(pdma->clk);
  1472. return ret;
  1473. }
  1474. static int xgene_dma_remove(struct platform_device *pdev)
  1475. {
  1476. struct xgene_dma *pdma = platform_get_drvdata(pdev);
  1477. struct xgene_dma_chan *chan;
  1478. int i;
  1479. xgene_dma_async_unregister(pdma);
  1480. /* Mask interrupts and disable DMA engine */
  1481. xgene_dma_mask_interrupts(pdma);
  1482. xgene_dma_disable(pdma);
  1483. xgene_dma_free_irqs(pdma);
  1484. for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
  1485. chan = &pdma->chan[i];
  1486. tasklet_kill(&chan->tasklet);
  1487. xgene_dma_delete_chan_rings(chan);
  1488. }
  1489. if (!IS_ERR(pdma->clk))
  1490. clk_disable_unprepare(pdma->clk);
  1491. return 0;
  1492. }
  1493. #ifdef CONFIG_ACPI
  1494. static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = {
  1495. {"APMC0D43", 0},
  1496. {},
  1497. };
  1498. MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr);
  1499. #endif
  1500. static const struct of_device_id xgene_dma_of_match_ptr[] = {
  1501. {.compatible = "apm,xgene-storm-dma",},
  1502. {},
  1503. };
  1504. MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
  1505. static struct platform_driver xgene_dma_driver = {
  1506. .probe = xgene_dma_probe,
  1507. .remove = xgene_dma_remove,
  1508. .driver = {
  1509. .name = "X-Gene-DMA",
  1510. .of_match_table = xgene_dma_of_match_ptr,
  1511. .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr),
  1512. },
  1513. };
  1514. module_platform_driver(xgene_dma_driver);
  1515. MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
  1516. MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
  1517. MODULE_AUTHOR("Loc Ho <lho@apm.com>");
  1518. MODULE_LICENSE("GPL");
  1519. MODULE_VERSION("1.0");