timb_dma.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * timb_dma.c timberdale FPGA DMA driver
  4. * Copyright (c) 2010 Intel Corporation
  5. */
  6. /* Supports:
  7. * Timberdale FPGA DMA engine
  8. */
  9. #include <linux/dmaengine.h>
  10. #include <linux/dma-mapping.h>
  11. #include <linux/init.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/timb_dma.h>
  18. #include "dmaengine.h"
  19. #define DRIVER_NAME "timb-dma"
  20. /* Global DMA registers */
  21. #define TIMBDMA_ACR 0x34
  22. #define TIMBDMA_32BIT_ADDR 0x01
  23. #define TIMBDMA_ISR 0x080000
  24. #define TIMBDMA_IPR 0x080004
  25. #define TIMBDMA_IER 0x080008
  26. /* Channel specific registers */
  27. /* RX instances base addresses are 0x00, 0x40, 0x80 ...
  28. * TX instances base addresses are 0x18, 0x58, 0x98 ...
  29. */
  30. #define TIMBDMA_INSTANCE_OFFSET 0x40
  31. #define TIMBDMA_INSTANCE_TX_OFFSET 0x18
  32. /* RX registers, relative the instance base */
  33. #define TIMBDMA_OFFS_RX_DHAR 0x00
  34. #define TIMBDMA_OFFS_RX_DLAR 0x04
  35. #define TIMBDMA_OFFS_RX_LR 0x0C
  36. #define TIMBDMA_OFFS_RX_BLR 0x10
  37. #define TIMBDMA_OFFS_RX_ER 0x14
  38. #define TIMBDMA_RX_EN 0x01
  39. /* bytes per Row, video specific register
  40. * which is placed after the TX registers...
  41. */
  42. #define TIMBDMA_OFFS_RX_BPRR 0x30
  43. /* TX registers, relative the instance base */
  44. #define TIMBDMA_OFFS_TX_DHAR 0x00
  45. #define TIMBDMA_OFFS_TX_DLAR 0x04
  46. #define TIMBDMA_OFFS_TX_BLR 0x0C
  47. #define TIMBDMA_OFFS_TX_LR 0x14
  48. #define TIMB_DMA_DESC_SIZE 8
  49. struct timb_dma_desc {
  50. struct list_head desc_node;
  51. struct dma_async_tx_descriptor txd;
  52. u8 *desc_list;
  53. unsigned int desc_list_len;
  54. bool interrupt;
  55. };
  56. struct timb_dma_chan {
  57. struct dma_chan chan;
  58. void __iomem *membase;
  59. spinlock_t lock; /* Used to protect data structures,
  60. especially the lists and descriptors,
  61. from races between the tasklet and calls
  62. from above */
  63. bool ongoing;
  64. struct list_head active_list;
  65. struct list_head queue;
  66. struct list_head free_list;
  67. unsigned int bytes_per_line;
  68. enum dma_transfer_direction direction;
  69. unsigned int descs; /* Descriptors to allocate */
  70. unsigned int desc_elems; /* number of elems per descriptor */
  71. };
  72. struct timb_dma {
  73. struct dma_device dma;
  74. void __iomem *membase;
  75. struct tasklet_struct tasklet;
  76. struct timb_dma_chan channels[];
  77. };
  78. static struct device *chan2dev(struct dma_chan *chan)
  79. {
  80. return &chan->dev->device;
  81. }
  82. static struct device *chan2dmadev(struct dma_chan *chan)
  83. {
  84. return chan2dev(chan)->parent->parent;
  85. }
  86. static struct timb_dma *tdchantotd(struct timb_dma_chan *td_chan)
  87. {
  88. int id = td_chan->chan.chan_id;
  89. return (struct timb_dma *)((u8 *)td_chan -
  90. id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
  91. }
  92. /* Must be called with the spinlock held */
  93. static void __td_enable_chan_irq(struct timb_dma_chan *td_chan)
  94. {
  95. int id = td_chan->chan.chan_id;
  96. struct timb_dma *td = tdchantotd(td_chan);
  97. u32 ier;
  98. /* enable interrupt for this channel */
  99. ier = ioread32(td->membase + TIMBDMA_IER);
  100. ier |= 1 << id;
  101. dev_dbg(chan2dev(&td_chan->chan), "Enabling irq: %d, IER: 0x%x\n", id,
  102. ier);
  103. iowrite32(ier, td->membase + TIMBDMA_IER);
  104. }
  105. /* Should be called with the spinlock held */
  106. static bool __td_dma_done_ack(struct timb_dma_chan *td_chan)
  107. {
  108. int id = td_chan->chan.chan_id;
  109. struct timb_dma *td = (struct timb_dma *)((u8 *)td_chan -
  110. id * sizeof(struct timb_dma_chan) - sizeof(struct timb_dma));
  111. u32 isr;
  112. bool done = false;
  113. dev_dbg(chan2dev(&td_chan->chan), "Checking irq: %d, td: %p\n", id, td);
  114. isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id);
  115. if (isr) {
  116. iowrite32(isr, td->membase + TIMBDMA_ISR);
  117. done = true;
  118. }
  119. return done;
  120. }
  121. static int td_fill_desc(struct timb_dma_chan *td_chan, u8 *dma_desc,
  122. struct scatterlist *sg, bool last)
  123. {
  124. if (sg_dma_len(sg) > USHRT_MAX) {
  125. dev_err(chan2dev(&td_chan->chan), "Too big sg element\n");
  126. return -EINVAL;
  127. }
  128. /* length must be word aligned */
  129. if (sg_dma_len(sg) % sizeof(u32)) {
  130. dev_err(chan2dev(&td_chan->chan), "Incorrect length: %d\n",
  131. sg_dma_len(sg));
  132. return -EINVAL;
  133. }
  134. dev_dbg(chan2dev(&td_chan->chan), "desc: %p, addr: 0x%llx\n",
  135. dma_desc, (unsigned long long)sg_dma_address(sg));
  136. dma_desc[7] = (sg_dma_address(sg) >> 24) & 0xff;
  137. dma_desc[6] = (sg_dma_address(sg) >> 16) & 0xff;
  138. dma_desc[5] = (sg_dma_address(sg) >> 8) & 0xff;
  139. dma_desc[4] = (sg_dma_address(sg) >> 0) & 0xff;
  140. dma_desc[3] = (sg_dma_len(sg) >> 8) & 0xff;
  141. dma_desc[2] = (sg_dma_len(sg) >> 0) & 0xff;
  142. dma_desc[1] = 0x00;
  143. dma_desc[0] = 0x21 | (last ? 0x02 : 0); /* tran, valid */
  144. return 0;
  145. }
  146. /* Must be called with the spinlock held */
  147. static void __td_start_dma(struct timb_dma_chan *td_chan)
  148. {
  149. struct timb_dma_desc *td_desc;
  150. if (td_chan->ongoing) {
  151. dev_err(chan2dev(&td_chan->chan),
  152. "Transfer already ongoing\n");
  153. return;
  154. }
  155. td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
  156. desc_node);
  157. dev_dbg(chan2dev(&td_chan->chan),
  158. "td_chan: %p, chan: %d, membase: %p\n",
  159. td_chan, td_chan->chan.chan_id, td_chan->membase);
  160. if (td_chan->direction == DMA_DEV_TO_MEM) {
  161. /* descriptor address */
  162. iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR);
  163. iowrite32(td_desc->txd.phys, td_chan->membase +
  164. TIMBDMA_OFFS_RX_DLAR);
  165. /* Bytes per line */
  166. iowrite32(td_chan->bytes_per_line, td_chan->membase +
  167. TIMBDMA_OFFS_RX_BPRR);
  168. /* enable RX */
  169. iowrite32(TIMBDMA_RX_EN, td_chan->membase + TIMBDMA_OFFS_RX_ER);
  170. } else {
  171. /* address high */
  172. iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DHAR);
  173. iowrite32(td_desc->txd.phys, td_chan->membase +
  174. TIMBDMA_OFFS_TX_DLAR);
  175. }
  176. td_chan->ongoing = true;
  177. if (td_desc->interrupt)
  178. __td_enable_chan_irq(td_chan);
  179. }
  180. static void __td_finish(struct timb_dma_chan *td_chan)
  181. {
  182. struct dmaengine_desc_callback cb;
  183. struct dma_async_tx_descriptor *txd;
  184. struct timb_dma_desc *td_desc;
  185. /* can happen if the descriptor is canceled */
  186. if (list_empty(&td_chan->active_list))
  187. return;
  188. td_desc = list_entry(td_chan->active_list.next, struct timb_dma_desc,
  189. desc_node);
  190. txd = &td_desc->txd;
  191. dev_dbg(chan2dev(&td_chan->chan), "descriptor %u complete\n",
  192. txd->cookie);
  193. /* make sure to stop the transfer */
  194. if (td_chan->direction == DMA_DEV_TO_MEM)
  195. iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_ER);
  196. /* Currently no support for stopping DMA transfers
  197. else
  198. iowrite32(0, td_chan->membase + TIMBDMA_OFFS_TX_DLAR);
  199. */
  200. dma_cookie_complete(txd);
  201. td_chan->ongoing = false;
  202. dmaengine_desc_get_callback(txd, &cb);
  203. list_move(&td_desc->desc_node, &td_chan->free_list);
  204. dma_descriptor_unmap(txd);
  205. /*
  206. * The API requires that no submissions are done from a
  207. * callback, so we don't need to drop the lock here
  208. */
  209. dmaengine_desc_callback_invoke(&cb, NULL);
  210. }
  211. static u32 __td_ier_mask(struct timb_dma *td)
  212. {
  213. int i;
  214. u32 ret = 0;
  215. for (i = 0; i < td->dma.chancnt; i++) {
  216. struct timb_dma_chan *td_chan = td->channels + i;
  217. if (td_chan->ongoing) {
  218. struct timb_dma_desc *td_desc =
  219. list_entry(td_chan->active_list.next,
  220. struct timb_dma_desc, desc_node);
  221. if (td_desc->interrupt)
  222. ret |= 1 << i;
  223. }
  224. }
  225. return ret;
  226. }
  227. static void __td_start_next(struct timb_dma_chan *td_chan)
  228. {
  229. struct timb_dma_desc *td_desc;
  230. BUG_ON(list_empty(&td_chan->queue));
  231. BUG_ON(td_chan->ongoing);
  232. td_desc = list_entry(td_chan->queue.next, struct timb_dma_desc,
  233. desc_node);
  234. dev_dbg(chan2dev(&td_chan->chan), "%s: started %u\n",
  235. __func__, td_desc->txd.cookie);
  236. list_move(&td_desc->desc_node, &td_chan->active_list);
  237. __td_start_dma(td_chan);
  238. }
  239. static dma_cookie_t td_tx_submit(struct dma_async_tx_descriptor *txd)
  240. {
  241. struct timb_dma_desc *td_desc = container_of(txd, struct timb_dma_desc,
  242. txd);
  243. struct timb_dma_chan *td_chan = container_of(txd->chan,
  244. struct timb_dma_chan, chan);
  245. dma_cookie_t cookie;
  246. spin_lock_bh(&td_chan->lock);
  247. cookie = dma_cookie_assign(txd);
  248. if (list_empty(&td_chan->active_list)) {
  249. dev_dbg(chan2dev(txd->chan), "%s: started %u\n", __func__,
  250. txd->cookie);
  251. list_add_tail(&td_desc->desc_node, &td_chan->active_list);
  252. __td_start_dma(td_chan);
  253. } else {
  254. dev_dbg(chan2dev(txd->chan), "tx_submit: queued %u\n",
  255. txd->cookie);
  256. list_add_tail(&td_desc->desc_node, &td_chan->queue);
  257. }
  258. spin_unlock_bh(&td_chan->lock);
  259. return cookie;
  260. }
  261. static struct timb_dma_desc *td_alloc_init_desc(struct timb_dma_chan *td_chan)
  262. {
  263. struct dma_chan *chan = &td_chan->chan;
  264. struct timb_dma_desc *td_desc;
  265. int err;
  266. td_desc = kzalloc(sizeof(struct timb_dma_desc), GFP_KERNEL);
  267. if (!td_desc)
  268. goto out;
  269. td_desc->desc_list_len = td_chan->desc_elems * TIMB_DMA_DESC_SIZE;
  270. td_desc->desc_list = kzalloc(td_desc->desc_list_len, GFP_KERNEL);
  271. if (!td_desc->desc_list)
  272. goto err;
  273. dma_async_tx_descriptor_init(&td_desc->txd, chan);
  274. td_desc->txd.tx_submit = td_tx_submit;
  275. td_desc->txd.flags = DMA_CTRL_ACK;
  276. td_desc->txd.phys = dma_map_single(chan2dmadev(chan),
  277. td_desc->desc_list, td_desc->desc_list_len, DMA_TO_DEVICE);
  278. err = dma_mapping_error(chan2dmadev(chan), td_desc->txd.phys);
  279. if (err) {
  280. dev_err(chan2dev(chan), "DMA mapping error: %d\n", err);
  281. goto err;
  282. }
  283. return td_desc;
  284. err:
  285. kfree(td_desc->desc_list);
  286. kfree(td_desc);
  287. out:
  288. return NULL;
  289. }
  290. static void td_free_desc(struct timb_dma_desc *td_desc)
  291. {
  292. dev_dbg(chan2dev(td_desc->txd.chan), "Freeing desc: %p\n", td_desc);
  293. dma_unmap_single(chan2dmadev(td_desc->txd.chan), td_desc->txd.phys,
  294. td_desc->desc_list_len, DMA_TO_DEVICE);
  295. kfree(td_desc->desc_list);
  296. kfree(td_desc);
  297. }
  298. static void td_desc_put(struct timb_dma_chan *td_chan,
  299. struct timb_dma_desc *td_desc)
  300. {
  301. dev_dbg(chan2dev(&td_chan->chan), "Putting desc: %p\n", td_desc);
  302. spin_lock_bh(&td_chan->lock);
  303. list_add(&td_desc->desc_node, &td_chan->free_list);
  304. spin_unlock_bh(&td_chan->lock);
  305. }
  306. static struct timb_dma_desc *td_desc_get(struct timb_dma_chan *td_chan)
  307. {
  308. struct timb_dma_desc *td_desc, *_td_desc;
  309. struct timb_dma_desc *ret = NULL;
  310. spin_lock_bh(&td_chan->lock);
  311. list_for_each_entry_safe(td_desc, _td_desc, &td_chan->free_list,
  312. desc_node) {
  313. if (async_tx_test_ack(&td_desc->txd)) {
  314. list_del(&td_desc->desc_node);
  315. ret = td_desc;
  316. break;
  317. }
  318. dev_dbg(chan2dev(&td_chan->chan), "desc %p not ACKed\n",
  319. td_desc);
  320. }
  321. spin_unlock_bh(&td_chan->lock);
  322. return ret;
  323. }
  324. static int td_alloc_chan_resources(struct dma_chan *chan)
  325. {
  326. struct timb_dma_chan *td_chan =
  327. container_of(chan, struct timb_dma_chan, chan);
  328. int i;
  329. dev_dbg(chan2dev(chan), "%s: entry\n", __func__);
  330. BUG_ON(!list_empty(&td_chan->free_list));
  331. for (i = 0; i < td_chan->descs; i++) {
  332. struct timb_dma_desc *td_desc = td_alloc_init_desc(td_chan);
  333. if (!td_desc) {
  334. if (i)
  335. break;
  336. else {
  337. dev_err(chan2dev(chan),
  338. "Couldn't allocate any descriptors\n");
  339. return -ENOMEM;
  340. }
  341. }
  342. td_desc_put(td_chan, td_desc);
  343. }
  344. spin_lock_bh(&td_chan->lock);
  345. dma_cookie_init(chan);
  346. spin_unlock_bh(&td_chan->lock);
  347. return 0;
  348. }
  349. static void td_free_chan_resources(struct dma_chan *chan)
  350. {
  351. struct timb_dma_chan *td_chan =
  352. container_of(chan, struct timb_dma_chan, chan);
  353. struct timb_dma_desc *td_desc, *_td_desc;
  354. LIST_HEAD(list);
  355. dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
  356. /* check that all descriptors are free */
  357. BUG_ON(!list_empty(&td_chan->active_list));
  358. BUG_ON(!list_empty(&td_chan->queue));
  359. spin_lock_bh(&td_chan->lock);
  360. list_splice_init(&td_chan->free_list, &list);
  361. spin_unlock_bh(&td_chan->lock);
  362. list_for_each_entry_safe(td_desc, _td_desc, &list, desc_node) {
  363. dev_dbg(chan2dev(chan), "%s: Freeing desc: %p\n", __func__,
  364. td_desc);
  365. td_free_desc(td_desc);
  366. }
  367. }
  368. static enum dma_status td_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
  369. struct dma_tx_state *txstate)
  370. {
  371. enum dma_status ret;
  372. dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
  373. ret = dma_cookie_status(chan, cookie, txstate);
  374. dev_dbg(chan2dev(chan), "%s: exit, ret: %d\n", __func__, ret);
  375. return ret;
  376. }
  377. static void td_issue_pending(struct dma_chan *chan)
  378. {
  379. struct timb_dma_chan *td_chan =
  380. container_of(chan, struct timb_dma_chan, chan);
  381. dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
  382. spin_lock_bh(&td_chan->lock);
  383. if (!list_empty(&td_chan->active_list))
  384. /* transfer ongoing */
  385. if (__td_dma_done_ack(td_chan))
  386. __td_finish(td_chan);
  387. if (list_empty(&td_chan->active_list) && !list_empty(&td_chan->queue))
  388. __td_start_next(td_chan);
  389. spin_unlock_bh(&td_chan->lock);
  390. }
  391. static struct dma_async_tx_descriptor *td_prep_slave_sg(struct dma_chan *chan,
  392. struct scatterlist *sgl, unsigned int sg_len,
  393. enum dma_transfer_direction direction, unsigned long flags,
  394. void *context)
  395. {
  396. struct timb_dma_chan *td_chan =
  397. container_of(chan, struct timb_dma_chan, chan);
  398. struct timb_dma_desc *td_desc;
  399. struct scatterlist *sg;
  400. unsigned int i;
  401. unsigned int desc_usage = 0;
  402. if (!sgl || !sg_len) {
  403. dev_err(chan2dev(chan), "%s: No SG list\n", __func__);
  404. return NULL;
  405. }
  406. /* even channels are for RX, odd for TX */
  407. if (td_chan->direction != direction) {
  408. dev_err(chan2dev(chan),
  409. "Requesting channel in wrong direction\n");
  410. return NULL;
  411. }
  412. td_desc = td_desc_get(td_chan);
  413. if (!td_desc) {
  414. dev_err(chan2dev(chan), "Not enough descriptors available\n");
  415. return NULL;
  416. }
  417. td_desc->interrupt = (flags & DMA_PREP_INTERRUPT) != 0;
  418. for_each_sg(sgl, sg, sg_len, i) {
  419. int err;
  420. if (desc_usage > td_desc->desc_list_len) {
  421. dev_err(chan2dev(chan), "No descriptor space\n");
  422. return NULL;
  423. }
  424. err = td_fill_desc(td_chan, td_desc->desc_list + desc_usage, sg,
  425. i == (sg_len - 1));
  426. if (err) {
  427. dev_err(chan2dev(chan), "Failed to update desc: %d\n",
  428. err);
  429. td_desc_put(td_chan, td_desc);
  430. return NULL;
  431. }
  432. desc_usage += TIMB_DMA_DESC_SIZE;
  433. }
  434. dma_sync_single_for_device(chan2dmadev(chan), td_desc->txd.phys,
  435. td_desc->desc_list_len, DMA_TO_DEVICE);
  436. return &td_desc->txd;
  437. }
  438. static int td_terminate_all(struct dma_chan *chan)
  439. {
  440. struct timb_dma_chan *td_chan =
  441. container_of(chan, struct timb_dma_chan, chan);
  442. struct timb_dma_desc *td_desc, *_td_desc;
  443. dev_dbg(chan2dev(chan), "%s: Entry\n", __func__);
  444. /* first the easy part, put the queue into the free list */
  445. spin_lock_bh(&td_chan->lock);
  446. list_for_each_entry_safe(td_desc, _td_desc, &td_chan->queue,
  447. desc_node)
  448. list_move(&td_desc->desc_node, &td_chan->free_list);
  449. /* now tear down the running */
  450. __td_finish(td_chan);
  451. spin_unlock_bh(&td_chan->lock);
  452. return 0;
  453. }
  454. static void td_tasklet(struct tasklet_struct *t)
  455. {
  456. struct timb_dma *td = from_tasklet(td, t, tasklet);
  457. u32 isr;
  458. u32 ipr;
  459. u32 ier;
  460. int i;
  461. isr = ioread32(td->membase + TIMBDMA_ISR);
  462. ipr = isr & __td_ier_mask(td);
  463. /* ack the interrupts */
  464. iowrite32(ipr, td->membase + TIMBDMA_ISR);
  465. for (i = 0; i < td->dma.chancnt; i++)
  466. if (ipr & (1 << i)) {
  467. struct timb_dma_chan *td_chan = td->channels + i;
  468. spin_lock(&td_chan->lock);
  469. __td_finish(td_chan);
  470. if (!list_empty(&td_chan->queue))
  471. __td_start_next(td_chan);
  472. spin_unlock(&td_chan->lock);
  473. }
  474. ier = __td_ier_mask(td);
  475. iowrite32(ier, td->membase + TIMBDMA_IER);
  476. }
  477. static irqreturn_t td_irq(int irq, void *devid)
  478. {
  479. struct timb_dma *td = devid;
  480. u32 ipr = ioread32(td->membase + TIMBDMA_IPR);
  481. if (ipr) {
  482. /* disable interrupts, will be re-enabled in tasklet */
  483. iowrite32(0, td->membase + TIMBDMA_IER);
  484. tasklet_schedule(&td->tasklet);
  485. return IRQ_HANDLED;
  486. } else
  487. return IRQ_NONE;
  488. }
  489. static int td_probe(struct platform_device *pdev)
  490. {
  491. struct timb_dma_platform_data *pdata = dev_get_platdata(&pdev->dev);
  492. struct timb_dma *td;
  493. struct resource *iomem;
  494. int irq;
  495. int err;
  496. int i;
  497. if (!pdata) {
  498. dev_err(&pdev->dev, "No platform data\n");
  499. return -EINVAL;
  500. }
  501. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  502. if (!iomem)
  503. return -EINVAL;
  504. irq = platform_get_irq(pdev, 0);
  505. if (irq < 0)
  506. return irq;
  507. if (!request_mem_region(iomem->start, resource_size(iomem),
  508. DRIVER_NAME))
  509. return -EBUSY;
  510. td = kzalloc(struct_size(td, channels, pdata->nr_channels),
  511. GFP_KERNEL);
  512. if (!td) {
  513. err = -ENOMEM;
  514. goto err_release_region;
  515. }
  516. dev_dbg(&pdev->dev, "Allocated TD: %p\n", td);
  517. td->membase = ioremap(iomem->start, resource_size(iomem));
  518. if (!td->membase) {
  519. dev_err(&pdev->dev, "Failed to remap I/O memory\n");
  520. err = -ENOMEM;
  521. goto err_free_mem;
  522. }
  523. /* 32bit addressing */
  524. iowrite32(TIMBDMA_32BIT_ADDR, td->membase + TIMBDMA_ACR);
  525. /* disable and clear any interrupts */
  526. iowrite32(0x0, td->membase + TIMBDMA_IER);
  527. iowrite32(0xFFFFFFFF, td->membase + TIMBDMA_ISR);
  528. tasklet_setup(&td->tasklet, td_tasklet);
  529. err = request_irq(irq, td_irq, IRQF_SHARED, DRIVER_NAME, td);
  530. if (err) {
  531. dev_err(&pdev->dev, "Failed to request IRQ\n");
  532. goto err_tasklet_kill;
  533. }
  534. td->dma.device_alloc_chan_resources = td_alloc_chan_resources;
  535. td->dma.device_free_chan_resources = td_free_chan_resources;
  536. td->dma.device_tx_status = td_tx_status;
  537. td->dma.device_issue_pending = td_issue_pending;
  538. dma_cap_set(DMA_SLAVE, td->dma.cap_mask);
  539. dma_cap_set(DMA_PRIVATE, td->dma.cap_mask);
  540. td->dma.device_prep_slave_sg = td_prep_slave_sg;
  541. td->dma.device_terminate_all = td_terminate_all;
  542. td->dma.dev = &pdev->dev;
  543. INIT_LIST_HEAD(&td->dma.channels);
  544. for (i = 0; i < pdata->nr_channels; i++) {
  545. struct timb_dma_chan *td_chan = &td->channels[i];
  546. struct timb_dma_platform_data_channel *pchan =
  547. pdata->channels + i;
  548. /* even channels are RX, odd are TX */
  549. if ((i % 2) == pchan->rx) {
  550. dev_err(&pdev->dev, "Wrong channel configuration\n");
  551. err = -EINVAL;
  552. goto err_free_irq;
  553. }
  554. td_chan->chan.device = &td->dma;
  555. dma_cookie_init(&td_chan->chan);
  556. spin_lock_init(&td_chan->lock);
  557. INIT_LIST_HEAD(&td_chan->active_list);
  558. INIT_LIST_HEAD(&td_chan->queue);
  559. INIT_LIST_HEAD(&td_chan->free_list);
  560. td_chan->descs = pchan->descriptors;
  561. td_chan->desc_elems = pchan->descriptor_elements;
  562. td_chan->bytes_per_line = pchan->bytes_per_line;
  563. td_chan->direction = pchan->rx ? DMA_DEV_TO_MEM :
  564. DMA_MEM_TO_DEV;
  565. td_chan->membase = td->membase +
  566. (i / 2) * TIMBDMA_INSTANCE_OFFSET +
  567. (pchan->rx ? 0 : TIMBDMA_INSTANCE_TX_OFFSET);
  568. dev_dbg(&pdev->dev, "Chan: %d, membase: %p\n",
  569. i, td_chan->membase);
  570. list_add_tail(&td_chan->chan.device_node, &td->dma.channels);
  571. }
  572. err = dma_async_device_register(&td->dma);
  573. if (err) {
  574. dev_err(&pdev->dev, "Failed to register async device\n");
  575. goto err_free_irq;
  576. }
  577. platform_set_drvdata(pdev, td);
  578. dev_dbg(&pdev->dev, "Probe result: %d\n", err);
  579. return err;
  580. err_free_irq:
  581. free_irq(irq, td);
  582. err_tasklet_kill:
  583. tasklet_kill(&td->tasklet);
  584. iounmap(td->membase);
  585. err_free_mem:
  586. kfree(td);
  587. err_release_region:
  588. release_mem_region(iomem->start, resource_size(iomem));
  589. return err;
  590. }
  591. static int td_remove(struct platform_device *pdev)
  592. {
  593. struct timb_dma *td = platform_get_drvdata(pdev);
  594. struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  595. int irq = platform_get_irq(pdev, 0);
  596. dma_async_device_unregister(&td->dma);
  597. free_irq(irq, td);
  598. tasklet_kill(&td->tasklet);
  599. iounmap(td->membase);
  600. kfree(td);
  601. release_mem_region(iomem->start, resource_size(iomem));
  602. dev_dbg(&pdev->dev, "Removed...\n");
  603. return 0;
  604. }
  605. static struct platform_driver td_driver = {
  606. .driver = {
  607. .name = DRIVER_NAME,
  608. },
  609. .probe = td_probe,
  610. .remove = td_remove,
  611. };
  612. module_platform_driver(td_driver);
  613. MODULE_LICENSE("GPL v2");
  614. MODULE_DESCRIPTION("Timberdale DMA controller driver");
  615. MODULE_AUTHOR("Pelagicore AB <info@pelagicore.com>");
  616. MODULE_ALIAS("platform:"DRIVER_NAME);