k3-psil-j721e.c 5.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
  4. * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  5. */
  6. #include <linux/kernel.h>
  7. #include "k3-psil-priv.h"
  8. #define PSIL_PDMA_XY_TR(x) \
  9. { \
  10. .thread_id = x, \
  11. .ep_config = { \
  12. .ep_type = PSIL_EP_PDMA_XY, \
  13. }, \
  14. }
  15. #define PSIL_PDMA_XY_PKT(x) \
  16. { \
  17. .thread_id = x, \
  18. .ep_config = { \
  19. .ep_type = PSIL_EP_PDMA_XY, \
  20. .pkt_mode = 1, \
  21. }, \
  22. }
  23. #define PSIL_PDMA_MCASP(x) \
  24. { \
  25. .thread_id = x, \
  26. .ep_config = { \
  27. .ep_type = PSIL_EP_PDMA_XY, \
  28. .pdma_acc32 = 1, \
  29. .pdma_burst = 1, \
  30. }, \
  31. }
  32. #define PSIL_ETHERNET(x) \
  33. { \
  34. .thread_id = x, \
  35. .ep_config = { \
  36. .ep_type = PSIL_EP_NATIVE, \
  37. .pkt_mode = 1, \
  38. .needs_epib = 1, \
  39. .psd_size = 16, \
  40. }, \
  41. }
  42. #define PSIL_SA2UL(x, tx) \
  43. { \
  44. .thread_id = x, \
  45. .ep_config = { \
  46. .ep_type = PSIL_EP_NATIVE, \
  47. .pkt_mode = 1, \
  48. .needs_epib = 1, \
  49. .psd_size = 64, \
  50. .notdpkt = tx, \
  51. }, \
  52. }
  53. /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
  54. static struct psil_ep j721e_src_ep_map[] = {
  55. /* SA2UL */
  56. PSIL_SA2UL(0x4000, 0),
  57. PSIL_SA2UL(0x4001, 0),
  58. PSIL_SA2UL(0x4002, 0),
  59. PSIL_SA2UL(0x4003, 0),
  60. /* PRU_ICSSG0 */
  61. PSIL_ETHERNET(0x4100),
  62. PSIL_ETHERNET(0x4101),
  63. PSIL_ETHERNET(0x4102),
  64. PSIL_ETHERNET(0x4103),
  65. /* PRU_ICSSG1 */
  66. PSIL_ETHERNET(0x4200),
  67. PSIL_ETHERNET(0x4201),
  68. PSIL_ETHERNET(0x4202),
  69. PSIL_ETHERNET(0x4203),
  70. /* PDMA6 (PSIL_PDMA_MCASP_G0) - McASP0-2 */
  71. PSIL_PDMA_MCASP(0x4400),
  72. PSIL_PDMA_MCASP(0x4401),
  73. PSIL_PDMA_MCASP(0x4402),
  74. /* PDMA7 (PSIL_PDMA_MCASP_G1) - McASP3-11 */
  75. PSIL_PDMA_MCASP(0x4500),
  76. PSIL_PDMA_MCASP(0x4501),
  77. PSIL_PDMA_MCASP(0x4502),
  78. PSIL_PDMA_MCASP(0x4503),
  79. PSIL_PDMA_MCASP(0x4504),
  80. PSIL_PDMA_MCASP(0x4505),
  81. PSIL_PDMA_MCASP(0x4506),
  82. PSIL_PDMA_MCASP(0x4507),
  83. PSIL_PDMA_MCASP(0x4508),
  84. /* PDMA8 (PDMA_MISC_G0) - SPI0-1 */
  85. PSIL_PDMA_XY_PKT(0x4600),
  86. PSIL_PDMA_XY_PKT(0x4601),
  87. PSIL_PDMA_XY_PKT(0x4602),
  88. PSIL_PDMA_XY_PKT(0x4603),
  89. PSIL_PDMA_XY_PKT(0x4604),
  90. PSIL_PDMA_XY_PKT(0x4605),
  91. PSIL_PDMA_XY_PKT(0x4606),
  92. PSIL_PDMA_XY_PKT(0x4607),
  93. /* PDMA9 (PDMA_MISC_G1) - SPI2-3 */
  94. PSIL_PDMA_XY_PKT(0x460c),
  95. PSIL_PDMA_XY_PKT(0x460d),
  96. PSIL_PDMA_XY_PKT(0x460e),
  97. PSIL_PDMA_XY_PKT(0x460f),
  98. PSIL_PDMA_XY_PKT(0x4610),
  99. PSIL_PDMA_XY_PKT(0x4611),
  100. PSIL_PDMA_XY_PKT(0x4612),
  101. PSIL_PDMA_XY_PKT(0x4613),
  102. /* PDMA10 (PDMA_MISC_G2) - SPI4-5 */
  103. PSIL_PDMA_XY_PKT(0x4618),
  104. PSIL_PDMA_XY_PKT(0x4619),
  105. PSIL_PDMA_XY_PKT(0x461a),
  106. PSIL_PDMA_XY_PKT(0x461b),
  107. PSIL_PDMA_XY_PKT(0x461c),
  108. PSIL_PDMA_XY_PKT(0x461d),
  109. PSIL_PDMA_XY_PKT(0x461e),
  110. PSIL_PDMA_XY_PKT(0x461f),
  111. /* PDMA11 (PDMA_MISC_G3) */
  112. PSIL_PDMA_XY_PKT(0x4624),
  113. PSIL_PDMA_XY_PKT(0x4625),
  114. PSIL_PDMA_XY_PKT(0x4626),
  115. PSIL_PDMA_XY_PKT(0x4627),
  116. PSIL_PDMA_XY_PKT(0x4628),
  117. PSIL_PDMA_XY_PKT(0x4629),
  118. PSIL_PDMA_XY_PKT(0x4630),
  119. PSIL_PDMA_XY_PKT(0x463a),
  120. /* PDMA13 (PDMA_USART_G0) - UART0-1 */
  121. PSIL_PDMA_XY_PKT(0x4700),
  122. PSIL_PDMA_XY_PKT(0x4701),
  123. /* PDMA14 (PDMA_USART_G1) - UART2-3 */
  124. PSIL_PDMA_XY_PKT(0x4702),
  125. PSIL_PDMA_XY_PKT(0x4703),
  126. /* PDMA15 (PDMA_USART_G2) - UART4-9 */
  127. PSIL_PDMA_XY_PKT(0x4704),
  128. PSIL_PDMA_XY_PKT(0x4705),
  129. PSIL_PDMA_XY_PKT(0x4706),
  130. PSIL_PDMA_XY_PKT(0x4707),
  131. PSIL_PDMA_XY_PKT(0x4708),
  132. PSIL_PDMA_XY_PKT(0x4709),
  133. /* CPSW9 */
  134. PSIL_ETHERNET(0x4a00),
  135. /* CPSW0 */
  136. PSIL_ETHERNET(0x7000),
  137. /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */
  138. PSIL_PDMA_XY_PKT(0x7100),
  139. PSIL_PDMA_XY_PKT(0x7101),
  140. PSIL_PDMA_XY_PKT(0x7102),
  141. PSIL_PDMA_XY_PKT(0x7103),
  142. /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */
  143. PSIL_PDMA_XY_PKT(0x7200),
  144. PSIL_PDMA_XY_PKT(0x7201),
  145. PSIL_PDMA_XY_PKT(0x7202),
  146. PSIL_PDMA_XY_PKT(0x7203),
  147. PSIL_PDMA_XY_PKT(0x7204),
  148. PSIL_PDMA_XY_PKT(0x7205),
  149. PSIL_PDMA_XY_PKT(0x7206),
  150. PSIL_PDMA_XY_PKT(0x7207),
  151. /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */
  152. PSIL_PDMA_XY_PKT(0x7300),
  153. /* MCU_PDMA_ADC - ADC0-1 */
  154. PSIL_PDMA_XY_TR(0x7400),
  155. PSIL_PDMA_XY_TR(0x7401),
  156. PSIL_PDMA_XY_TR(0x7402),
  157. PSIL_PDMA_XY_TR(0x7403),
  158. /* SA2UL */
  159. PSIL_SA2UL(0x7500, 0),
  160. PSIL_SA2UL(0x7501, 0),
  161. PSIL_SA2UL(0x7502, 0),
  162. PSIL_SA2UL(0x7503, 0),
  163. };
  164. /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
  165. static struct psil_ep j721e_dst_ep_map[] = {
  166. /* SA2UL */
  167. PSIL_SA2UL(0xc000, 1),
  168. PSIL_SA2UL(0xc001, 1),
  169. /* PRU_ICSSG0 */
  170. PSIL_ETHERNET(0xc100),
  171. PSIL_ETHERNET(0xc101),
  172. PSIL_ETHERNET(0xc102),
  173. PSIL_ETHERNET(0xc103),
  174. PSIL_ETHERNET(0xc104),
  175. PSIL_ETHERNET(0xc105),
  176. PSIL_ETHERNET(0xc106),
  177. PSIL_ETHERNET(0xc107),
  178. /* PRU_ICSSG1 */
  179. PSIL_ETHERNET(0xc200),
  180. PSIL_ETHERNET(0xc201),
  181. PSIL_ETHERNET(0xc202),
  182. PSIL_ETHERNET(0xc203),
  183. PSIL_ETHERNET(0xc204),
  184. PSIL_ETHERNET(0xc205),
  185. PSIL_ETHERNET(0xc206),
  186. PSIL_ETHERNET(0xc207),
  187. /* CPSW9 */
  188. PSIL_ETHERNET(0xca00),
  189. PSIL_ETHERNET(0xca01),
  190. PSIL_ETHERNET(0xca02),
  191. PSIL_ETHERNET(0xca03),
  192. PSIL_ETHERNET(0xca04),
  193. PSIL_ETHERNET(0xca05),
  194. PSIL_ETHERNET(0xca06),
  195. PSIL_ETHERNET(0xca07),
  196. /* CPSW0 */
  197. PSIL_ETHERNET(0xf000),
  198. PSIL_ETHERNET(0xf001),
  199. PSIL_ETHERNET(0xf002),
  200. PSIL_ETHERNET(0xf003),
  201. PSIL_ETHERNET(0xf004),
  202. PSIL_ETHERNET(0xf005),
  203. PSIL_ETHERNET(0xf006),
  204. PSIL_ETHERNET(0xf007),
  205. /* SA2UL */
  206. PSIL_SA2UL(0xf500, 1),
  207. PSIL_SA2UL(0xf501, 1),
  208. };
  209. struct psil_ep_map j721e_ep_map = {
  210. .name = "j721e",
  211. .src = j721e_src_ep_map,
  212. .src_count = ARRAY_SIZE(j721e_src_ep_map),
  213. .dst = j721e_dst_ep_map,
  214. .dst_count = ARRAY_SIZE(j721e_dst_ep_map),
  215. };