k3-psil-j7200.c 4.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
  4. * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
  5. */
  6. #include <linux/kernel.h>
  7. #include "k3-psil-priv.h"
  8. #define PSIL_PDMA_XY_TR(x) \
  9. { \
  10. .thread_id = x, \
  11. .ep_config = { \
  12. .ep_type = PSIL_EP_PDMA_XY, \
  13. }, \
  14. }
  15. #define PSIL_PDMA_XY_PKT(x) \
  16. { \
  17. .thread_id = x, \
  18. .ep_config = { \
  19. .ep_type = PSIL_EP_PDMA_XY, \
  20. .pkt_mode = 1, \
  21. }, \
  22. }
  23. #define PSIL_PDMA_MCASP(x) \
  24. { \
  25. .thread_id = x, \
  26. .ep_config = { \
  27. .ep_type = PSIL_EP_PDMA_XY, \
  28. .pdma_acc32 = 1, \
  29. .pdma_burst = 1, \
  30. }, \
  31. }
  32. #define PSIL_ETHERNET(x) \
  33. { \
  34. .thread_id = x, \
  35. .ep_config = { \
  36. .ep_type = PSIL_EP_NATIVE, \
  37. .pkt_mode = 1, \
  38. .needs_epib = 1, \
  39. .psd_size = 16, \
  40. }, \
  41. }
  42. #define PSIL_SA2UL(x, tx) \
  43. { \
  44. .thread_id = x, \
  45. .ep_config = { \
  46. .ep_type = PSIL_EP_NATIVE, \
  47. .pkt_mode = 1, \
  48. .needs_epib = 1, \
  49. .psd_size = 64, \
  50. .notdpkt = tx, \
  51. }, \
  52. }
  53. /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
  54. static struct psil_ep j7200_src_ep_map[] = {
  55. /* PDMA_MCASP - McASP0-2 */
  56. PSIL_PDMA_MCASP(0x4400),
  57. PSIL_PDMA_MCASP(0x4401),
  58. PSIL_PDMA_MCASP(0x4402),
  59. /* PDMA_SPI_G0 - SPI0-3 */
  60. PSIL_PDMA_XY_PKT(0x4600),
  61. PSIL_PDMA_XY_PKT(0x4601),
  62. PSIL_PDMA_XY_PKT(0x4602),
  63. PSIL_PDMA_XY_PKT(0x4603),
  64. PSIL_PDMA_XY_PKT(0x4604),
  65. PSIL_PDMA_XY_PKT(0x4605),
  66. PSIL_PDMA_XY_PKT(0x4606),
  67. PSIL_PDMA_XY_PKT(0x4607),
  68. PSIL_PDMA_XY_PKT(0x4608),
  69. PSIL_PDMA_XY_PKT(0x4609),
  70. PSIL_PDMA_XY_PKT(0x460a),
  71. PSIL_PDMA_XY_PKT(0x460b),
  72. PSIL_PDMA_XY_PKT(0x460c),
  73. PSIL_PDMA_XY_PKT(0x460d),
  74. PSIL_PDMA_XY_PKT(0x460e),
  75. PSIL_PDMA_XY_PKT(0x460f),
  76. /* PDMA_SPI_G1 - SPI4-7 */
  77. PSIL_PDMA_XY_PKT(0x4610),
  78. PSIL_PDMA_XY_PKT(0x4611),
  79. PSIL_PDMA_XY_PKT(0x4612),
  80. PSIL_PDMA_XY_PKT(0x4613),
  81. PSIL_PDMA_XY_PKT(0x4614),
  82. PSIL_PDMA_XY_PKT(0x4615),
  83. PSIL_PDMA_XY_PKT(0x4616),
  84. PSIL_PDMA_XY_PKT(0x4617),
  85. PSIL_PDMA_XY_PKT(0x4618),
  86. PSIL_PDMA_XY_PKT(0x4619),
  87. PSIL_PDMA_XY_PKT(0x461a),
  88. PSIL_PDMA_XY_PKT(0x461b),
  89. PSIL_PDMA_XY_PKT(0x461c),
  90. PSIL_PDMA_XY_PKT(0x461d),
  91. PSIL_PDMA_XY_PKT(0x461e),
  92. PSIL_PDMA_XY_PKT(0x461f),
  93. /* PDMA_USART_G0 - UART0-1 */
  94. PSIL_PDMA_XY_PKT(0x4700),
  95. PSIL_PDMA_XY_PKT(0x4701),
  96. /* PDMA_USART_G1 - UART2-3 */
  97. PSIL_PDMA_XY_PKT(0x4702),
  98. PSIL_PDMA_XY_PKT(0x4703),
  99. /* PDMA_USART_G2 - UART4-9 */
  100. PSIL_PDMA_XY_PKT(0x4704),
  101. PSIL_PDMA_XY_PKT(0x4705),
  102. PSIL_PDMA_XY_PKT(0x4706),
  103. PSIL_PDMA_XY_PKT(0x4707),
  104. PSIL_PDMA_XY_PKT(0x4708),
  105. PSIL_PDMA_XY_PKT(0x4709),
  106. /* CPSW5 */
  107. PSIL_ETHERNET(0x4a00),
  108. /* CPSW0 */
  109. PSIL_ETHERNET(0x7000),
  110. /* MCU_PDMA_MISC_G0 - SPI0 */
  111. PSIL_PDMA_XY_PKT(0x7100),
  112. PSIL_PDMA_XY_PKT(0x7101),
  113. PSIL_PDMA_XY_PKT(0x7102),
  114. PSIL_PDMA_XY_PKT(0x7103),
  115. /* MCU_PDMA_MISC_G1 - SPI1-2 */
  116. PSIL_PDMA_XY_PKT(0x7200),
  117. PSIL_PDMA_XY_PKT(0x7201),
  118. PSIL_PDMA_XY_PKT(0x7202),
  119. PSIL_PDMA_XY_PKT(0x7203),
  120. PSIL_PDMA_XY_PKT(0x7204),
  121. PSIL_PDMA_XY_PKT(0x7205),
  122. PSIL_PDMA_XY_PKT(0x7206),
  123. PSIL_PDMA_XY_PKT(0x7207),
  124. /* MCU_PDMA_MISC_G2 - UART0 */
  125. PSIL_PDMA_XY_PKT(0x7300),
  126. /* MCU_PDMA_ADC - ADC0-1 */
  127. PSIL_PDMA_XY_TR(0x7400),
  128. PSIL_PDMA_XY_TR(0x7401),
  129. /* SA2UL */
  130. PSIL_SA2UL(0x7500, 0),
  131. PSIL_SA2UL(0x7501, 0),
  132. PSIL_SA2UL(0x7502, 0),
  133. PSIL_SA2UL(0x7503, 0),
  134. };
  135. /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
  136. static struct psil_ep j7200_dst_ep_map[] = {
  137. /* CPSW5 */
  138. PSIL_ETHERNET(0xca00),
  139. PSIL_ETHERNET(0xca01),
  140. PSIL_ETHERNET(0xca02),
  141. PSIL_ETHERNET(0xca03),
  142. PSIL_ETHERNET(0xca04),
  143. PSIL_ETHERNET(0xca05),
  144. PSIL_ETHERNET(0xca06),
  145. PSIL_ETHERNET(0xca07),
  146. /* CPSW0 */
  147. PSIL_ETHERNET(0xf000),
  148. PSIL_ETHERNET(0xf001),
  149. PSIL_ETHERNET(0xf002),
  150. PSIL_ETHERNET(0xf003),
  151. PSIL_ETHERNET(0xf004),
  152. PSIL_ETHERNET(0xf005),
  153. PSIL_ETHERNET(0xf006),
  154. PSIL_ETHERNET(0xf007),
  155. /* SA2UL */
  156. PSIL_SA2UL(0xf500, 1),
  157. PSIL_SA2UL(0xf501, 1),
  158. };
  159. struct psil_ep_map j7200_ep_map = {
  160. .name = "j7200",
  161. .src = j7200_src_ep_map,
  162. .src_count = ARRAY_SIZE(j7200_src_ep_map),
  163. .dst = j7200_dst_ep_map,
  164. .dst_count = ARRAY_SIZE(j7200_dst_ep_map),
  165. };