tegra20-apb-dma.c 45 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * DMA driver for Nvidia's Tegra20 APB DMA controller.
  4. *
  5. * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
  6. */
  7. #include <linux/bitops.h>
  8. #include <linux/clk.h>
  9. #include <linux/delay.h>
  10. #include <linux/dmaengine.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/err.h>
  13. #include <linux/init.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/io.h>
  16. #include <linux/mm.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_dma.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/pm.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/reset.h>
  25. #include <linux/slab.h>
  26. #include <linux/wait.h>
  27. #include "dmaengine.h"
  28. #define CREATE_TRACE_POINTS
  29. #include <trace/events/tegra_apb_dma.h>
  30. #define TEGRA_APBDMA_GENERAL 0x0
  31. #define TEGRA_APBDMA_GENERAL_ENABLE BIT(31)
  32. #define TEGRA_APBDMA_CONTROL 0x010
  33. #define TEGRA_APBDMA_IRQ_MASK 0x01c
  34. #define TEGRA_APBDMA_IRQ_MASK_SET 0x020
  35. /* CSR register */
  36. #define TEGRA_APBDMA_CHAN_CSR 0x00
  37. #define TEGRA_APBDMA_CSR_ENB BIT(31)
  38. #define TEGRA_APBDMA_CSR_IE_EOC BIT(30)
  39. #define TEGRA_APBDMA_CSR_HOLD BIT(29)
  40. #define TEGRA_APBDMA_CSR_DIR BIT(28)
  41. #define TEGRA_APBDMA_CSR_ONCE BIT(27)
  42. #define TEGRA_APBDMA_CSR_FLOW BIT(21)
  43. #define TEGRA_APBDMA_CSR_REQ_SEL_SHIFT 16
  44. #define TEGRA_APBDMA_CSR_REQ_SEL_MASK 0x1F
  45. #define TEGRA_APBDMA_CSR_WCOUNT_MASK 0xFFFC
  46. /* STATUS register */
  47. #define TEGRA_APBDMA_CHAN_STATUS 0x004
  48. #define TEGRA_APBDMA_STATUS_BUSY BIT(31)
  49. #define TEGRA_APBDMA_STATUS_ISE_EOC BIT(30)
  50. #define TEGRA_APBDMA_STATUS_HALT BIT(29)
  51. #define TEGRA_APBDMA_STATUS_PING_PONG BIT(28)
  52. #define TEGRA_APBDMA_STATUS_COUNT_SHIFT 2
  53. #define TEGRA_APBDMA_STATUS_COUNT_MASK 0xFFFC
  54. #define TEGRA_APBDMA_CHAN_CSRE 0x00C
  55. #define TEGRA_APBDMA_CHAN_CSRE_PAUSE BIT(31)
  56. /* AHB memory address */
  57. #define TEGRA_APBDMA_CHAN_AHBPTR 0x010
  58. /* AHB sequence register */
  59. #define TEGRA_APBDMA_CHAN_AHBSEQ 0x14
  60. #define TEGRA_APBDMA_AHBSEQ_INTR_ENB BIT(31)
  61. #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_8 (0 << 28)
  62. #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_16 (1 << 28)
  63. #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32 (2 << 28)
  64. #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_64 (3 << 28)
  65. #define TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_128 (4 << 28)
  66. #define TEGRA_APBDMA_AHBSEQ_DATA_SWAP BIT(27)
  67. #define TEGRA_APBDMA_AHBSEQ_BURST_1 (4 << 24)
  68. #define TEGRA_APBDMA_AHBSEQ_BURST_4 (5 << 24)
  69. #define TEGRA_APBDMA_AHBSEQ_BURST_8 (6 << 24)
  70. #define TEGRA_APBDMA_AHBSEQ_DBL_BUF BIT(19)
  71. #define TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT 16
  72. #define TEGRA_APBDMA_AHBSEQ_WRAP_NONE 0
  73. /* APB address */
  74. #define TEGRA_APBDMA_CHAN_APBPTR 0x018
  75. /* APB sequence register */
  76. #define TEGRA_APBDMA_CHAN_APBSEQ 0x01c
  77. #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8 (0 << 28)
  78. #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16 (1 << 28)
  79. #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32 (2 << 28)
  80. #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64 (3 << 28)
  81. #define TEGRA_APBDMA_APBSEQ_BUS_WIDTH_128 (4 << 28)
  82. #define TEGRA_APBDMA_APBSEQ_DATA_SWAP BIT(27)
  83. #define TEGRA_APBDMA_APBSEQ_WRAP_WORD_1 (1 << 16)
  84. /* Tegra148 specific registers */
  85. #define TEGRA_APBDMA_CHAN_WCOUNT 0x20
  86. #define TEGRA_APBDMA_CHAN_WORD_TRANSFER 0x24
  87. /*
  88. * If any burst is in flight and DMA paused then this is the time to complete
  89. * on-flight burst and update DMA status register.
  90. */
  91. #define TEGRA_APBDMA_BURST_COMPLETE_TIME 20
  92. /* Channel base address offset from APBDMA base address */
  93. #define TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET 0x1000
  94. #define TEGRA_APBDMA_SLAVE_ID_INVALID (TEGRA_APBDMA_CSR_REQ_SEL_MASK + 1)
  95. struct tegra_dma;
  96. /*
  97. * tegra_dma_chip_data Tegra chip specific DMA data
  98. * @nr_channels: Number of channels available in the controller.
  99. * @channel_reg_size: Channel register size/stride.
  100. * @max_dma_count: Maximum DMA transfer count supported by DMA controller.
  101. * @support_channel_pause: Support channel wise pause of dma.
  102. * @support_separate_wcount_reg: Support separate word count register.
  103. */
  104. struct tegra_dma_chip_data {
  105. unsigned int nr_channels;
  106. unsigned int channel_reg_size;
  107. unsigned int max_dma_count;
  108. bool support_channel_pause;
  109. bool support_separate_wcount_reg;
  110. };
  111. /* DMA channel registers */
  112. struct tegra_dma_channel_regs {
  113. u32 csr;
  114. u32 ahb_ptr;
  115. u32 apb_ptr;
  116. u32 ahb_seq;
  117. u32 apb_seq;
  118. u32 wcount;
  119. };
  120. /*
  121. * tegra_dma_sg_req: DMA request details to configure hardware. This
  122. * contains the details for one transfer to configure DMA hw.
  123. * The client's request for data transfer can be broken into multiple
  124. * sub-transfer as per requester details and hw support.
  125. * This sub transfer get added in the list of transfer and point to Tegra
  126. * DMA descriptor which manages the transfer details.
  127. */
  128. struct tegra_dma_sg_req {
  129. struct tegra_dma_channel_regs ch_regs;
  130. unsigned int req_len;
  131. bool configured;
  132. bool last_sg;
  133. struct list_head node;
  134. struct tegra_dma_desc *dma_desc;
  135. unsigned int words_xferred;
  136. };
  137. /*
  138. * tegra_dma_desc: Tegra DMA descriptors which manages the client requests.
  139. * This descriptor keep track of transfer status, callbacks and request
  140. * counts etc.
  141. */
  142. struct tegra_dma_desc {
  143. struct dma_async_tx_descriptor txd;
  144. unsigned int bytes_requested;
  145. unsigned int bytes_transferred;
  146. enum dma_status dma_status;
  147. struct list_head node;
  148. struct list_head tx_list;
  149. struct list_head cb_node;
  150. unsigned int cb_count;
  151. };
  152. struct tegra_dma_channel;
  153. typedef void (*dma_isr_handler)(struct tegra_dma_channel *tdc,
  154. bool to_terminate);
  155. /* tegra_dma_channel: Channel specific information */
  156. struct tegra_dma_channel {
  157. struct dma_chan dma_chan;
  158. char name[12];
  159. bool config_init;
  160. unsigned int id;
  161. void __iomem *chan_addr;
  162. spinlock_t lock;
  163. bool busy;
  164. struct tegra_dma *tdma;
  165. bool cyclic;
  166. /* Different lists for managing the requests */
  167. struct list_head free_sg_req;
  168. struct list_head pending_sg_req;
  169. struct list_head free_dma_desc;
  170. struct list_head cb_desc;
  171. /* ISR handler and tasklet for bottom half of isr handling */
  172. dma_isr_handler isr_handler;
  173. struct tasklet_struct tasklet;
  174. /* Channel-slave specific configuration */
  175. unsigned int slave_id;
  176. struct dma_slave_config dma_sconfig;
  177. struct tegra_dma_channel_regs channel_reg;
  178. struct wait_queue_head wq;
  179. };
  180. /* tegra_dma: Tegra DMA specific information */
  181. struct tegra_dma {
  182. struct dma_device dma_dev;
  183. struct device *dev;
  184. struct clk *dma_clk;
  185. struct reset_control *rst;
  186. spinlock_t global_lock;
  187. void __iomem *base_addr;
  188. const struct tegra_dma_chip_data *chip_data;
  189. /*
  190. * Counter for managing global pausing of the DMA controller.
  191. * Only applicable for devices that don't support individual
  192. * channel pausing.
  193. */
  194. u32 global_pause_count;
  195. /* Last member of the structure */
  196. struct tegra_dma_channel channels[];
  197. };
  198. static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)
  199. {
  200. writel(val, tdma->base_addr + reg);
  201. }
  202. static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)
  203. {
  204. return readl(tdma->base_addr + reg);
  205. }
  206. static inline void tdc_write(struct tegra_dma_channel *tdc,
  207. u32 reg, u32 val)
  208. {
  209. writel(val, tdc->chan_addr + reg);
  210. }
  211. static inline u32 tdc_read(struct tegra_dma_channel *tdc, u32 reg)
  212. {
  213. return readl(tdc->chan_addr + reg);
  214. }
  215. static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc)
  216. {
  217. return container_of(dc, struct tegra_dma_channel, dma_chan);
  218. }
  219. static inline struct tegra_dma_desc *
  220. txd_to_tegra_dma_desc(struct dma_async_tx_descriptor *td)
  221. {
  222. return container_of(td, struct tegra_dma_desc, txd);
  223. }
  224. static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)
  225. {
  226. return &tdc->dma_chan.dev->device;
  227. }
  228. static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *tx);
  229. /* Get DMA desc from free list, if not there then allocate it. */
  230. static struct tegra_dma_desc *tegra_dma_desc_get(struct tegra_dma_channel *tdc)
  231. {
  232. struct tegra_dma_desc *dma_desc;
  233. unsigned long flags;
  234. spin_lock_irqsave(&tdc->lock, flags);
  235. /* Do not allocate if desc are waiting for ack */
  236. list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
  237. if (async_tx_test_ack(&dma_desc->txd) && !dma_desc->cb_count) {
  238. list_del(&dma_desc->node);
  239. spin_unlock_irqrestore(&tdc->lock, flags);
  240. dma_desc->txd.flags = 0;
  241. return dma_desc;
  242. }
  243. }
  244. spin_unlock_irqrestore(&tdc->lock, flags);
  245. /* Allocate DMA desc */
  246. dma_desc = kzalloc(sizeof(*dma_desc), GFP_NOWAIT);
  247. if (!dma_desc)
  248. return NULL;
  249. dma_async_tx_descriptor_init(&dma_desc->txd, &tdc->dma_chan);
  250. dma_desc->txd.tx_submit = tegra_dma_tx_submit;
  251. dma_desc->txd.flags = 0;
  252. return dma_desc;
  253. }
  254. static void tegra_dma_desc_put(struct tegra_dma_channel *tdc,
  255. struct tegra_dma_desc *dma_desc)
  256. {
  257. unsigned long flags;
  258. spin_lock_irqsave(&tdc->lock, flags);
  259. if (!list_empty(&dma_desc->tx_list))
  260. list_splice_init(&dma_desc->tx_list, &tdc->free_sg_req);
  261. list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
  262. spin_unlock_irqrestore(&tdc->lock, flags);
  263. }
  264. static struct tegra_dma_sg_req *
  265. tegra_dma_sg_req_get(struct tegra_dma_channel *tdc)
  266. {
  267. struct tegra_dma_sg_req *sg_req;
  268. unsigned long flags;
  269. spin_lock_irqsave(&tdc->lock, flags);
  270. if (!list_empty(&tdc->free_sg_req)) {
  271. sg_req = list_first_entry(&tdc->free_sg_req, typeof(*sg_req),
  272. node);
  273. list_del(&sg_req->node);
  274. spin_unlock_irqrestore(&tdc->lock, flags);
  275. return sg_req;
  276. }
  277. spin_unlock_irqrestore(&tdc->lock, flags);
  278. sg_req = kzalloc(sizeof(*sg_req), GFP_NOWAIT);
  279. return sg_req;
  280. }
  281. static int tegra_dma_slave_config(struct dma_chan *dc,
  282. struct dma_slave_config *sconfig)
  283. {
  284. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  285. if (!list_empty(&tdc->pending_sg_req)) {
  286. dev_err(tdc2dev(tdc), "Configuration not allowed\n");
  287. return -EBUSY;
  288. }
  289. memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig));
  290. if (tdc->slave_id == TEGRA_APBDMA_SLAVE_ID_INVALID &&
  291. sconfig->device_fc) {
  292. if (sconfig->slave_id > TEGRA_APBDMA_CSR_REQ_SEL_MASK)
  293. return -EINVAL;
  294. tdc->slave_id = sconfig->slave_id;
  295. }
  296. tdc->config_init = true;
  297. return 0;
  298. }
  299. static void tegra_dma_global_pause(struct tegra_dma_channel *tdc,
  300. bool wait_for_burst_complete)
  301. {
  302. struct tegra_dma *tdma = tdc->tdma;
  303. spin_lock(&tdma->global_lock);
  304. if (tdc->tdma->global_pause_count == 0) {
  305. tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);
  306. if (wait_for_burst_complete)
  307. udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
  308. }
  309. tdc->tdma->global_pause_count++;
  310. spin_unlock(&tdma->global_lock);
  311. }
  312. static void tegra_dma_global_resume(struct tegra_dma_channel *tdc)
  313. {
  314. struct tegra_dma *tdma = tdc->tdma;
  315. spin_lock(&tdma->global_lock);
  316. if (WARN_ON(tdc->tdma->global_pause_count == 0))
  317. goto out;
  318. if (--tdc->tdma->global_pause_count == 0)
  319. tdma_write(tdma, TEGRA_APBDMA_GENERAL,
  320. TEGRA_APBDMA_GENERAL_ENABLE);
  321. out:
  322. spin_unlock(&tdma->global_lock);
  323. }
  324. static void tegra_dma_pause(struct tegra_dma_channel *tdc,
  325. bool wait_for_burst_complete)
  326. {
  327. struct tegra_dma *tdma = tdc->tdma;
  328. if (tdma->chip_data->support_channel_pause) {
  329. tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE,
  330. TEGRA_APBDMA_CHAN_CSRE_PAUSE);
  331. if (wait_for_burst_complete)
  332. udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
  333. } else {
  334. tegra_dma_global_pause(tdc, wait_for_burst_complete);
  335. }
  336. }
  337. static void tegra_dma_resume(struct tegra_dma_channel *tdc)
  338. {
  339. struct tegra_dma *tdma = tdc->tdma;
  340. if (tdma->chip_data->support_channel_pause)
  341. tdc_write(tdc, TEGRA_APBDMA_CHAN_CSRE, 0);
  342. else
  343. tegra_dma_global_resume(tdc);
  344. }
  345. static void tegra_dma_stop(struct tegra_dma_channel *tdc)
  346. {
  347. u32 csr, status;
  348. /* Disable interrupts */
  349. csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
  350. csr &= ~TEGRA_APBDMA_CSR_IE_EOC;
  351. tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
  352. /* Disable DMA */
  353. csr &= ~TEGRA_APBDMA_CSR_ENB;
  354. tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, csr);
  355. /* Clear interrupt status if it is there */
  356. status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
  357. if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
  358. dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__);
  359. tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
  360. }
  361. tdc->busy = false;
  362. }
  363. static void tegra_dma_start(struct tegra_dma_channel *tdc,
  364. struct tegra_dma_sg_req *sg_req)
  365. {
  366. struct tegra_dma_channel_regs *ch_regs = &sg_req->ch_regs;
  367. tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR, ch_regs->csr);
  368. tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_regs->apb_seq);
  369. tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_regs->apb_ptr);
  370. tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_regs->ahb_seq);
  371. tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_regs->ahb_ptr);
  372. if (tdc->tdma->chip_data->support_separate_wcount_reg)
  373. tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT, ch_regs->wcount);
  374. /* Start DMA */
  375. tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
  376. ch_regs->csr | TEGRA_APBDMA_CSR_ENB);
  377. }
  378. static void tegra_dma_configure_for_next(struct tegra_dma_channel *tdc,
  379. struct tegra_dma_sg_req *nsg_req)
  380. {
  381. unsigned long status;
  382. /*
  383. * The DMA controller reloads the new configuration for next transfer
  384. * after last burst of current transfer completes.
  385. * If there is no IEC status then this makes sure that last burst
  386. * has not be completed. There may be case that last burst is on
  387. * flight and so it can complete but because DMA is paused, it
  388. * will not generates interrupt as well as not reload the new
  389. * configuration.
  390. * If there is already IEC status then interrupt handler need to
  391. * load new configuration.
  392. */
  393. tegra_dma_pause(tdc, false);
  394. status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
  395. /*
  396. * If interrupt is pending then do nothing as the ISR will handle
  397. * the programing for new request.
  398. */
  399. if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
  400. dev_err(tdc2dev(tdc),
  401. "Skipping new configuration as interrupt is pending\n");
  402. tegra_dma_resume(tdc);
  403. return;
  404. }
  405. /* Safe to program new configuration */
  406. tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, nsg_req->ch_regs.apb_ptr);
  407. tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, nsg_req->ch_regs.ahb_ptr);
  408. if (tdc->tdma->chip_data->support_separate_wcount_reg)
  409. tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
  410. nsg_req->ch_regs.wcount);
  411. tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
  412. nsg_req->ch_regs.csr | TEGRA_APBDMA_CSR_ENB);
  413. nsg_req->configured = true;
  414. nsg_req->words_xferred = 0;
  415. tegra_dma_resume(tdc);
  416. }
  417. static void tdc_start_head_req(struct tegra_dma_channel *tdc)
  418. {
  419. struct tegra_dma_sg_req *sg_req;
  420. sg_req = list_first_entry(&tdc->pending_sg_req, typeof(*sg_req), node);
  421. tegra_dma_start(tdc, sg_req);
  422. sg_req->configured = true;
  423. sg_req->words_xferred = 0;
  424. tdc->busy = true;
  425. }
  426. static void tdc_configure_next_head_desc(struct tegra_dma_channel *tdc)
  427. {
  428. struct tegra_dma_sg_req *hsgreq, *hnsgreq;
  429. hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
  430. if (!list_is_last(&hsgreq->node, &tdc->pending_sg_req)) {
  431. hnsgreq = list_first_entry(&hsgreq->node, typeof(*hnsgreq),
  432. node);
  433. tegra_dma_configure_for_next(tdc, hnsgreq);
  434. }
  435. }
  436. static inline unsigned int
  437. get_current_xferred_count(struct tegra_dma_channel *tdc,
  438. struct tegra_dma_sg_req *sg_req,
  439. unsigned long status)
  440. {
  441. return sg_req->req_len - (status & TEGRA_APBDMA_STATUS_COUNT_MASK) - 4;
  442. }
  443. static void tegra_dma_abort_all(struct tegra_dma_channel *tdc)
  444. {
  445. struct tegra_dma_desc *dma_desc;
  446. struct tegra_dma_sg_req *sgreq;
  447. while (!list_empty(&tdc->pending_sg_req)) {
  448. sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq),
  449. node);
  450. list_move_tail(&sgreq->node, &tdc->free_sg_req);
  451. if (sgreq->last_sg) {
  452. dma_desc = sgreq->dma_desc;
  453. dma_desc->dma_status = DMA_ERROR;
  454. list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
  455. /* Add in cb list if it is not there. */
  456. if (!dma_desc->cb_count)
  457. list_add_tail(&dma_desc->cb_node,
  458. &tdc->cb_desc);
  459. dma_desc->cb_count++;
  460. }
  461. }
  462. tdc->isr_handler = NULL;
  463. }
  464. static bool handle_continuous_head_request(struct tegra_dma_channel *tdc,
  465. bool to_terminate)
  466. {
  467. struct tegra_dma_sg_req *hsgreq;
  468. /*
  469. * Check that head req on list should be in flight.
  470. * If it is not in flight then abort transfer as
  471. * looping of transfer can not continue.
  472. */
  473. hsgreq = list_first_entry(&tdc->pending_sg_req, typeof(*hsgreq), node);
  474. if (!hsgreq->configured) {
  475. tegra_dma_stop(tdc);
  476. pm_runtime_put(tdc->tdma->dev);
  477. dev_err(tdc2dev(tdc), "DMA transfer underflow, aborting DMA\n");
  478. tegra_dma_abort_all(tdc);
  479. return false;
  480. }
  481. /* Configure next request */
  482. if (!to_terminate)
  483. tdc_configure_next_head_desc(tdc);
  484. return true;
  485. }
  486. static void handle_once_dma_done(struct tegra_dma_channel *tdc,
  487. bool to_terminate)
  488. {
  489. struct tegra_dma_desc *dma_desc;
  490. struct tegra_dma_sg_req *sgreq;
  491. tdc->busy = false;
  492. sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
  493. dma_desc = sgreq->dma_desc;
  494. dma_desc->bytes_transferred += sgreq->req_len;
  495. list_del(&sgreq->node);
  496. if (sgreq->last_sg) {
  497. dma_desc->dma_status = DMA_COMPLETE;
  498. dma_cookie_complete(&dma_desc->txd);
  499. if (!dma_desc->cb_count)
  500. list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
  501. dma_desc->cb_count++;
  502. list_add_tail(&dma_desc->node, &tdc->free_dma_desc);
  503. }
  504. list_add_tail(&sgreq->node, &tdc->free_sg_req);
  505. /* Do not start DMA if it is going to be terminate */
  506. if (to_terminate)
  507. return;
  508. if (list_empty(&tdc->pending_sg_req)) {
  509. pm_runtime_put(tdc->tdma->dev);
  510. return;
  511. }
  512. tdc_start_head_req(tdc);
  513. }
  514. static void handle_cont_sngl_cycle_dma_done(struct tegra_dma_channel *tdc,
  515. bool to_terminate)
  516. {
  517. struct tegra_dma_desc *dma_desc;
  518. struct tegra_dma_sg_req *sgreq;
  519. bool st;
  520. sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq), node);
  521. dma_desc = sgreq->dma_desc;
  522. /* if we dma for long enough the transfer count will wrap */
  523. dma_desc->bytes_transferred =
  524. (dma_desc->bytes_transferred + sgreq->req_len) %
  525. dma_desc->bytes_requested;
  526. /* Callback need to be call */
  527. if (!dma_desc->cb_count)
  528. list_add_tail(&dma_desc->cb_node, &tdc->cb_desc);
  529. dma_desc->cb_count++;
  530. sgreq->words_xferred = 0;
  531. /* If not last req then put at end of pending list */
  532. if (!list_is_last(&sgreq->node, &tdc->pending_sg_req)) {
  533. list_move_tail(&sgreq->node, &tdc->pending_sg_req);
  534. sgreq->configured = false;
  535. st = handle_continuous_head_request(tdc, to_terminate);
  536. if (!st)
  537. dma_desc->dma_status = DMA_ERROR;
  538. }
  539. }
  540. static void tegra_dma_tasklet(struct tasklet_struct *t)
  541. {
  542. struct tegra_dma_channel *tdc = from_tasklet(tdc, t, tasklet);
  543. struct dmaengine_desc_callback cb;
  544. struct tegra_dma_desc *dma_desc;
  545. unsigned int cb_count;
  546. unsigned long flags;
  547. spin_lock_irqsave(&tdc->lock, flags);
  548. while (!list_empty(&tdc->cb_desc)) {
  549. dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc),
  550. cb_node);
  551. list_del(&dma_desc->cb_node);
  552. dmaengine_desc_get_callback(&dma_desc->txd, &cb);
  553. cb_count = dma_desc->cb_count;
  554. dma_desc->cb_count = 0;
  555. trace_tegra_dma_complete_cb(&tdc->dma_chan, cb_count,
  556. cb.callback);
  557. spin_unlock_irqrestore(&tdc->lock, flags);
  558. while (cb_count--)
  559. dmaengine_desc_callback_invoke(&cb, NULL);
  560. spin_lock_irqsave(&tdc->lock, flags);
  561. }
  562. spin_unlock_irqrestore(&tdc->lock, flags);
  563. }
  564. static irqreturn_t tegra_dma_isr(int irq, void *dev_id)
  565. {
  566. struct tegra_dma_channel *tdc = dev_id;
  567. u32 status;
  568. spin_lock(&tdc->lock);
  569. trace_tegra_dma_isr(&tdc->dma_chan, irq);
  570. status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
  571. if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
  572. tdc_write(tdc, TEGRA_APBDMA_CHAN_STATUS, status);
  573. tdc->isr_handler(tdc, false);
  574. tasklet_schedule(&tdc->tasklet);
  575. wake_up_all(&tdc->wq);
  576. spin_unlock(&tdc->lock);
  577. return IRQ_HANDLED;
  578. }
  579. spin_unlock(&tdc->lock);
  580. dev_info(tdc2dev(tdc), "Interrupt already served status 0x%08x\n",
  581. status);
  582. return IRQ_NONE;
  583. }
  584. static dma_cookie_t tegra_dma_tx_submit(struct dma_async_tx_descriptor *txd)
  585. {
  586. struct tegra_dma_desc *dma_desc = txd_to_tegra_dma_desc(txd);
  587. struct tegra_dma_channel *tdc = to_tegra_dma_chan(txd->chan);
  588. unsigned long flags;
  589. dma_cookie_t cookie;
  590. spin_lock_irqsave(&tdc->lock, flags);
  591. dma_desc->dma_status = DMA_IN_PROGRESS;
  592. cookie = dma_cookie_assign(&dma_desc->txd);
  593. list_splice_tail_init(&dma_desc->tx_list, &tdc->pending_sg_req);
  594. spin_unlock_irqrestore(&tdc->lock, flags);
  595. return cookie;
  596. }
  597. static void tegra_dma_issue_pending(struct dma_chan *dc)
  598. {
  599. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  600. unsigned long flags;
  601. int err;
  602. spin_lock_irqsave(&tdc->lock, flags);
  603. if (list_empty(&tdc->pending_sg_req)) {
  604. dev_err(tdc2dev(tdc), "No DMA request\n");
  605. goto end;
  606. }
  607. if (!tdc->busy) {
  608. err = pm_runtime_resume_and_get(tdc->tdma->dev);
  609. if (err < 0) {
  610. dev_err(tdc2dev(tdc), "Failed to enable DMA\n");
  611. goto end;
  612. }
  613. tdc_start_head_req(tdc);
  614. /* Continuous single mode: Configure next req */
  615. if (tdc->cyclic) {
  616. /*
  617. * Wait for 1 burst time for configure DMA for
  618. * next transfer.
  619. */
  620. udelay(TEGRA_APBDMA_BURST_COMPLETE_TIME);
  621. tdc_configure_next_head_desc(tdc);
  622. }
  623. }
  624. end:
  625. spin_unlock_irqrestore(&tdc->lock, flags);
  626. }
  627. static int tegra_dma_terminate_all(struct dma_chan *dc)
  628. {
  629. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  630. struct tegra_dma_desc *dma_desc;
  631. struct tegra_dma_sg_req *sgreq;
  632. unsigned long flags;
  633. u32 status, wcount;
  634. bool was_busy;
  635. spin_lock_irqsave(&tdc->lock, flags);
  636. if (!tdc->busy)
  637. goto skip_dma_stop;
  638. /* Pause DMA before checking the queue status */
  639. tegra_dma_pause(tdc, true);
  640. status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
  641. if (status & TEGRA_APBDMA_STATUS_ISE_EOC) {
  642. dev_dbg(tdc2dev(tdc), "%s():handling isr\n", __func__);
  643. tdc->isr_handler(tdc, true);
  644. status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
  645. }
  646. if (tdc->tdma->chip_data->support_separate_wcount_reg)
  647. wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
  648. else
  649. wcount = status;
  650. was_busy = tdc->busy;
  651. tegra_dma_stop(tdc);
  652. if (!list_empty(&tdc->pending_sg_req) && was_busy) {
  653. sgreq = list_first_entry(&tdc->pending_sg_req, typeof(*sgreq),
  654. node);
  655. sgreq->dma_desc->bytes_transferred +=
  656. get_current_xferred_count(tdc, sgreq, wcount);
  657. }
  658. tegra_dma_resume(tdc);
  659. pm_runtime_put(tdc->tdma->dev);
  660. wake_up_all(&tdc->wq);
  661. skip_dma_stop:
  662. tegra_dma_abort_all(tdc);
  663. while (!list_empty(&tdc->cb_desc)) {
  664. dma_desc = list_first_entry(&tdc->cb_desc, typeof(*dma_desc),
  665. cb_node);
  666. list_del(&dma_desc->cb_node);
  667. dma_desc->cb_count = 0;
  668. }
  669. spin_unlock_irqrestore(&tdc->lock, flags);
  670. return 0;
  671. }
  672. static bool tegra_dma_eoc_interrupt_deasserted(struct tegra_dma_channel *tdc)
  673. {
  674. unsigned long flags;
  675. u32 status;
  676. spin_lock_irqsave(&tdc->lock, flags);
  677. status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
  678. spin_unlock_irqrestore(&tdc->lock, flags);
  679. return !(status & TEGRA_APBDMA_STATUS_ISE_EOC);
  680. }
  681. static void tegra_dma_synchronize(struct dma_chan *dc)
  682. {
  683. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  684. int err;
  685. err = pm_runtime_resume_and_get(tdc->tdma->dev);
  686. if (err < 0) {
  687. dev_err(tdc2dev(tdc), "Failed to synchronize DMA: %d\n", err);
  688. return;
  689. }
  690. /*
  691. * CPU, which handles interrupt, could be busy in
  692. * uninterruptible state, in this case sibling CPU
  693. * should wait until interrupt is handled.
  694. */
  695. wait_event(tdc->wq, tegra_dma_eoc_interrupt_deasserted(tdc));
  696. tasklet_kill(&tdc->tasklet);
  697. pm_runtime_put(tdc->tdma->dev);
  698. }
  699. static unsigned int tegra_dma_sg_bytes_xferred(struct tegra_dma_channel *tdc,
  700. struct tegra_dma_sg_req *sg_req)
  701. {
  702. u32 status, wcount = 0;
  703. if (!list_is_first(&sg_req->node, &tdc->pending_sg_req))
  704. return 0;
  705. if (tdc->tdma->chip_data->support_separate_wcount_reg)
  706. wcount = tdc_read(tdc, TEGRA_APBDMA_CHAN_WORD_TRANSFER);
  707. status = tdc_read(tdc, TEGRA_APBDMA_CHAN_STATUS);
  708. if (!tdc->tdma->chip_data->support_separate_wcount_reg)
  709. wcount = status;
  710. if (status & TEGRA_APBDMA_STATUS_ISE_EOC)
  711. return sg_req->req_len;
  712. wcount = get_current_xferred_count(tdc, sg_req, wcount);
  713. if (!wcount) {
  714. /*
  715. * If wcount wasn't ever polled for this SG before, then
  716. * simply assume that transfer hasn't started yet.
  717. *
  718. * Otherwise it's the end of the transfer.
  719. *
  720. * The alternative would be to poll the status register
  721. * until EOC bit is set or wcount goes UP. That's so
  722. * because EOC bit is getting set only after the last
  723. * burst's completion and counter is less than the actual
  724. * transfer size by 4 bytes. The counter value wraps around
  725. * in a cyclic mode before EOC is set(!), so we can't easily
  726. * distinguish start of transfer from its end.
  727. */
  728. if (sg_req->words_xferred)
  729. wcount = sg_req->req_len - 4;
  730. } else if (wcount < sg_req->words_xferred) {
  731. /*
  732. * This case will never happen for a non-cyclic transfer.
  733. *
  734. * For a cyclic transfer, although it is possible for the
  735. * next transfer to have already started (resetting the word
  736. * count), this case should still not happen because we should
  737. * have detected that the EOC bit is set and hence the transfer
  738. * was completed.
  739. */
  740. WARN_ON_ONCE(1);
  741. wcount = sg_req->req_len - 4;
  742. } else {
  743. sg_req->words_xferred = wcount;
  744. }
  745. return wcount;
  746. }
  747. static enum dma_status tegra_dma_tx_status(struct dma_chan *dc,
  748. dma_cookie_t cookie,
  749. struct dma_tx_state *txstate)
  750. {
  751. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  752. struct tegra_dma_desc *dma_desc;
  753. struct tegra_dma_sg_req *sg_req;
  754. enum dma_status ret;
  755. unsigned long flags;
  756. unsigned int residual;
  757. unsigned int bytes = 0;
  758. ret = dma_cookie_status(dc, cookie, txstate);
  759. if (ret == DMA_COMPLETE)
  760. return ret;
  761. spin_lock_irqsave(&tdc->lock, flags);
  762. /* Check on wait_ack desc status */
  763. list_for_each_entry(dma_desc, &tdc->free_dma_desc, node) {
  764. if (dma_desc->txd.cookie == cookie) {
  765. ret = dma_desc->dma_status;
  766. goto found;
  767. }
  768. }
  769. /* Check in pending list */
  770. list_for_each_entry(sg_req, &tdc->pending_sg_req, node) {
  771. dma_desc = sg_req->dma_desc;
  772. if (dma_desc->txd.cookie == cookie) {
  773. bytes = tegra_dma_sg_bytes_xferred(tdc, sg_req);
  774. ret = dma_desc->dma_status;
  775. goto found;
  776. }
  777. }
  778. dev_dbg(tdc2dev(tdc), "cookie %d not found\n", cookie);
  779. dma_desc = NULL;
  780. found:
  781. if (dma_desc && txstate) {
  782. residual = dma_desc->bytes_requested -
  783. ((dma_desc->bytes_transferred + bytes) %
  784. dma_desc->bytes_requested);
  785. dma_set_residue(txstate, residual);
  786. }
  787. trace_tegra_dma_tx_status(&tdc->dma_chan, cookie, txstate);
  788. spin_unlock_irqrestore(&tdc->lock, flags);
  789. return ret;
  790. }
  791. static inline unsigned int get_bus_width(struct tegra_dma_channel *tdc,
  792. enum dma_slave_buswidth slave_bw)
  793. {
  794. switch (slave_bw) {
  795. case DMA_SLAVE_BUSWIDTH_1_BYTE:
  796. return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_8;
  797. case DMA_SLAVE_BUSWIDTH_2_BYTES:
  798. return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_16;
  799. case DMA_SLAVE_BUSWIDTH_4_BYTES:
  800. return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
  801. case DMA_SLAVE_BUSWIDTH_8_BYTES:
  802. return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_64;
  803. default:
  804. dev_warn(tdc2dev(tdc),
  805. "slave bw is not supported, using 32bits\n");
  806. return TEGRA_APBDMA_APBSEQ_BUS_WIDTH_32;
  807. }
  808. }
  809. static inline unsigned int get_burst_size(struct tegra_dma_channel *tdc,
  810. u32 burst_size,
  811. enum dma_slave_buswidth slave_bw,
  812. u32 len)
  813. {
  814. unsigned int burst_byte, burst_ahb_width;
  815. /*
  816. * burst_size from client is in terms of the bus_width.
  817. * convert them into AHB memory width which is 4 byte.
  818. */
  819. burst_byte = burst_size * slave_bw;
  820. burst_ahb_width = burst_byte / 4;
  821. /* If burst size is 0 then calculate the burst size based on length */
  822. if (!burst_ahb_width) {
  823. if (len & 0xF)
  824. return TEGRA_APBDMA_AHBSEQ_BURST_1;
  825. else if ((len >> 4) & 0x1)
  826. return TEGRA_APBDMA_AHBSEQ_BURST_4;
  827. else
  828. return TEGRA_APBDMA_AHBSEQ_BURST_8;
  829. }
  830. if (burst_ahb_width < 4)
  831. return TEGRA_APBDMA_AHBSEQ_BURST_1;
  832. else if (burst_ahb_width < 8)
  833. return TEGRA_APBDMA_AHBSEQ_BURST_4;
  834. else
  835. return TEGRA_APBDMA_AHBSEQ_BURST_8;
  836. }
  837. static int get_transfer_param(struct tegra_dma_channel *tdc,
  838. enum dma_transfer_direction direction,
  839. u32 *apb_addr,
  840. u32 *apb_seq,
  841. u32 *csr,
  842. unsigned int *burst_size,
  843. enum dma_slave_buswidth *slave_bw)
  844. {
  845. switch (direction) {
  846. case DMA_MEM_TO_DEV:
  847. *apb_addr = tdc->dma_sconfig.dst_addr;
  848. *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width);
  849. *burst_size = tdc->dma_sconfig.dst_maxburst;
  850. *slave_bw = tdc->dma_sconfig.dst_addr_width;
  851. *csr = TEGRA_APBDMA_CSR_DIR;
  852. return 0;
  853. case DMA_DEV_TO_MEM:
  854. *apb_addr = tdc->dma_sconfig.src_addr;
  855. *apb_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width);
  856. *burst_size = tdc->dma_sconfig.src_maxburst;
  857. *slave_bw = tdc->dma_sconfig.src_addr_width;
  858. *csr = 0;
  859. return 0;
  860. default:
  861. dev_err(tdc2dev(tdc), "DMA direction is not supported\n");
  862. break;
  863. }
  864. return -EINVAL;
  865. }
  866. static void tegra_dma_prep_wcount(struct tegra_dma_channel *tdc,
  867. struct tegra_dma_channel_regs *ch_regs,
  868. u32 len)
  869. {
  870. u32 len_field = (len - 4) & 0xFFFC;
  871. if (tdc->tdma->chip_data->support_separate_wcount_reg)
  872. ch_regs->wcount = len_field;
  873. else
  874. ch_regs->csr |= len_field;
  875. }
  876. static struct dma_async_tx_descriptor *
  877. tegra_dma_prep_slave_sg(struct dma_chan *dc,
  878. struct scatterlist *sgl,
  879. unsigned int sg_len,
  880. enum dma_transfer_direction direction,
  881. unsigned long flags,
  882. void *context)
  883. {
  884. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  885. struct tegra_dma_sg_req *sg_req = NULL;
  886. u32 csr, ahb_seq, apb_ptr, apb_seq;
  887. enum dma_slave_buswidth slave_bw;
  888. struct tegra_dma_desc *dma_desc;
  889. struct list_head req_list;
  890. struct scatterlist *sg;
  891. unsigned int burst_size;
  892. unsigned int i;
  893. if (!tdc->config_init) {
  894. dev_err(tdc2dev(tdc), "DMA channel is not configured\n");
  895. return NULL;
  896. }
  897. if (sg_len < 1) {
  898. dev_err(tdc2dev(tdc), "Invalid segment length %d\n", sg_len);
  899. return NULL;
  900. }
  901. if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
  902. &burst_size, &slave_bw) < 0)
  903. return NULL;
  904. INIT_LIST_HEAD(&req_list);
  905. ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
  906. ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
  907. TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
  908. ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
  909. csr |= TEGRA_APBDMA_CSR_ONCE;
  910. if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
  911. csr |= TEGRA_APBDMA_CSR_FLOW;
  912. csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
  913. }
  914. if (flags & DMA_PREP_INTERRUPT) {
  915. csr |= TEGRA_APBDMA_CSR_IE_EOC;
  916. } else {
  917. WARN_ON_ONCE(1);
  918. return NULL;
  919. }
  920. apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
  921. dma_desc = tegra_dma_desc_get(tdc);
  922. if (!dma_desc) {
  923. dev_err(tdc2dev(tdc), "DMA descriptors not available\n");
  924. return NULL;
  925. }
  926. INIT_LIST_HEAD(&dma_desc->tx_list);
  927. INIT_LIST_HEAD(&dma_desc->cb_node);
  928. dma_desc->cb_count = 0;
  929. dma_desc->bytes_requested = 0;
  930. dma_desc->bytes_transferred = 0;
  931. dma_desc->dma_status = DMA_IN_PROGRESS;
  932. /* Make transfer requests */
  933. for_each_sg(sgl, sg, sg_len, i) {
  934. u32 len, mem;
  935. mem = sg_dma_address(sg);
  936. len = sg_dma_len(sg);
  937. if ((len & 3) || (mem & 3) ||
  938. len > tdc->tdma->chip_data->max_dma_count) {
  939. dev_err(tdc2dev(tdc),
  940. "DMA length/memory address is not supported\n");
  941. tegra_dma_desc_put(tdc, dma_desc);
  942. return NULL;
  943. }
  944. sg_req = tegra_dma_sg_req_get(tdc);
  945. if (!sg_req) {
  946. dev_err(tdc2dev(tdc), "DMA sg-req not available\n");
  947. tegra_dma_desc_put(tdc, dma_desc);
  948. return NULL;
  949. }
  950. ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
  951. dma_desc->bytes_requested += len;
  952. sg_req->ch_regs.apb_ptr = apb_ptr;
  953. sg_req->ch_regs.ahb_ptr = mem;
  954. sg_req->ch_regs.csr = csr;
  955. tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
  956. sg_req->ch_regs.apb_seq = apb_seq;
  957. sg_req->ch_regs.ahb_seq = ahb_seq;
  958. sg_req->configured = false;
  959. sg_req->last_sg = false;
  960. sg_req->dma_desc = dma_desc;
  961. sg_req->req_len = len;
  962. list_add_tail(&sg_req->node, &dma_desc->tx_list);
  963. }
  964. sg_req->last_sg = true;
  965. if (flags & DMA_CTRL_ACK)
  966. dma_desc->txd.flags = DMA_CTRL_ACK;
  967. /*
  968. * Make sure that mode should not be conflicting with currently
  969. * configured mode.
  970. */
  971. if (!tdc->isr_handler) {
  972. tdc->isr_handler = handle_once_dma_done;
  973. tdc->cyclic = false;
  974. } else {
  975. if (tdc->cyclic) {
  976. dev_err(tdc2dev(tdc), "DMA configured in cyclic mode\n");
  977. tegra_dma_desc_put(tdc, dma_desc);
  978. return NULL;
  979. }
  980. }
  981. return &dma_desc->txd;
  982. }
  983. static struct dma_async_tx_descriptor *
  984. tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr,
  985. size_t buf_len,
  986. size_t period_len,
  987. enum dma_transfer_direction direction,
  988. unsigned long flags)
  989. {
  990. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  991. struct tegra_dma_sg_req *sg_req = NULL;
  992. u32 csr, ahb_seq, apb_ptr, apb_seq;
  993. enum dma_slave_buswidth slave_bw;
  994. struct tegra_dma_desc *dma_desc;
  995. dma_addr_t mem = buf_addr;
  996. unsigned int burst_size;
  997. size_t len, remain_len;
  998. if (!buf_len || !period_len) {
  999. dev_err(tdc2dev(tdc), "Invalid buffer/period len\n");
  1000. return NULL;
  1001. }
  1002. if (!tdc->config_init) {
  1003. dev_err(tdc2dev(tdc), "DMA slave is not configured\n");
  1004. return NULL;
  1005. }
  1006. /*
  1007. * We allow to take more number of requests till DMA is
  1008. * not started. The driver will loop over all requests.
  1009. * Once DMA is started then new requests can be queued only after
  1010. * terminating the DMA.
  1011. */
  1012. if (tdc->busy) {
  1013. dev_err(tdc2dev(tdc), "Request not allowed when DMA running\n");
  1014. return NULL;
  1015. }
  1016. /*
  1017. * We only support cycle transfer when buf_len is multiple of
  1018. * period_len.
  1019. */
  1020. if (buf_len % period_len) {
  1021. dev_err(tdc2dev(tdc), "buf_len is not multiple of period_len\n");
  1022. return NULL;
  1023. }
  1024. len = period_len;
  1025. if ((len & 3) || (buf_addr & 3) ||
  1026. len > tdc->tdma->chip_data->max_dma_count) {
  1027. dev_err(tdc2dev(tdc), "Req len/mem address is not correct\n");
  1028. return NULL;
  1029. }
  1030. if (get_transfer_param(tdc, direction, &apb_ptr, &apb_seq, &csr,
  1031. &burst_size, &slave_bw) < 0)
  1032. return NULL;
  1033. ahb_seq = TEGRA_APBDMA_AHBSEQ_INTR_ENB;
  1034. ahb_seq |= TEGRA_APBDMA_AHBSEQ_WRAP_NONE <<
  1035. TEGRA_APBDMA_AHBSEQ_WRAP_SHIFT;
  1036. ahb_seq |= TEGRA_APBDMA_AHBSEQ_BUS_WIDTH_32;
  1037. if (tdc->slave_id != TEGRA_APBDMA_SLAVE_ID_INVALID) {
  1038. csr |= TEGRA_APBDMA_CSR_FLOW;
  1039. csr |= tdc->slave_id << TEGRA_APBDMA_CSR_REQ_SEL_SHIFT;
  1040. }
  1041. if (flags & DMA_PREP_INTERRUPT) {
  1042. csr |= TEGRA_APBDMA_CSR_IE_EOC;
  1043. } else {
  1044. WARN_ON_ONCE(1);
  1045. return NULL;
  1046. }
  1047. apb_seq |= TEGRA_APBDMA_APBSEQ_WRAP_WORD_1;
  1048. dma_desc = tegra_dma_desc_get(tdc);
  1049. if (!dma_desc) {
  1050. dev_err(tdc2dev(tdc), "not enough descriptors available\n");
  1051. return NULL;
  1052. }
  1053. INIT_LIST_HEAD(&dma_desc->tx_list);
  1054. INIT_LIST_HEAD(&dma_desc->cb_node);
  1055. dma_desc->cb_count = 0;
  1056. dma_desc->bytes_transferred = 0;
  1057. dma_desc->bytes_requested = buf_len;
  1058. remain_len = buf_len;
  1059. /* Split transfer equal to period size */
  1060. while (remain_len) {
  1061. sg_req = tegra_dma_sg_req_get(tdc);
  1062. if (!sg_req) {
  1063. dev_err(tdc2dev(tdc), "DMA sg-req not available\n");
  1064. tegra_dma_desc_put(tdc, dma_desc);
  1065. return NULL;
  1066. }
  1067. ahb_seq |= get_burst_size(tdc, burst_size, slave_bw, len);
  1068. sg_req->ch_regs.apb_ptr = apb_ptr;
  1069. sg_req->ch_regs.ahb_ptr = mem;
  1070. sg_req->ch_regs.csr = csr;
  1071. tegra_dma_prep_wcount(tdc, &sg_req->ch_regs, len);
  1072. sg_req->ch_regs.apb_seq = apb_seq;
  1073. sg_req->ch_regs.ahb_seq = ahb_seq;
  1074. sg_req->configured = false;
  1075. sg_req->last_sg = false;
  1076. sg_req->dma_desc = dma_desc;
  1077. sg_req->req_len = len;
  1078. list_add_tail(&sg_req->node, &dma_desc->tx_list);
  1079. remain_len -= len;
  1080. mem += len;
  1081. }
  1082. sg_req->last_sg = true;
  1083. if (flags & DMA_CTRL_ACK)
  1084. dma_desc->txd.flags = DMA_CTRL_ACK;
  1085. /*
  1086. * Make sure that mode should not be conflicting with currently
  1087. * configured mode.
  1088. */
  1089. if (!tdc->isr_handler) {
  1090. tdc->isr_handler = handle_cont_sngl_cycle_dma_done;
  1091. tdc->cyclic = true;
  1092. } else {
  1093. if (!tdc->cyclic) {
  1094. dev_err(tdc2dev(tdc), "DMA configuration conflict\n");
  1095. tegra_dma_desc_put(tdc, dma_desc);
  1096. return NULL;
  1097. }
  1098. }
  1099. return &dma_desc->txd;
  1100. }
  1101. static int tegra_dma_alloc_chan_resources(struct dma_chan *dc)
  1102. {
  1103. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  1104. dma_cookie_init(&tdc->dma_chan);
  1105. return 0;
  1106. }
  1107. static void tegra_dma_free_chan_resources(struct dma_chan *dc)
  1108. {
  1109. struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);
  1110. struct tegra_dma_desc *dma_desc;
  1111. struct tegra_dma_sg_req *sg_req;
  1112. struct list_head dma_desc_list;
  1113. struct list_head sg_req_list;
  1114. INIT_LIST_HEAD(&dma_desc_list);
  1115. INIT_LIST_HEAD(&sg_req_list);
  1116. dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id);
  1117. tegra_dma_terminate_all(dc);
  1118. tasklet_kill(&tdc->tasklet);
  1119. list_splice_init(&tdc->pending_sg_req, &sg_req_list);
  1120. list_splice_init(&tdc->free_sg_req, &sg_req_list);
  1121. list_splice_init(&tdc->free_dma_desc, &dma_desc_list);
  1122. INIT_LIST_HEAD(&tdc->cb_desc);
  1123. tdc->config_init = false;
  1124. tdc->isr_handler = NULL;
  1125. while (!list_empty(&dma_desc_list)) {
  1126. dma_desc = list_first_entry(&dma_desc_list, typeof(*dma_desc),
  1127. node);
  1128. list_del(&dma_desc->node);
  1129. kfree(dma_desc);
  1130. }
  1131. while (!list_empty(&sg_req_list)) {
  1132. sg_req = list_first_entry(&sg_req_list, typeof(*sg_req), node);
  1133. list_del(&sg_req->node);
  1134. kfree(sg_req);
  1135. }
  1136. tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
  1137. }
  1138. static struct dma_chan *tegra_dma_of_xlate(struct of_phandle_args *dma_spec,
  1139. struct of_dma *ofdma)
  1140. {
  1141. struct tegra_dma *tdma = ofdma->of_dma_data;
  1142. struct tegra_dma_channel *tdc;
  1143. struct dma_chan *chan;
  1144. if (dma_spec->args[0] > TEGRA_APBDMA_CSR_REQ_SEL_MASK) {
  1145. dev_err(tdma->dev, "Invalid slave id: %d\n", dma_spec->args[0]);
  1146. return NULL;
  1147. }
  1148. chan = dma_get_any_slave_channel(&tdma->dma_dev);
  1149. if (!chan)
  1150. return NULL;
  1151. tdc = to_tegra_dma_chan(chan);
  1152. tdc->slave_id = dma_spec->args[0];
  1153. return chan;
  1154. }
  1155. /* Tegra20 specific DMA controller information */
  1156. static const struct tegra_dma_chip_data tegra20_dma_chip_data = {
  1157. .nr_channels = 16,
  1158. .channel_reg_size = 0x20,
  1159. .max_dma_count = 1024UL * 64,
  1160. .support_channel_pause = false,
  1161. .support_separate_wcount_reg = false,
  1162. };
  1163. /* Tegra30 specific DMA controller information */
  1164. static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
  1165. .nr_channels = 32,
  1166. .channel_reg_size = 0x20,
  1167. .max_dma_count = 1024UL * 64,
  1168. .support_channel_pause = false,
  1169. .support_separate_wcount_reg = false,
  1170. };
  1171. /* Tegra114 specific DMA controller information */
  1172. static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
  1173. .nr_channels = 32,
  1174. .channel_reg_size = 0x20,
  1175. .max_dma_count = 1024UL * 64,
  1176. .support_channel_pause = true,
  1177. .support_separate_wcount_reg = false,
  1178. };
  1179. /* Tegra148 specific DMA controller information */
  1180. static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
  1181. .nr_channels = 32,
  1182. .channel_reg_size = 0x40,
  1183. .max_dma_count = 1024UL * 64,
  1184. .support_channel_pause = true,
  1185. .support_separate_wcount_reg = true,
  1186. };
  1187. static int tegra_dma_init_hw(struct tegra_dma *tdma)
  1188. {
  1189. int err;
  1190. err = reset_control_assert(tdma->rst);
  1191. if (err) {
  1192. dev_err(tdma->dev, "failed to assert reset: %d\n", err);
  1193. return err;
  1194. }
  1195. err = clk_enable(tdma->dma_clk);
  1196. if (err) {
  1197. dev_err(tdma->dev, "failed to enable clk: %d\n", err);
  1198. return err;
  1199. }
  1200. /* reset DMA controller */
  1201. udelay(2);
  1202. reset_control_deassert(tdma->rst);
  1203. /* enable global DMA registers */
  1204. tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
  1205. tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
  1206. tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFF);
  1207. clk_disable(tdma->dma_clk);
  1208. return 0;
  1209. }
  1210. static int tegra_dma_probe(struct platform_device *pdev)
  1211. {
  1212. const struct tegra_dma_chip_data *cdata;
  1213. struct tegra_dma *tdma;
  1214. unsigned int i;
  1215. size_t size;
  1216. int ret;
  1217. cdata = of_device_get_match_data(&pdev->dev);
  1218. size = struct_size(tdma, channels, cdata->nr_channels);
  1219. tdma = devm_kzalloc(&pdev->dev, size, GFP_KERNEL);
  1220. if (!tdma)
  1221. return -ENOMEM;
  1222. tdma->dev = &pdev->dev;
  1223. tdma->chip_data = cdata;
  1224. platform_set_drvdata(pdev, tdma);
  1225. tdma->base_addr = devm_platform_ioremap_resource(pdev, 0);
  1226. if (IS_ERR(tdma->base_addr))
  1227. return PTR_ERR(tdma->base_addr);
  1228. tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);
  1229. if (IS_ERR(tdma->dma_clk)) {
  1230. dev_err(&pdev->dev, "Error: Missing controller clock\n");
  1231. return PTR_ERR(tdma->dma_clk);
  1232. }
  1233. tdma->rst = devm_reset_control_get(&pdev->dev, "dma");
  1234. if (IS_ERR(tdma->rst)) {
  1235. dev_err(&pdev->dev, "Error: Missing reset\n");
  1236. return PTR_ERR(tdma->rst);
  1237. }
  1238. spin_lock_init(&tdma->global_lock);
  1239. ret = clk_prepare(tdma->dma_clk);
  1240. if (ret)
  1241. return ret;
  1242. ret = tegra_dma_init_hw(tdma);
  1243. if (ret)
  1244. goto err_clk_unprepare;
  1245. pm_runtime_irq_safe(&pdev->dev);
  1246. pm_runtime_enable(&pdev->dev);
  1247. INIT_LIST_HEAD(&tdma->dma_dev.channels);
  1248. for (i = 0; i < cdata->nr_channels; i++) {
  1249. struct tegra_dma_channel *tdc = &tdma->channels[i];
  1250. int irq;
  1251. tdc->chan_addr = tdma->base_addr +
  1252. TEGRA_APBDMA_CHANNEL_BASE_ADD_OFFSET +
  1253. (i * cdata->channel_reg_size);
  1254. irq = platform_get_irq(pdev, i);
  1255. if (irq < 0) {
  1256. ret = irq;
  1257. goto err_pm_disable;
  1258. }
  1259. snprintf(tdc->name, sizeof(tdc->name), "apbdma.%d", i);
  1260. ret = devm_request_irq(&pdev->dev, irq, tegra_dma_isr, 0,
  1261. tdc->name, tdc);
  1262. if (ret) {
  1263. dev_err(&pdev->dev,
  1264. "request_irq failed with err %d channel %d\n",
  1265. ret, i);
  1266. goto err_pm_disable;
  1267. }
  1268. tdc->dma_chan.device = &tdma->dma_dev;
  1269. dma_cookie_init(&tdc->dma_chan);
  1270. list_add_tail(&tdc->dma_chan.device_node,
  1271. &tdma->dma_dev.channels);
  1272. tdc->tdma = tdma;
  1273. tdc->id = i;
  1274. tdc->slave_id = TEGRA_APBDMA_SLAVE_ID_INVALID;
  1275. tasklet_setup(&tdc->tasklet, tegra_dma_tasklet);
  1276. spin_lock_init(&tdc->lock);
  1277. init_waitqueue_head(&tdc->wq);
  1278. INIT_LIST_HEAD(&tdc->pending_sg_req);
  1279. INIT_LIST_HEAD(&tdc->free_sg_req);
  1280. INIT_LIST_HEAD(&tdc->free_dma_desc);
  1281. INIT_LIST_HEAD(&tdc->cb_desc);
  1282. }
  1283. dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);
  1284. dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);
  1285. dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);
  1286. tdma->global_pause_count = 0;
  1287. tdma->dma_dev.dev = &pdev->dev;
  1288. tdma->dma_dev.device_alloc_chan_resources =
  1289. tegra_dma_alloc_chan_resources;
  1290. tdma->dma_dev.device_free_chan_resources =
  1291. tegra_dma_free_chan_resources;
  1292. tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;
  1293. tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;
  1294. tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  1295. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  1296. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  1297. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
  1298. tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
  1299. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
  1300. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
  1301. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
  1302. tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  1303. tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
  1304. tdma->dma_dev.device_config = tegra_dma_slave_config;
  1305. tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;
  1306. tdma->dma_dev.device_synchronize = tegra_dma_synchronize;
  1307. tdma->dma_dev.device_tx_status = tegra_dma_tx_status;
  1308. tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;
  1309. ret = dma_async_device_register(&tdma->dma_dev);
  1310. if (ret < 0) {
  1311. dev_err(&pdev->dev,
  1312. "Tegra20 APB DMA driver registration failed %d\n", ret);
  1313. goto err_pm_disable;
  1314. }
  1315. ret = of_dma_controller_register(pdev->dev.of_node,
  1316. tegra_dma_of_xlate, tdma);
  1317. if (ret < 0) {
  1318. dev_err(&pdev->dev,
  1319. "Tegra20 APB DMA OF registration failed %d\n", ret);
  1320. goto err_unregister_dma_dev;
  1321. }
  1322. dev_info(&pdev->dev, "Tegra20 APB DMA driver registered %u channels\n",
  1323. cdata->nr_channels);
  1324. return 0;
  1325. err_unregister_dma_dev:
  1326. dma_async_device_unregister(&tdma->dma_dev);
  1327. err_pm_disable:
  1328. pm_runtime_disable(&pdev->dev);
  1329. err_clk_unprepare:
  1330. clk_unprepare(tdma->dma_clk);
  1331. return ret;
  1332. }
  1333. static int tegra_dma_remove(struct platform_device *pdev)
  1334. {
  1335. struct tegra_dma *tdma = platform_get_drvdata(pdev);
  1336. of_dma_controller_free(pdev->dev.of_node);
  1337. dma_async_device_unregister(&tdma->dma_dev);
  1338. pm_runtime_disable(&pdev->dev);
  1339. clk_unprepare(tdma->dma_clk);
  1340. return 0;
  1341. }
  1342. static int __maybe_unused tegra_dma_runtime_suspend(struct device *dev)
  1343. {
  1344. struct tegra_dma *tdma = dev_get_drvdata(dev);
  1345. clk_disable(tdma->dma_clk);
  1346. return 0;
  1347. }
  1348. static int __maybe_unused tegra_dma_runtime_resume(struct device *dev)
  1349. {
  1350. struct tegra_dma *tdma = dev_get_drvdata(dev);
  1351. return clk_enable(tdma->dma_clk);
  1352. }
  1353. static int __maybe_unused tegra_dma_dev_suspend(struct device *dev)
  1354. {
  1355. struct tegra_dma *tdma = dev_get_drvdata(dev);
  1356. unsigned long flags;
  1357. unsigned int i;
  1358. bool busy;
  1359. for (i = 0; i < tdma->chip_data->nr_channels; i++) {
  1360. struct tegra_dma_channel *tdc = &tdma->channels[i];
  1361. tasklet_kill(&tdc->tasklet);
  1362. spin_lock_irqsave(&tdc->lock, flags);
  1363. busy = tdc->busy;
  1364. spin_unlock_irqrestore(&tdc->lock, flags);
  1365. if (busy) {
  1366. dev_err(tdma->dev, "channel %u busy\n", i);
  1367. return -EBUSY;
  1368. }
  1369. }
  1370. return pm_runtime_force_suspend(dev);
  1371. }
  1372. static int __maybe_unused tegra_dma_dev_resume(struct device *dev)
  1373. {
  1374. struct tegra_dma *tdma = dev_get_drvdata(dev);
  1375. int err;
  1376. err = tegra_dma_init_hw(tdma);
  1377. if (err)
  1378. return err;
  1379. return pm_runtime_force_resume(dev);
  1380. }
  1381. static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
  1382. SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
  1383. NULL)
  1384. SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_dev_suspend, tegra_dma_dev_resume)
  1385. };
  1386. static const struct of_device_id tegra_dma_of_match[] = {
  1387. {
  1388. .compatible = "nvidia,tegra148-apbdma",
  1389. .data = &tegra148_dma_chip_data,
  1390. }, {
  1391. .compatible = "nvidia,tegra114-apbdma",
  1392. .data = &tegra114_dma_chip_data,
  1393. }, {
  1394. .compatible = "nvidia,tegra30-apbdma",
  1395. .data = &tegra30_dma_chip_data,
  1396. }, {
  1397. .compatible = "nvidia,tegra20-apbdma",
  1398. .data = &tegra20_dma_chip_data,
  1399. }, {
  1400. },
  1401. };
  1402. MODULE_DEVICE_TABLE(of, tegra_dma_of_match);
  1403. static struct platform_driver tegra_dmac_driver = {
  1404. .driver = {
  1405. .name = "tegra-apbdma",
  1406. .pm = &tegra_dma_dev_pm_ops,
  1407. .of_match_table = tegra_dma_of_match,
  1408. },
  1409. .probe = tegra_dma_probe,
  1410. .remove = tegra_dma_remove,
  1411. };
  1412. module_platform_driver(tegra_dmac_driver);
  1413. MODULE_DESCRIPTION("NVIDIA Tegra APB DMA Controller driver");
  1414. MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
  1415. MODULE_LICENSE("GPL v2");