sirf-dma.c 33 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DMA controller driver for CSR SiRFprimaII
  4. *
  5. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  6. */
  7. #include <linux/module.h>
  8. #include <linux/dmaengine.h>
  9. #include <linux/dma-mapping.h>
  10. #include <linux/pm_runtime.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/io.h>
  13. #include <linux/slab.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/of_address.h>
  16. #include <linux/of_device.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/clk.h>
  19. #include <linux/of_dma.h>
  20. #include <linux/sirfsoc_dma.h>
  21. #include "dmaengine.h"
  22. #define SIRFSOC_DMA_VER_A7V1 1
  23. #define SIRFSOC_DMA_VER_A7V2 2
  24. #define SIRFSOC_DMA_VER_A6 4
  25. #define SIRFSOC_DMA_DESCRIPTORS 16
  26. #define SIRFSOC_DMA_CHANNELS 16
  27. #define SIRFSOC_DMA_TABLE_NUM 256
  28. #define SIRFSOC_DMA_CH_ADDR 0x00
  29. #define SIRFSOC_DMA_CH_XLEN 0x04
  30. #define SIRFSOC_DMA_CH_YLEN 0x08
  31. #define SIRFSOC_DMA_CH_CTRL 0x0C
  32. #define SIRFSOC_DMA_WIDTH_0 0x100
  33. #define SIRFSOC_DMA_CH_VALID 0x140
  34. #define SIRFSOC_DMA_CH_INT 0x144
  35. #define SIRFSOC_DMA_INT_EN 0x148
  36. #define SIRFSOC_DMA_INT_EN_CLR 0x14C
  37. #define SIRFSOC_DMA_CH_LOOP_CTRL 0x150
  38. #define SIRFSOC_DMA_CH_LOOP_CTRL_CLR 0x154
  39. #define SIRFSOC_DMA_WIDTH_ATLAS7 0x10
  40. #define SIRFSOC_DMA_VALID_ATLAS7 0x14
  41. #define SIRFSOC_DMA_INT_ATLAS7 0x18
  42. #define SIRFSOC_DMA_INT_EN_ATLAS7 0x1c
  43. #define SIRFSOC_DMA_LOOP_CTRL_ATLAS7 0x20
  44. #define SIRFSOC_DMA_CUR_DATA_ADDR 0x34
  45. #define SIRFSOC_DMA_MUL_ATLAS7 0x38
  46. #define SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7 0x158
  47. #define SIRFSOC_DMA_CH_LOOP_CTRL_CLR_ATLAS7 0x15C
  48. #define SIRFSOC_DMA_IOBG_SCMD_EN 0x800
  49. #define SIRFSOC_DMA_EARLY_RESP_SET 0x818
  50. #define SIRFSOC_DMA_EARLY_RESP_CLR 0x81C
  51. #define SIRFSOC_DMA_MODE_CTRL_BIT 4
  52. #define SIRFSOC_DMA_DIR_CTRL_BIT 5
  53. #define SIRFSOC_DMA_MODE_CTRL_BIT_ATLAS7 2
  54. #define SIRFSOC_DMA_CHAIN_CTRL_BIT_ATLAS7 3
  55. #define SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7 4
  56. #define SIRFSOC_DMA_TAB_NUM_ATLAS7 7
  57. #define SIRFSOC_DMA_CHAIN_INT_BIT_ATLAS7 5
  58. #define SIRFSOC_DMA_CHAIN_FLAG_SHIFT_ATLAS7 25
  59. #define SIRFSOC_DMA_CHAIN_ADDR_SHIFT 32
  60. #define SIRFSOC_DMA_INT_FINI_INT_ATLAS7 BIT(0)
  61. #define SIRFSOC_DMA_INT_CNT_INT_ATLAS7 BIT(1)
  62. #define SIRFSOC_DMA_INT_PAU_INT_ATLAS7 BIT(2)
  63. #define SIRFSOC_DMA_INT_LOOP_INT_ATLAS7 BIT(3)
  64. #define SIRFSOC_DMA_INT_INV_INT_ATLAS7 BIT(4)
  65. #define SIRFSOC_DMA_INT_END_INT_ATLAS7 BIT(5)
  66. #define SIRFSOC_DMA_INT_ALL_ATLAS7 0x3F
  67. /* xlen and dma_width register is in 4 bytes boundary */
  68. #define SIRFSOC_DMA_WORD_LEN 4
  69. #define SIRFSOC_DMA_XLEN_MAX_V1 0x800
  70. #define SIRFSOC_DMA_XLEN_MAX_V2 0x1000
  71. struct sirfsoc_dma_desc {
  72. struct dma_async_tx_descriptor desc;
  73. struct list_head node;
  74. /* SiRFprimaII 2D-DMA parameters */
  75. int xlen; /* DMA xlen */
  76. int ylen; /* DMA ylen */
  77. int width; /* DMA width */
  78. int dir;
  79. bool cyclic; /* is loop DMA? */
  80. bool chain; /* is chain DMA? */
  81. u32 addr; /* DMA buffer address */
  82. u64 chain_table[SIRFSOC_DMA_TABLE_NUM]; /* chain tbl */
  83. };
  84. struct sirfsoc_dma_chan {
  85. struct dma_chan chan;
  86. struct list_head free;
  87. struct list_head prepared;
  88. struct list_head queued;
  89. struct list_head active;
  90. struct list_head completed;
  91. unsigned long happened_cyclic;
  92. unsigned long completed_cyclic;
  93. /* Lock for this structure */
  94. spinlock_t lock;
  95. int mode;
  96. };
  97. struct sirfsoc_dma_regs {
  98. u32 ctrl[SIRFSOC_DMA_CHANNELS];
  99. u32 interrupt_en;
  100. };
  101. struct sirfsoc_dma {
  102. struct dma_device dma;
  103. struct tasklet_struct tasklet;
  104. struct sirfsoc_dma_chan channels[SIRFSOC_DMA_CHANNELS];
  105. void __iomem *base;
  106. int irq;
  107. struct clk *clk;
  108. int type;
  109. void (*exec_desc)(struct sirfsoc_dma_desc *sdesc,
  110. int cid, int burst_mode, void __iomem *base);
  111. struct sirfsoc_dma_regs regs_save;
  112. };
  113. struct sirfsoc_dmadata {
  114. void (*exec)(struct sirfsoc_dma_desc *sdesc,
  115. int cid, int burst_mode, void __iomem *base);
  116. int type;
  117. };
  118. enum sirfsoc_dma_chain_flag {
  119. SIRFSOC_DMA_CHAIN_NORMAL = 0x01,
  120. SIRFSOC_DMA_CHAIN_PAUSE = 0x02,
  121. SIRFSOC_DMA_CHAIN_LOOP = 0x03,
  122. SIRFSOC_DMA_CHAIN_END = 0x04
  123. };
  124. #define DRV_NAME "sirfsoc_dma"
  125. static int sirfsoc_dma_runtime_suspend(struct device *dev);
  126. /* Convert struct dma_chan to struct sirfsoc_dma_chan */
  127. static inline
  128. struct sirfsoc_dma_chan *dma_chan_to_sirfsoc_dma_chan(struct dma_chan *c)
  129. {
  130. return container_of(c, struct sirfsoc_dma_chan, chan);
  131. }
  132. /* Convert struct dma_chan to struct sirfsoc_dma */
  133. static inline struct sirfsoc_dma *dma_chan_to_sirfsoc_dma(struct dma_chan *c)
  134. {
  135. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(c);
  136. return container_of(schan, struct sirfsoc_dma, channels[c->chan_id]);
  137. }
  138. static void sirfsoc_dma_execute_hw_a7v2(struct sirfsoc_dma_desc *sdesc,
  139. int cid, int burst_mode, void __iomem *base)
  140. {
  141. if (sdesc->chain) {
  142. /* DMA v2 HW chain mode */
  143. writel_relaxed((sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7) |
  144. (sdesc->chain <<
  145. SIRFSOC_DMA_CHAIN_CTRL_BIT_ATLAS7) |
  146. (0x8 << SIRFSOC_DMA_TAB_NUM_ATLAS7) | 0x3,
  147. base + SIRFSOC_DMA_CH_CTRL);
  148. } else {
  149. /* DMA v2 legacy mode */
  150. writel_relaxed(sdesc->xlen, base + SIRFSOC_DMA_CH_XLEN);
  151. writel_relaxed(sdesc->ylen, base + SIRFSOC_DMA_CH_YLEN);
  152. writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_ATLAS7);
  153. writel_relaxed((sdesc->width*((sdesc->ylen+1)>>1)),
  154. base + SIRFSOC_DMA_MUL_ATLAS7);
  155. writel_relaxed((sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT_ATLAS7) |
  156. (sdesc->chain <<
  157. SIRFSOC_DMA_CHAIN_CTRL_BIT_ATLAS7) |
  158. 0x3, base + SIRFSOC_DMA_CH_CTRL);
  159. }
  160. writel_relaxed(sdesc->chain ? SIRFSOC_DMA_INT_END_INT_ATLAS7 :
  161. (SIRFSOC_DMA_INT_FINI_INT_ATLAS7 |
  162. SIRFSOC_DMA_INT_LOOP_INT_ATLAS7),
  163. base + SIRFSOC_DMA_INT_EN_ATLAS7);
  164. writel(sdesc->addr, base + SIRFSOC_DMA_CH_ADDR);
  165. if (sdesc->cyclic)
  166. writel(0x10001, base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
  167. }
  168. static void sirfsoc_dma_execute_hw_a7v1(struct sirfsoc_dma_desc *sdesc,
  169. int cid, int burst_mode, void __iomem *base)
  170. {
  171. writel_relaxed(1, base + SIRFSOC_DMA_IOBG_SCMD_EN);
  172. writel_relaxed((1 << cid), base + SIRFSOC_DMA_EARLY_RESP_SET);
  173. writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4);
  174. writel_relaxed(cid | (burst_mode << SIRFSOC_DMA_MODE_CTRL_BIT) |
  175. (sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT),
  176. base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL);
  177. writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN);
  178. writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN);
  179. writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) |
  180. (1 << cid), base + SIRFSOC_DMA_INT_EN);
  181. writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR);
  182. if (sdesc->cyclic) {
  183. writel((1 << cid) | 1 << (cid + 16) |
  184. readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7),
  185. base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7);
  186. }
  187. }
  188. static void sirfsoc_dma_execute_hw_a6(struct sirfsoc_dma_desc *sdesc,
  189. int cid, int burst_mode, void __iomem *base)
  190. {
  191. writel_relaxed(sdesc->width, base + SIRFSOC_DMA_WIDTH_0 + cid * 4);
  192. writel_relaxed(cid | (burst_mode << SIRFSOC_DMA_MODE_CTRL_BIT) |
  193. (sdesc->dir << SIRFSOC_DMA_DIR_CTRL_BIT),
  194. base + cid * 0x10 + SIRFSOC_DMA_CH_CTRL);
  195. writel_relaxed(sdesc->xlen, base + cid * 0x10 + SIRFSOC_DMA_CH_XLEN);
  196. writel_relaxed(sdesc->ylen, base + cid * 0x10 + SIRFSOC_DMA_CH_YLEN);
  197. writel_relaxed(readl_relaxed(base + SIRFSOC_DMA_INT_EN) |
  198. (1 << cid), base + SIRFSOC_DMA_INT_EN);
  199. writel(sdesc->addr >> 2, base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR);
  200. if (sdesc->cyclic) {
  201. writel((1 << cid) | 1 << (cid + 16) |
  202. readl_relaxed(base + SIRFSOC_DMA_CH_LOOP_CTRL),
  203. base + SIRFSOC_DMA_CH_LOOP_CTRL);
  204. }
  205. }
  206. /* Execute all queued DMA descriptors */
  207. static void sirfsoc_dma_execute(struct sirfsoc_dma_chan *schan)
  208. {
  209. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
  210. int cid = schan->chan.chan_id;
  211. struct sirfsoc_dma_desc *sdesc = NULL;
  212. void __iomem *base;
  213. /*
  214. * lock has been held by functions calling this, so we don't hold
  215. * lock again
  216. */
  217. base = sdma->base;
  218. sdesc = list_first_entry(&schan->queued, struct sirfsoc_dma_desc,
  219. node);
  220. /* Move the first queued descriptor to active list */
  221. list_move_tail(&sdesc->node, &schan->active);
  222. if (sdma->type == SIRFSOC_DMA_VER_A7V2)
  223. cid = 0;
  224. /* Start the DMA transfer */
  225. sdma->exec_desc(sdesc, cid, schan->mode, base);
  226. if (sdesc->cyclic)
  227. schan->happened_cyclic = schan->completed_cyclic = 0;
  228. }
  229. /* Interrupt handler */
  230. static irqreturn_t sirfsoc_dma_irq(int irq, void *data)
  231. {
  232. struct sirfsoc_dma *sdma = data;
  233. struct sirfsoc_dma_chan *schan;
  234. struct sirfsoc_dma_desc *sdesc = NULL;
  235. u32 is;
  236. bool chain;
  237. int ch;
  238. void __iomem *reg;
  239. switch (sdma->type) {
  240. case SIRFSOC_DMA_VER_A6:
  241. case SIRFSOC_DMA_VER_A7V1:
  242. is = readl(sdma->base + SIRFSOC_DMA_CH_INT);
  243. reg = sdma->base + SIRFSOC_DMA_CH_INT;
  244. while ((ch = fls(is) - 1) >= 0) {
  245. is &= ~(1 << ch);
  246. writel_relaxed(1 << ch, reg);
  247. schan = &sdma->channels[ch];
  248. spin_lock(&schan->lock);
  249. sdesc = list_first_entry(&schan->active,
  250. struct sirfsoc_dma_desc, node);
  251. if (!sdesc->cyclic) {
  252. /* Execute queued descriptors */
  253. list_splice_tail_init(&schan->active,
  254. &schan->completed);
  255. dma_cookie_complete(&sdesc->desc);
  256. if (!list_empty(&schan->queued))
  257. sirfsoc_dma_execute(schan);
  258. } else
  259. schan->happened_cyclic++;
  260. spin_unlock(&schan->lock);
  261. }
  262. break;
  263. case SIRFSOC_DMA_VER_A7V2:
  264. is = readl(sdma->base + SIRFSOC_DMA_INT_ATLAS7);
  265. reg = sdma->base + SIRFSOC_DMA_INT_ATLAS7;
  266. writel_relaxed(SIRFSOC_DMA_INT_ALL_ATLAS7, reg);
  267. schan = &sdma->channels[0];
  268. spin_lock(&schan->lock);
  269. sdesc = list_first_entry(&schan->active,
  270. struct sirfsoc_dma_desc, node);
  271. if (!sdesc->cyclic) {
  272. chain = sdesc->chain;
  273. if ((chain && (is & SIRFSOC_DMA_INT_END_INT_ATLAS7)) ||
  274. (!chain &&
  275. (is & SIRFSOC_DMA_INT_FINI_INT_ATLAS7))) {
  276. /* Execute queued descriptors */
  277. list_splice_tail_init(&schan->active,
  278. &schan->completed);
  279. dma_cookie_complete(&sdesc->desc);
  280. if (!list_empty(&schan->queued))
  281. sirfsoc_dma_execute(schan);
  282. }
  283. } else if (sdesc->cyclic && (is &
  284. SIRFSOC_DMA_INT_LOOP_INT_ATLAS7))
  285. schan->happened_cyclic++;
  286. spin_unlock(&schan->lock);
  287. break;
  288. default:
  289. break;
  290. }
  291. /* Schedule tasklet */
  292. tasklet_schedule(&sdma->tasklet);
  293. return IRQ_HANDLED;
  294. }
  295. /* process completed descriptors */
  296. static void sirfsoc_dma_process_completed(struct sirfsoc_dma *sdma)
  297. {
  298. dma_cookie_t last_cookie = 0;
  299. struct sirfsoc_dma_chan *schan;
  300. struct sirfsoc_dma_desc *sdesc;
  301. struct dma_async_tx_descriptor *desc;
  302. unsigned long flags;
  303. unsigned long happened_cyclic;
  304. LIST_HEAD(list);
  305. int i;
  306. for (i = 0; i < sdma->dma.chancnt; i++) {
  307. schan = &sdma->channels[i];
  308. /* Get all completed descriptors */
  309. spin_lock_irqsave(&schan->lock, flags);
  310. if (!list_empty(&schan->completed)) {
  311. list_splice_tail_init(&schan->completed, &list);
  312. spin_unlock_irqrestore(&schan->lock, flags);
  313. /* Execute callbacks and run dependencies */
  314. list_for_each_entry(sdesc, &list, node) {
  315. desc = &sdesc->desc;
  316. dmaengine_desc_get_callback_invoke(desc, NULL);
  317. last_cookie = desc->cookie;
  318. dma_run_dependencies(desc);
  319. }
  320. /* Free descriptors */
  321. spin_lock_irqsave(&schan->lock, flags);
  322. list_splice_tail_init(&list, &schan->free);
  323. schan->chan.completed_cookie = last_cookie;
  324. spin_unlock_irqrestore(&schan->lock, flags);
  325. } else {
  326. if (list_empty(&schan->active)) {
  327. spin_unlock_irqrestore(&schan->lock, flags);
  328. continue;
  329. }
  330. /* for cyclic channel, desc is always in active list */
  331. sdesc = list_first_entry(&schan->active,
  332. struct sirfsoc_dma_desc, node);
  333. /* cyclic DMA */
  334. happened_cyclic = schan->happened_cyclic;
  335. spin_unlock_irqrestore(&schan->lock, flags);
  336. desc = &sdesc->desc;
  337. while (happened_cyclic != schan->completed_cyclic) {
  338. dmaengine_desc_get_callback_invoke(desc, NULL);
  339. schan->completed_cyclic++;
  340. }
  341. }
  342. }
  343. }
  344. /* DMA Tasklet */
  345. static void sirfsoc_dma_tasklet(struct tasklet_struct *t)
  346. {
  347. struct sirfsoc_dma *sdma = from_tasklet(sdma, t, tasklet);
  348. sirfsoc_dma_process_completed(sdma);
  349. }
  350. /* Submit descriptor to hardware */
  351. static dma_cookie_t sirfsoc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
  352. {
  353. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(txd->chan);
  354. struct sirfsoc_dma_desc *sdesc;
  355. unsigned long flags;
  356. dma_cookie_t cookie;
  357. sdesc = container_of(txd, struct sirfsoc_dma_desc, desc);
  358. spin_lock_irqsave(&schan->lock, flags);
  359. /* Move descriptor to queue */
  360. list_move_tail(&sdesc->node, &schan->queued);
  361. cookie = dma_cookie_assign(txd);
  362. spin_unlock_irqrestore(&schan->lock, flags);
  363. return cookie;
  364. }
  365. static int sirfsoc_dma_slave_config(struct dma_chan *chan,
  366. struct dma_slave_config *config)
  367. {
  368. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  369. unsigned long flags;
  370. if ((config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
  371. (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES))
  372. return -EINVAL;
  373. spin_lock_irqsave(&schan->lock, flags);
  374. schan->mode = (config->src_maxburst == 4 ? 1 : 0);
  375. spin_unlock_irqrestore(&schan->lock, flags);
  376. return 0;
  377. }
  378. static int sirfsoc_dma_terminate_all(struct dma_chan *chan)
  379. {
  380. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  381. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
  382. int cid = schan->chan.chan_id;
  383. unsigned long flags;
  384. spin_lock_irqsave(&schan->lock, flags);
  385. switch (sdma->type) {
  386. case SIRFSOC_DMA_VER_A7V1:
  387. writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_INT_EN_CLR);
  388. writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_INT);
  389. writel_relaxed((1 << cid) | 1 << (cid + 16),
  390. sdma->base +
  391. SIRFSOC_DMA_CH_LOOP_CTRL_CLR_ATLAS7);
  392. writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);
  393. break;
  394. case SIRFSOC_DMA_VER_A7V2:
  395. writel_relaxed(0, sdma->base + SIRFSOC_DMA_INT_EN_ATLAS7);
  396. writel_relaxed(SIRFSOC_DMA_INT_ALL_ATLAS7,
  397. sdma->base + SIRFSOC_DMA_INT_ATLAS7);
  398. writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
  399. writel_relaxed(0, sdma->base + SIRFSOC_DMA_VALID_ATLAS7);
  400. break;
  401. case SIRFSOC_DMA_VER_A6:
  402. writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) &
  403. ~(1 << cid), sdma->base + SIRFSOC_DMA_INT_EN);
  404. writel_relaxed(readl_relaxed(sdma->base +
  405. SIRFSOC_DMA_CH_LOOP_CTRL) &
  406. ~((1 << cid) | 1 << (cid + 16)),
  407. sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
  408. writel_relaxed(1 << cid, sdma->base + SIRFSOC_DMA_CH_VALID);
  409. break;
  410. default:
  411. break;
  412. }
  413. list_splice_tail_init(&schan->active, &schan->free);
  414. list_splice_tail_init(&schan->queued, &schan->free);
  415. spin_unlock_irqrestore(&schan->lock, flags);
  416. return 0;
  417. }
  418. static int sirfsoc_dma_pause_chan(struct dma_chan *chan)
  419. {
  420. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  421. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
  422. int cid = schan->chan.chan_id;
  423. unsigned long flags;
  424. spin_lock_irqsave(&schan->lock, flags);
  425. switch (sdma->type) {
  426. case SIRFSOC_DMA_VER_A7V1:
  427. writel_relaxed((1 << cid) | 1 << (cid + 16),
  428. sdma->base +
  429. SIRFSOC_DMA_CH_LOOP_CTRL_CLR_ATLAS7);
  430. break;
  431. case SIRFSOC_DMA_VER_A7V2:
  432. writel_relaxed(0, sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
  433. break;
  434. case SIRFSOC_DMA_VER_A6:
  435. writel_relaxed(readl_relaxed(sdma->base +
  436. SIRFSOC_DMA_CH_LOOP_CTRL) &
  437. ~((1 << cid) | 1 << (cid + 16)),
  438. sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
  439. break;
  440. default:
  441. break;
  442. }
  443. spin_unlock_irqrestore(&schan->lock, flags);
  444. return 0;
  445. }
  446. static int sirfsoc_dma_resume_chan(struct dma_chan *chan)
  447. {
  448. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  449. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(&schan->chan);
  450. int cid = schan->chan.chan_id;
  451. unsigned long flags;
  452. spin_lock_irqsave(&schan->lock, flags);
  453. switch (sdma->type) {
  454. case SIRFSOC_DMA_VER_A7V1:
  455. writel_relaxed((1 << cid) | 1 << (cid + 16),
  456. sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL_ATLAS7);
  457. break;
  458. case SIRFSOC_DMA_VER_A7V2:
  459. writel_relaxed(0x10001,
  460. sdma->base + SIRFSOC_DMA_LOOP_CTRL_ATLAS7);
  461. break;
  462. case SIRFSOC_DMA_VER_A6:
  463. writel_relaxed(readl_relaxed(sdma->base +
  464. SIRFSOC_DMA_CH_LOOP_CTRL) |
  465. ((1 << cid) | 1 << (cid + 16)),
  466. sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL);
  467. break;
  468. default:
  469. break;
  470. }
  471. spin_unlock_irqrestore(&schan->lock, flags);
  472. return 0;
  473. }
  474. /* Alloc channel resources */
  475. static int sirfsoc_dma_alloc_chan_resources(struct dma_chan *chan)
  476. {
  477. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
  478. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  479. struct sirfsoc_dma_desc *sdesc;
  480. unsigned long flags;
  481. LIST_HEAD(descs);
  482. int i;
  483. pm_runtime_get_sync(sdma->dma.dev);
  484. /* Alloc descriptors for this channel */
  485. for (i = 0; i < SIRFSOC_DMA_DESCRIPTORS; i++) {
  486. sdesc = kzalloc(sizeof(*sdesc), GFP_KERNEL);
  487. if (!sdesc) {
  488. dev_notice(sdma->dma.dev, "Memory allocation error. "
  489. "Allocated only %u descriptors\n", i);
  490. break;
  491. }
  492. dma_async_tx_descriptor_init(&sdesc->desc, chan);
  493. sdesc->desc.flags = DMA_CTRL_ACK;
  494. sdesc->desc.tx_submit = sirfsoc_dma_tx_submit;
  495. list_add_tail(&sdesc->node, &descs);
  496. }
  497. /* Return error only if no descriptors were allocated */
  498. if (i == 0)
  499. return -ENOMEM;
  500. spin_lock_irqsave(&schan->lock, flags);
  501. list_splice_tail_init(&descs, &schan->free);
  502. spin_unlock_irqrestore(&schan->lock, flags);
  503. return i;
  504. }
  505. /* Free channel resources */
  506. static void sirfsoc_dma_free_chan_resources(struct dma_chan *chan)
  507. {
  508. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  509. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
  510. struct sirfsoc_dma_desc *sdesc, *tmp;
  511. unsigned long flags;
  512. LIST_HEAD(descs);
  513. spin_lock_irqsave(&schan->lock, flags);
  514. /* Channel must be idle */
  515. BUG_ON(!list_empty(&schan->prepared));
  516. BUG_ON(!list_empty(&schan->queued));
  517. BUG_ON(!list_empty(&schan->active));
  518. BUG_ON(!list_empty(&schan->completed));
  519. /* Move data */
  520. list_splice_tail_init(&schan->free, &descs);
  521. spin_unlock_irqrestore(&schan->lock, flags);
  522. /* Free descriptors */
  523. list_for_each_entry_safe(sdesc, tmp, &descs, node)
  524. kfree(sdesc);
  525. pm_runtime_put(sdma->dma.dev);
  526. }
  527. /* Send pending descriptor to hardware */
  528. static void sirfsoc_dma_issue_pending(struct dma_chan *chan)
  529. {
  530. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  531. unsigned long flags;
  532. spin_lock_irqsave(&schan->lock, flags);
  533. if (list_empty(&schan->active) && !list_empty(&schan->queued))
  534. sirfsoc_dma_execute(schan);
  535. spin_unlock_irqrestore(&schan->lock, flags);
  536. }
  537. /* Check request completion status */
  538. static enum dma_status
  539. sirfsoc_dma_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
  540. struct dma_tx_state *txstate)
  541. {
  542. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
  543. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  544. unsigned long flags;
  545. enum dma_status ret;
  546. struct sirfsoc_dma_desc *sdesc;
  547. int cid = schan->chan.chan_id;
  548. unsigned long dma_pos;
  549. unsigned long dma_request_bytes;
  550. unsigned long residue;
  551. spin_lock_irqsave(&schan->lock, flags);
  552. if (list_empty(&schan->active)) {
  553. ret = dma_cookie_status(chan, cookie, txstate);
  554. dma_set_residue(txstate, 0);
  555. spin_unlock_irqrestore(&schan->lock, flags);
  556. return ret;
  557. }
  558. sdesc = list_first_entry(&schan->active, struct sirfsoc_dma_desc, node);
  559. if (sdesc->cyclic)
  560. dma_request_bytes = (sdesc->xlen + 1) * (sdesc->ylen + 1) *
  561. (sdesc->width * SIRFSOC_DMA_WORD_LEN);
  562. else
  563. dma_request_bytes = sdesc->xlen * SIRFSOC_DMA_WORD_LEN;
  564. ret = dma_cookie_status(chan, cookie, txstate);
  565. if (sdma->type == SIRFSOC_DMA_VER_A7V2)
  566. cid = 0;
  567. if (sdma->type == SIRFSOC_DMA_VER_A7V2) {
  568. dma_pos = readl_relaxed(sdma->base + SIRFSOC_DMA_CUR_DATA_ADDR);
  569. } else {
  570. dma_pos = readl_relaxed(
  571. sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) << 2;
  572. }
  573. residue = dma_request_bytes - (dma_pos - sdesc->addr);
  574. dma_set_residue(txstate, residue);
  575. spin_unlock_irqrestore(&schan->lock, flags);
  576. return ret;
  577. }
  578. static struct dma_async_tx_descriptor *sirfsoc_dma_prep_interleaved(
  579. struct dma_chan *chan, struct dma_interleaved_template *xt,
  580. unsigned long flags)
  581. {
  582. struct sirfsoc_dma *sdma = dma_chan_to_sirfsoc_dma(chan);
  583. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  584. struct sirfsoc_dma_desc *sdesc = NULL;
  585. unsigned long iflags;
  586. int ret;
  587. if ((xt->dir != DMA_MEM_TO_DEV) && (xt->dir != DMA_DEV_TO_MEM)) {
  588. ret = -EINVAL;
  589. goto err_dir;
  590. }
  591. /* Get free descriptor */
  592. spin_lock_irqsave(&schan->lock, iflags);
  593. if (!list_empty(&schan->free)) {
  594. sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
  595. node);
  596. list_del(&sdesc->node);
  597. }
  598. spin_unlock_irqrestore(&schan->lock, iflags);
  599. if (!sdesc) {
  600. /* try to free completed descriptors */
  601. sirfsoc_dma_process_completed(sdma);
  602. ret = 0;
  603. goto no_desc;
  604. }
  605. /* Place descriptor in prepared list */
  606. spin_lock_irqsave(&schan->lock, iflags);
  607. /*
  608. * Number of chunks in a frame can only be 1 for prima2
  609. * and ylen (number of frame - 1) must be at least 0
  610. */
  611. if ((xt->frame_size == 1) && (xt->numf > 0)) {
  612. sdesc->cyclic = 0;
  613. sdesc->xlen = xt->sgl[0].size / SIRFSOC_DMA_WORD_LEN;
  614. sdesc->width = (xt->sgl[0].size + xt->sgl[0].icg) /
  615. SIRFSOC_DMA_WORD_LEN;
  616. sdesc->ylen = xt->numf - 1;
  617. if (xt->dir == DMA_MEM_TO_DEV) {
  618. sdesc->addr = xt->src_start;
  619. sdesc->dir = 1;
  620. } else {
  621. sdesc->addr = xt->dst_start;
  622. sdesc->dir = 0;
  623. }
  624. list_add_tail(&sdesc->node, &schan->prepared);
  625. } else {
  626. pr_err("sirfsoc DMA Invalid xfer\n");
  627. ret = -EINVAL;
  628. goto err_xfer;
  629. }
  630. spin_unlock_irqrestore(&schan->lock, iflags);
  631. return &sdesc->desc;
  632. err_xfer:
  633. spin_unlock_irqrestore(&schan->lock, iflags);
  634. no_desc:
  635. err_dir:
  636. return ERR_PTR(ret);
  637. }
  638. static struct dma_async_tx_descriptor *
  639. sirfsoc_dma_prep_cyclic(struct dma_chan *chan, dma_addr_t addr,
  640. size_t buf_len, size_t period_len,
  641. enum dma_transfer_direction direction, unsigned long flags)
  642. {
  643. struct sirfsoc_dma_chan *schan = dma_chan_to_sirfsoc_dma_chan(chan);
  644. struct sirfsoc_dma_desc *sdesc = NULL;
  645. unsigned long iflags;
  646. /*
  647. * we only support cycle transfer with 2 period
  648. * If the X-length is set to 0, it would be the loop mode.
  649. * The DMA address keeps increasing until reaching the end of a loop
  650. * area whose size is defined by (DMA_WIDTH x (Y_LENGTH + 1)). Then
  651. * the DMA address goes back to the beginning of this area.
  652. * In loop mode, the DMA data region is divided into two parts, BUFA
  653. * and BUFB. DMA controller generates interrupts twice in each loop:
  654. * when the DMA address reaches the end of BUFA or the end of the
  655. * BUFB
  656. */
  657. if (buf_len != 2 * period_len)
  658. return ERR_PTR(-EINVAL);
  659. /* Get free descriptor */
  660. spin_lock_irqsave(&schan->lock, iflags);
  661. if (!list_empty(&schan->free)) {
  662. sdesc = list_first_entry(&schan->free, struct sirfsoc_dma_desc,
  663. node);
  664. list_del(&sdesc->node);
  665. }
  666. spin_unlock_irqrestore(&schan->lock, iflags);
  667. if (!sdesc)
  668. return NULL;
  669. /* Place descriptor in prepared list */
  670. spin_lock_irqsave(&schan->lock, iflags);
  671. sdesc->addr = addr;
  672. sdesc->cyclic = 1;
  673. sdesc->xlen = 0;
  674. sdesc->ylen = buf_len / SIRFSOC_DMA_WORD_LEN - 1;
  675. sdesc->width = 1;
  676. list_add_tail(&sdesc->node, &schan->prepared);
  677. spin_unlock_irqrestore(&schan->lock, iflags);
  678. return &sdesc->desc;
  679. }
  680. /*
  681. * The DMA controller consists of 16 independent DMA channels.
  682. * Each channel is allocated to a different function
  683. */
  684. bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id)
  685. {
  686. unsigned int ch_nr = (unsigned int) chan_id;
  687. if (ch_nr == chan->chan_id +
  688. chan->device->dev_id * SIRFSOC_DMA_CHANNELS)
  689. return true;
  690. return false;
  691. }
  692. EXPORT_SYMBOL(sirfsoc_dma_filter_id);
  693. #define SIRFSOC_DMA_BUSWIDTHS \
  694. (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
  695. BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
  696. BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
  697. BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
  698. BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
  699. static struct dma_chan *of_dma_sirfsoc_xlate(struct of_phandle_args *dma_spec,
  700. struct of_dma *ofdma)
  701. {
  702. struct sirfsoc_dma *sdma = ofdma->of_dma_data;
  703. unsigned int request = dma_spec->args[0];
  704. if (request >= SIRFSOC_DMA_CHANNELS)
  705. return NULL;
  706. return dma_get_slave_channel(&sdma->channels[request].chan);
  707. }
  708. static int sirfsoc_dma_probe(struct platform_device *op)
  709. {
  710. struct device_node *dn = op->dev.of_node;
  711. struct device *dev = &op->dev;
  712. struct dma_device *dma;
  713. struct sirfsoc_dma *sdma;
  714. struct sirfsoc_dma_chan *schan;
  715. struct sirfsoc_dmadata *data;
  716. struct resource res;
  717. ulong regs_start, regs_size;
  718. u32 id;
  719. int ret, i;
  720. sdma = devm_kzalloc(dev, sizeof(*sdma), GFP_KERNEL);
  721. if (!sdma)
  722. return -ENOMEM;
  723. data = (struct sirfsoc_dmadata *)
  724. (of_match_device(op->dev.driver->of_match_table,
  725. &op->dev)->data);
  726. sdma->exec_desc = data->exec;
  727. sdma->type = data->type;
  728. if (of_property_read_u32(dn, "cell-index", &id)) {
  729. dev_err(dev, "Fail to get DMAC index\n");
  730. return -ENODEV;
  731. }
  732. sdma->irq = irq_of_parse_and_map(dn, 0);
  733. if (!sdma->irq) {
  734. dev_err(dev, "Error mapping IRQ!\n");
  735. return -EINVAL;
  736. }
  737. sdma->clk = devm_clk_get(dev, NULL);
  738. if (IS_ERR(sdma->clk)) {
  739. dev_err(dev, "failed to get a clock.\n");
  740. return PTR_ERR(sdma->clk);
  741. }
  742. ret = of_address_to_resource(dn, 0, &res);
  743. if (ret) {
  744. dev_err(dev, "Error parsing memory region!\n");
  745. goto irq_dispose;
  746. }
  747. regs_start = res.start;
  748. regs_size = resource_size(&res);
  749. sdma->base = devm_ioremap(dev, regs_start, regs_size);
  750. if (!sdma->base) {
  751. dev_err(dev, "Error mapping memory region!\n");
  752. ret = -ENOMEM;
  753. goto irq_dispose;
  754. }
  755. ret = request_irq(sdma->irq, &sirfsoc_dma_irq, 0, DRV_NAME, sdma);
  756. if (ret) {
  757. dev_err(dev, "Error requesting IRQ!\n");
  758. ret = -EINVAL;
  759. goto irq_dispose;
  760. }
  761. dma = &sdma->dma;
  762. dma->dev = dev;
  763. dma->device_alloc_chan_resources = sirfsoc_dma_alloc_chan_resources;
  764. dma->device_free_chan_resources = sirfsoc_dma_free_chan_resources;
  765. dma->device_issue_pending = sirfsoc_dma_issue_pending;
  766. dma->device_config = sirfsoc_dma_slave_config;
  767. dma->device_pause = sirfsoc_dma_pause_chan;
  768. dma->device_resume = sirfsoc_dma_resume_chan;
  769. dma->device_terminate_all = sirfsoc_dma_terminate_all;
  770. dma->device_tx_status = sirfsoc_dma_tx_status;
  771. dma->device_prep_interleaved_dma = sirfsoc_dma_prep_interleaved;
  772. dma->device_prep_dma_cyclic = sirfsoc_dma_prep_cyclic;
  773. dma->src_addr_widths = SIRFSOC_DMA_BUSWIDTHS;
  774. dma->dst_addr_widths = SIRFSOC_DMA_BUSWIDTHS;
  775. dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
  776. INIT_LIST_HEAD(&dma->channels);
  777. dma_cap_set(DMA_SLAVE, dma->cap_mask);
  778. dma_cap_set(DMA_CYCLIC, dma->cap_mask);
  779. dma_cap_set(DMA_INTERLEAVE, dma->cap_mask);
  780. dma_cap_set(DMA_PRIVATE, dma->cap_mask);
  781. for (i = 0; i < SIRFSOC_DMA_CHANNELS; i++) {
  782. schan = &sdma->channels[i];
  783. schan->chan.device = dma;
  784. dma_cookie_init(&schan->chan);
  785. INIT_LIST_HEAD(&schan->free);
  786. INIT_LIST_HEAD(&schan->prepared);
  787. INIT_LIST_HEAD(&schan->queued);
  788. INIT_LIST_HEAD(&schan->active);
  789. INIT_LIST_HEAD(&schan->completed);
  790. spin_lock_init(&schan->lock);
  791. list_add_tail(&schan->chan.device_node, &dma->channels);
  792. }
  793. tasklet_setup(&sdma->tasklet, sirfsoc_dma_tasklet);
  794. /* Register DMA engine */
  795. dev_set_drvdata(dev, sdma);
  796. ret = dma_async_device_register(dma);
  797. if (ret)
  798. goto free_irq;
  799. /* Device-tree DMA controller registration */
  800. ret = of_dma_controller_register(dn, of_dma_sirfsoc_xlate, sdma);
  801. if (ret) {
  802. dev_err(dev, "failed to register DMA controller\n");
  803. goto unreg_dma_dev;
  804. }
  805. pm_runtime_enable(&op->dev);
  806. dev_info(dev, "initialized SIRFSOC DMAC driver\n");
  807. return 0;
  808. unreg_dma_dev:
  809. dma_async_device_unregister(dma);
  810. free_irq:
  811. free_irq(sdma->irq, sdma);
  812. irq_dispose:
  813. irq_dispose_mapping(sdma->irq);
  814. return ret;
  815. }
  816. static int sirfsoc_dma_remove(struct platform_device *op)
  817. {
  818. struct device *dev = &op->dev;
  819. struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
  820. of_dma_controller_free(op->dev.of_node);
  821. dma_async_device_unregister(&sdma->dma);
  822. free_irq(sdma->irq, sdma);
  823. tasklet_kill(&sdma->tasklet);
  824. irq_dispose_mapping(sdma->irq);
  825. pm_runtime_disable(&op->dev);
  826. if (!pm_runtime_status_suspended(&op->dev))
  827. sirfsoc_dma_runtime_suspend(&op->dev);
  828. return 0;
  829. }
  830. static int __maybe_unused sirfsoc_dma_runtime_suspend(struct device *dev)
  831. {
  832. struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
  833. clk_disable_unprepare(sdma->clk);
  834. return 0;
  835. }
  836. static int __maybe_unused sirfsoc_dma_runtime_resume(struct device *dev)
  837. {
  838. struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
  839. int ret;
  840. ret = clk_prepare_enable(sdma->clk);
  841. if (ret < 0) {
  842. dev_err(dev, "clk_enable failed: %d\n", ret);
  843. return ret;
  844. }
  845. return 0;
  846. }
  847. static int __maybe_unused sirfsoc_dma_pm_suspend(struct device *dev)
  848. {
  849. struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
  850. struct sirfsoc_dma_regs *save = &sdma->regs_save;
  851. struct sirfsoc_dma_chan *schan;
  852. int ch;
  853. int ret;
  854. int count;
  855. u32 int_offset;
  856. /*
  857. * if we were runtime-suspended before, resume to enable clock
  858. * before accessing register
  859. */
  860. if (pm_runtime_status_suspended(dev)) {
  861. ret = sirfsoc_dma_runtime_resume(dev);
  862. if (ret < 0)
  863. return ret;
  864. }
  865. if (sdma->type == SIRFSOC_DMA_VER_A7V2) {
  866. count = 1;
  867. int_offset = SIRFSOC_DMA_INT_EN_ATLAS7;
  868. } else {
  869. count = SIRFSOC_DMA_CHANNELS;
  870. int_offset = SIRFSOC_DMA_INT_EN;
  871. }
  872. /*
  873. * DMA controller will lose all registers while suspending
  874. * so we need to save registers for active channels
  875. */
  876. for (ch = 0; ch < count; ch++) {
  877. schan = &sdma->channels[ch];
  878. if (list_empty(&schan->active))
  879. continue;
  880. save->ctrl[ch] = readl_relaxed(sdma->base +
  881. ch * 0x10 + SIRFSOC_DMA_CH_CTRL);
  882. }
  883. save->interrupt_en = readl_relaxed(sdma->base + int_offset);
  884. /* Disable clock */
  885. sirfsoc_dma_runtime_suspend(dev);
  886. return 0;
  887. }
  888. static int __maybe_unused sirfsoc_dma_pm_resume(struct device *dev)
  889. {
  890. struct sirfsoc_dma *sdma = dev_get_drvdata(dev);
  891. struct sirfsoc_dma_regs *save = &sdma->regs_save;
  892. struct sirfsoc_dma_desc *sdesc;
  893. struct sirfsoc_dma_chan *schan;
  894. int ch;
  895. int ret;
  896. int count;
  897. u32 int_offset;
  898. u32 width_offset;
  899. /* Enable clock before accessing register */
  900. ret = sirfsoc_dma_runtime_resume(dev);
  901. if (ret < 0)
  902. return ret;
  903. if (sdma->type == SIRFSOC_DMA_VER_A7V2) {
  904. count = 1;
  905. int_offset = SIRFSOC_DMA_INT_EN_ATLAS7;
  906. width_offset = SIRFSOC_DMA_WIDTH_ATLAS7;
  907. } else {
  908. count = SIRFSOC_DMA_CHANNELS;
  909. int_offset = SIRFSOC_DMA_INT_EN;
  910. width_offset = SIRFSOC_DMA_WIDTH_0;
  911. }
  912. writel_relaxed(save->interrupt_en, sdma->base + int_offset);
  913. for (ch = 0; ch < count; ch++) {
  914. schan = &sdma->channels[ch];
  915. if (list_empty(&schan->active))
  916. continue;
  917. sdesc = list_first_entry(&schan->active,
  918. struct sirfsoc_dma_desc,
  919. node);
  920. writel_relaxed(sdesc->width,
  921. sdma->base + width_offset + ch * 4);
  922. writel_relaxed(sdesc->xlen,
  923. sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_XLEN);
  924. writel_relaxed(sdesc->ylen,
  925. sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_YLEN);
  926. writel_relaxed(save->ctrl[ch],
  927. sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_CTRL);
  928. if (sdma->type == SIRFSOC_DMA_VER_A7V2) {
  929. writel_relaxed(sdesc->addr,
  930. sdma->base + SIRFSOC_DMA_CH_ADDR);
  931. } else {
  932. writel_relaxed(sdesc->addr >> 2,
  933. sdma->base + ch * 0x10 + SIRFSOC_DMA_CH_ADDR);
  934. }
  935. }
  936. /* if we were runtime-suspended before, suspend again */
  937. if (pm_runtime_status_suspended(dev))
  938. sirfsoc_dma_runtime_suspend(dev);
  939. return 0;
  940. }
  941. static const struct dev_pm_ops sirfsoc_dma_pm_ops = {
  942. SET_RUNTIME_PM_OPS(sirfsoc_dma_runtime_suspend, sirfsoc_dma_runtime_resume, NULL)
  943. SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_dma_pm_suspend, sirfsoc_dma_pm_resume)
  944. };
  945. static struct sirfsoc_dmadata sirfsoc_dmadata_a6 = {
  946. .exec = sirfsoc_dma_execute_hw_a6,
  947. .type = SIRFSOC_DMA_VER_A6,
  948. };
  949. static struct sirfsoc_dmadata sirfsoc_dmadata_a7v1 = {
  950. .exec = sirfsoc_dma_execute_hw_a7v1,
  951. .type = SIRFSOC_DMA_VER_A7V1,
  952. };
  953. static struct sirfsoc_dmadata sirfsoc_dmadata_a7v2 = {
  954. .exec = sirfsoc_dma_execute_hw_a7v2,
  955. .type = SIRFSOC_DMA_VER_A7V2,
  956. };
  957. static const struct of_device_id sirfsoc_dma_match[] = {
  958. { .compatible = "sirf,prima2-dmac", .data = &sirfsoc_dmadata_a6,},
  959. { .compatible = "sirf,atlas7-dmac", .data = &sirfsoc_dmadata_a7v1,},
  960. { .compatible = "sirf,atlas7-dmac-v2", .data = &sirfsoc_dmadata_a7v2,},
  961. {},
  962. };
  963. MODULE_DEVICE_TABLE(of, sirfsoc_dma_match);
  964. static struct platform_driver sirfsoc_dma_driver = {
  965. .probe = sirfsoc_dma_probe,
  966. .remove = sirfsoc_dma_remove,
  967. .driver = {
  968. .name = DRV_NAME,
  969. .pm = &sirfsoc_dma_pm_ops,
  970. .of_match_table = sirfsoc_dma_match,
  971. },
  972. };
  973. static __init int sirfsoc_dma_init(void)
  974. {
  975. return platform_driver_register(&sirfsoc_dma_driver);
  976. }
  977. static void __exit sirfsoc_dma_exit(void)
  978. {
  979. platform_driver_unregister(&sirfsoc_dma_driver);
  980. }
  981. subsys_initcall(sirfsoc_dma_init);
  982. module_exit(sirfsoc_dma_exit);
  983. MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>");
  984. MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
  985. MODULE_DESCRIPTION("SIRFSOC DMA control driver");
  986. MODULE_LICENSE("GPL v2");