hidma_mgmt.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Qualcomm Technologies HIDMA DMA engine Management interface
  4. *
  5. * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
  6. */
  7. #include <linux/dmaengine.h>
  8. #include <linux/acpi.h>
  9. #include <linux/of.h>
  10. #include <linux/property.h>
  11. #include <linux/of_address.h>
  12. #include <linux/of_irq.h>
  13. #include <linux/of_platform.h>
  14. #include <linux/module.h>
  15. #include <linux/uaccess.h>
  16. #include <linux/slab.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/bitops.h>
  19. #include <linux/dma-mapping.h>
  20. #include "hidma_mgmt.h"
  21. #define HIDMA_QOS_N_OFFSET 0x700
  22. #define HIDMA_CFG_OFFSET 0x400
  23. #define HIDMA_MAX_BUS_REQ_LEN_OFFSET 0x41C
  24. #define HIDMA_MAX_XACTIONS_OFFSET 0x420
  25. #define HIDMA_HW_VERSION_OFFSET 0x424
  26. #define HIDMA_CHRESET_TIMEOUT_OFFSET 0x418
  27. #define HIDMA_MAX_WR_XACTIONS_MASK GENMASK(4, 0)
  28. #define HIDMA_MAX_RD_XACTIONS_MASK GENMASK(4, 0)
  29. #define HIDMA_WEIGHT_MASK GENMASK(6, 0)
  30. #define HIDMA_MAX_BUS_REQ_LEN_MASK GENMASK(15, 0)
  31. #define HIDMA_CHRESET_TIMEOUT_MASK GENMASK(19, 0)
  32. #define HIDMA_MAX_WR_XACTIONS_BIT_POS 16
  33. #define HIDMA_MAX_BUS_WR_REQ_BIT_POS 16
  34. #define HIDMA_WRR_BIT_POS 8
  35. #define HIDMA_PRIORITY_BIT_POS 15
  36. #define HIDMA_AUTOSUSPEND_TIMEOUT 2000
  37. #define HIDMA_MAX_CHANNEL_WEIGHT 15
  38. static unsigned int max_write_request;
  39. module_param(max_write_request, uint, 0644);
  40. MODULE_PARM_DESC(max_write_request,
  41. "maximum write burst (default: ACPI/DT value)");
  42. static unsigned int max_read_request;
  43. module_param(max_read_request, uint, 0644);
  44. MODULE_PARM_DESC(max_read_request,
  45. "maximum read burst (default: ACPI/DT value)");
  46. static unsigned int max_wr_xactions;
  47. module_param(max_wr_xactions, uint, 0644);
  48. MODULE_PARM_DESC(max_wr_xactions,
  49. "maximum number of write transactions (default: ACPI/DT value)");
  50. static unsigned int max_rd_xactions;
  51. module_param(max_rd_xactions, uint, 0644);
  52. MODULE_PARM_DESC(max_rd_xactions,
  53. "maximum number of read transactions (default: ACPI/DT value)");
  54. int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
  55. {
  56. unsigned int i;
  57. u32 val;
  58. if (!is_power_of_2(mgmtdev->max_write_request) ||
  59. (mgmtdev->max_write_request < 128) ||
  60. (mgmtdev->max_write_request > 1024)) {
  61. dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
  62. mgmtdev->max_write_request);
  63. return -EINVAL;
  64. }
  65. if (!is_power_of_2(mgmtdev->max_read_request) ||
  66. (mgmtdev->max_read_request < 128) ||
  67. (mgmtdev->max_read_request > 1024)) {
  68. dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
  69. mgmtdev->max_read_request);
  70. return -EINVAL;
  71. }
  72. if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
  73. dev_err(&mgmtdev->pdev->dev,
  74. "max_wr_xactions cannot be bigger than %ld\n",
  75. HIDMA_MAX_WR_XACTIONS_MASK);
  76. return -EINVAL;
  77. }
  78. if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
  79. dev_err(&mgmtdev->pdev->dev,
  80. "max_rd_xactions cannot be bigger than %ld\n",
  81. HIDMA_MAX_RD_XACTIONS_MASK);
  82. return -EINVAL;
  83. }
  84. for (i = 0; i < mgmtdev->dma_channels; i++) {
  85. if (mgmtdev->priority[i] > 1) {
  86. dev_err(&mgmtdev->pdev->dev,
  87. "priority can be 0 or 1\n");
  88. return -EINVAL;
  89. }
  90. if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
  91. dev_err(&mgmtdev->pdev->dev,
  92. "max value of weight can be %d.\n",
  93. HIDMA_MAX_CHANNEL_WEIGHT);
  94. return -EINVAL;
  95. }
  96. /* weight needs to be at least one */
  97. if (mgmtdev->weight[i] == 0)
  98. mgmtdev->weight[i] = 1;
  99. }
  100. pm_runtime_get_sync(&mgmtdev->pdev->dev);
  101. val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
  102. val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
  103. val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
  104. val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
  105. val |= mgmtdev->max_read_request;
  106. writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
  107. val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
  108. val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
  109. val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
  110. val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
  111. val |= mgmtdev->max_rd_xactions;
  112. writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
  113. mgmtdev->hw_version =
  114. readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
  115. mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
  116. mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
  117. for (i = 0; i < mgmtdev->dma_channels; i++) {
  118. u32 weight = mgmtdev->weight[i];
  119. u32 priority = mgmtdev->priority[i];
  120. val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
  121. val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
  122. val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
  123. val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
  124. val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
  125. writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
  126. }
  127. val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
  128. val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
  129. val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
  130. writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
  131. pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
  132. pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
  133. return 0;
  134. }
  135. EXPORT_SYMBOL_GPL(hidma_mgmt_setup);
  136. static int hidma_mgmt_probe(struct platform_device *pdev)
  137. {
  138. struct hidma_mgmt_dev *mgmtdev;
  139. struct resource *res;
  140. void __iomem *virtaddr;
  141. int irq;
  142. int rc;
  143. u32 val;
  144. pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
  145. pm_runtime_use_autosuspend(&pdev->dev);
  146. pm_runtime_set_active(&pdev->dev);
  147. pm_runtime_enable(&pdev->dev);
  148. pm_runtime_get_sync(&pdev->dev);
  149. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  150. virtaddr = devm_ioremap_resource(&pdev->dev, res);
  151. if (IS_ERR(virtaddr)) {
  152. rc = -ENOMEM;
  153. goto out;
  154. }
  155. irq = platform_get_irq(pdev, 0);
  156. if (irq < 0) {
  157. rc = irq;
  158. goto out;
  159. }
  160. mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
  161. if (!mgmtdev) {
  162. rc = -ENOMEM;
  163. goto out;
  164. }
  165. mgmtdev->pdev = pdev;
  166. mgmtdev->addrsize = resource_size(res);
  167. mgmtdev->virtaddr = virtaddr;
  168. rc = device_property_read_u32(&pdev->dev, "dma-channels",
  169. &mgmtdev->dma_channels);
  170. if (rc) {
  171. dev_err(&pdev->dev, "number of channels missing\n");
  172. goto out;
  173. }
  174. rc = device_property_read_u32(&pdev->dev,
  175. "channel-reset-timeout-cycles",
  176. &mgmtdev->chreset_timeout_cycles);
  177. if (rc) {
  178. dev_err(&pdev->dev, "channel reset timeout missing\n");
  179. goto out;
  180. }
  181. rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",
  182. &mgmtdev->max_write_request);
  183. if (rc) {
  184. dev_err(&pdev->dev, "max-write-burst-bytes missing\n");
  185. goto out;
  186. }
  187. if (max_write_request &&
  188. (max_write_request != mgmtdev->max_write_request)) {
  189. dev_info(&pdev->dev, "overriding max-write-burst-bytes: %d\n",
  190. max_write_request);
  191. mgmtdev->max_write_request = max_write_request;
  192. } else
  193. max_write_request = mgmtdev->max_write_request;
  194. rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",
  195. &mgmtdev->max_read_request);
  196. if (rc) {
  197. dev_err(&pdev->dev, "max-read-burst-bytes missing\n");
  198. goto out;
  199. }
  200. if (max_read_request &&
  201. (max_read_request != mgmtdev->max_read_request)) {
  202. dev_info(&pdev->dev, "overriding max-read-burst-bytes: %d\n",
  203. max_read_request);
  204. mgmtdev->max_read_request = max_read_request;
  205. } else
  206. max_read_request = mgmtdev->max_read_request;
  207. rc = device_property_read_u32(&pdev->dev, "max-write-transactions",
  208. &mgmtdev->max_wr_xactions);
  209. if (rc) {
  210. dev_err(&pdev->dev, "max-write-transactions missing\n");
  211. goto out;
  212. }
  213. if (max_wr_xactions &&
  214. (max_wr_xactions != mgmtdev->max_wr_xactions)) {
  215. dev_info(&pdev->dev, "overriding max-write-transactions: %d\n",
  216. max_wr_xactions);
  217. mgmtdev->max_wr_xactions = max_wr_xactions;
  218. } else
  219. max_wr_xactions = mgmtdev->max_wr_xactions;
  220. rc = device_property_read_u32(&pdev->dev, "max-read-transactions",
  221. &mgmtdev->max_rd_xactions);
  222. if (rc) {
  223. dev_err(&pdev->dev, "max-read-transactions missing\n");
  224. goto out;
  225. }
  226. if (max_rd_xactions &&
  227. (max_rd_xactions != mgmtdev->max_rd_xactions)) {
  228. dev_info(&pdev->dev, "overriding max-read-transactions: %d\n",
  229. max_rd_xactions);
  230. mgmtdev->max_rd_xactions = max_rd_xactions;
  231. } else
  232. max_rd_xactions = mgmtdev->max_rd_xactions;
  233. mgmtdev->priority = devm_kcalloc(&pdev->dev,
  234. mgmtdev->dma_channels,
  235. sizeof(*mgmtdev->priority),
  236. GFP_KERNEL);
  237. if (!mgmtdev->priority) {
  238. rc = -ENOMEM;
  239. goto out;
  240. }
  241. mgmtdev->weight = devm_kcalloc(&pdev->dev,
  242. mgmtdev->dma_channels,
  243. sizeof(*mgmtdev->weight), GFP_KERNEL);
  244. if (!mgmtdev->weight) {
  245. rc = -ENOMEM;
  246. goto out;
  247. }
  248. rc = hidma_mgmt_setup(mgmtdev);
  249. if (rc) {
  250. dev_err(&pdev->dev, "setup failed\n");
  251. goto out;
  252. }
  253. /* start the HW */
  254. val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
  255. val |= 1;
  256. writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
  257. rc = hidma_mgmt_init_sys(mgmtdev);
  258. if (rc) {
  259. dev_err(&pdev->dev, "sysfs setup failed\n");
  260. goto out;
  261. }
  262. dev_info(&pdev->dev,
  263. "HW rev: %d.%d @ %pa with %d physical channels\n",
  264. mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
  265. &res->start, mgmtdev->dma_channels);
  266. platform_set_drvdata(pdev, mgmtdev);
  267. pm_runtime_mark_last_busy(&pdev->dev);
  268. pm_runtime_put_autosuspend(&pdev->dev);
  269. return 0;
  270. out:
  271. pm_runtime_put_sync_suspend(&pdev->dev);
  272. pm_runtime_disable(&pdev->dev);
  273. return rc;
  274. }
  275. #if IS_ENABLED(CONFIG_ACPI)
  276. static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {
  277. {"QCOM8060"},
  278. {},
  279. };
  280. MODULE_DEVICE_TABLE(acpi, hidma_mgmt_acpi_ids);
  281. #endif
  282. static const struct of_device_id hidma_mgmt_match[] = {
  283. {.compatible = "qcom,hidma-mgmt-1.0",},
  284. {},
  285. };
  286. MODULE_DEVICE_TABLE(of, hidma_mgmt_match);
  287. static struct platform_driver hidma_mgmt_driver = {
  288. .probe = hidma_mgmt_probe,
  289. .driver = {
  290. .name = "hidma-mgmt",
  291. .of_match_table = hidma_mgmt_match,
  292. .acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),
  293. },
  294. };
  295. #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
  296. static int object_counter;
  297. static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
  298. {
  299. struct platform_device *pdev_parent = of_find_device_by_node(np);
  300. struct platform_device_info pdevinfo;
  301. struct device_node *child;
  302. struct resource *res;
  303. int ret = 0;
  304. /* allocate a resource array */
  305. res = kcalloc(3, sizeof(*res), GFP_KERNEL);
  306. if (!res)
  307. return -ENOMEM;
  308. for_each_available_child_of_node(np, child) {
  309. struct platform_device *new_pdev;
  310. ret = of_address_to_resource(child, 0, &res[0]);
  311. if (!ret)
  312. goto out;
  313. ret = of_address_to_resource(child, 1, &res[1]);
  314. if (!ret)
  315. goto out;
  316. ret = of_irq_to_resource(child, 0, &res[2]);
  317. if (ret <= 0)
  318. goto out;
  319. memset(&pdevinfo, 0, sizeof(pdevinfo));
  320. pdevinfo.fwnode = &child->fwnode;
  321. pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL;
  322. pdevinfo.name = child->name;
  323. pdevinfo.id = object_counter++;
  324. pdevinfo.res = res;
  325. pdevinfo.num_res = 3;
  326. pdevinfo.data = NULL;
  327. pdevinfo.size_data = 0;
  328. pdevinfo.dma_mask = DMA_BIT_MASK(64);
  329. new_pdev = platform_device_register_full(&pdevinfo);
  330. if (IS_ERR(new_pdev)) {
  331. ret = PTR_ERR(new_pdev);
  332. goto out;
  333. }
  334. new_pdev->dev.of_node = child;
  335. of_dma_configure(&new_pdev->dev, child, true);
  336. /*
  337. * It is assumed that calling of_msi_configure is safe on
  338. * platforms with or without MSI support.
  339. */
  340. of_msi_configure(&new_pdev->dev, child);
  341. }
  342. kfree(res);
  343. return ret;
  344. out:
  345. of_node_put(child);
  346. kfree(res);
  347. return ret;
  348. }
  349. #endif
  350. static int __init hidma_mgmt_init(void)
  351. {
  352. #if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
  353. struct device_node *child;
  354. for_each_matching_node(child, hidma_mgmt_match) {
  355. /* device tree based firmware here */
  356. hidma_mgmt_of_populate_channels(child);
  357. }
  358. #endif
  359. /*
  360. * We do not check for return value here, as it is assumed that
  361. * platform_driver_register must not fail. The reason for this is that
  362. * the (potential) hidma_mgmt_of_populate_channels calls above are not
  363. * cleaned up if it does fail, and to do this work is quite
  364. * complicated. In particular, various calls of of_address_to_resource,
  365. * of_irq_to_resource, platform_device_register_full, of_dma_configure,
  366. * and of_msi_configure which then call other functions and so on, must
  367. * be cleaned up - this is not a trivial exercise.
  368. *
  369. * Currently, this module is not intended to be unloaded, and there is
  370. * no module_exit function defined which does the needed cleanup. For
  371. * this reason, we have to assume success here.
  372. */
  373. platform_driver_register(&hidma_mgmt_driver);
  374. return 0;
  375. }
  376. module_init(hidma_mgmt_init);
  377. MODULE_LICENSE("GPL v2");