xor.h 3.5 KB

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  1. /*
  2. * 440SPe's XOR engines support header file
  3. *
  4. * 2006-2009 (C) DENX Software Engineering.
  5. *
  6. * Author: Yuri Tikhonov <yur@emcraft.com>
  7. *
  8. * This file is licensed under the term of the GNU General Public License
  9. * version 2. The program licensed "as is" without any warranty of any
  10. * kind, whether express or implied.
  11. */
  12. #ifndef _PPC440SPE_XOR_H
  13. #define _PPC440SPE_XOR_H
  14. #include <linux/types.h>
  15. /* Number of XOR engines available on the contoller */
  16. #define XOR_ENGINES_NUM 1
  17. /* Number of operands supported in the h/w */
  18. #define XOR_MAX_OPS 16
  19. /*
  20. * XOR Command Block Control Register bits
  21. */
  22. #define XOR_CBCR_LNK_BIT (1<<31) /* link present */
  23. #define XOR_CBCR_TGT_BIT (1<<30) /* target present */
  24. #define XOR_CBCR_CBCE_BIT (1<<29) /* command block compete enable */
  25. #define XOR_CBCR_RNZE_BIT (1<<28) /* result not zero enable */
  26. #define XOR_CBCR_XNOR_BIT (1<<15) /* XOR/XNOR */
  27. #define XOR_CDCR_OAC_MSK (0x7F) /* operand address count */
  28. /*
  29. * XORCore Status Register bits
  30. */
  31. #define XOR_SR_XCP_BIT (1<<31) /* core processing */
  32. #define XOR_SR_ICB_BIT (1<<17) /* invalid CB */
  33. #define XOR_SR_IC_BIT (1<<16) /* invalid command */
  34. #define XOR_SR_IPE_BIT (1<<15) /* internal parity error */
  35. #define XOR_SR_RNZ_BIT (1<<2) /* result not Zero */
  36. #define XOR_SR_CBC_BIT (1<<1) /* CB complete */
  37. #define XOR_SR_CBLC_BIT (1<<0) /* CB list complete */
  38. /*
  39. * XORCore Control Set and Reset Register bits
  40. */
  41. #define XOR_CRSR_XASR_BIT (1<<31) /* soft reset */
  42. #define XOR_CRSR_XAE_BIT (1<<30) /* enable */
  43. #define XOR_CRSR_RCBE_BIT (1<<29) /* refetch CB enable */
  44. #define XOR_CRSR_PAUS_BIT (1<<28) /* pause */
  45. #define XOR_CRSR_64BA_BIT (1<<27) /* 64/32 CB format */
  46. #define XOR_CRSR_CLP_BIT (1<<25) /* continue list processing */
  47. /*
  48. * XORCore Interrupt Enable Register
  49. */
  50. #define XOR_IE_ICBIE_BIT (1<<17) /* Invalid Command Block IRQ Enable */
  51. #define XOR_IE_ICIE_BIT (1<<16) /* Invalid Command IRQ Enable */
  52. #define XOR_IE_RPTIE_BIT (1<<14) /* Read PLB Timeout Error IRQ Enable */
  53. #define XOR_IE_CBCIE_BIT (1<<1) /* CB complete interrupt enable */
  54. #define XOR_IE_CBLCI_BIT (1<<0) /* CB list complete interrupt enable */
  55. /*
  56. * XOR Accelerator engine Command Block Type
  57. */
  58. struct xor_cb {
  59. /*
  60. * Basic 64-bit format XOR CB (Table 19-1, p.463, 440spe_um_1_22.pdf)
  61. */
  62. u32 cbc; /* control */
  63. u32 cbbc; /* byte count */
  64. u32 cbs; /* status */
  65. u8 pad0[4]; /* reserved */
  66. u32 cbtah; /* target address high */
  67. u32 cbtal; /* target address low */
  68. u32 cblah; /* link address high */
  69. u32 cblal; /* link address low */
  70. struct {
  71. u32 h;
  72. u32 l;
  73. } __attribute__ ((packed)) ops[16];
  74. } __attribute__ ((packed));
  75. /*
  76. * XOR hardware registers Table 19-3, UM 1.22
  77. */
  78. struct xor_regs {
  79. u32 op_ar[16][2]; /* operand address[0]-high,[1]-low registers */
  80. u8 pad0[352]; /* reserved */
  81. u32 cbcr; /* CB control register */
  82. u32 cbbcr; /* CB byte count register */
  83. u32 cbsr; /* CB status register */
  84. u8 pad1[4]; /* reserved */
  85. u32 cbtahr; /* operand target address high register */
  86. u32 cbtalr; /* operand target address low register */
  87. u32 cblahr; /* CB link address high register */
  88. u32 cblalr; /* CB link address low register */
  89. u32 crsr; /* control set register */
  90. u32 crrr; /* control reset register */
  91. u32 ccbahr; /* current CB address high register */
  92. u32 ccbalr; /* current CB address low register */
  93. u32 plbr; /* PLB configuration register */
  94. u32 ier; /* interrupt enable register */
  95. u32 pecr; /* parity error count register */
  96. u32 sr; /* status register */
  97. u32 revidr; /* revision ID register */
  98. };
  99. #endif /* _PPC440SPE_XOR_H */